2 * $Id: asic.c,v 1.16 2006-06-15 10:32:38 nkeynes Exp $
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE asic_module
28 #include "dreamcast.h"
29 #include "maple/maple.h"
30 #include "gdrom/ide.h"
36 * 1) Does changing the mask after event occurance result in the
37 * interrupt being delivered immediately?
38 * TODO: Logic diagram of ASIC event/interrupt logic.
40 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
41 * practically nothing is publicly known...
44 static void asic_check_cleared_events( void );
45 static void asic_init( void );
46 static void asic_reset( void );
47 static void asic_save_state( FILE *f );
48 static int asic_load_state( FILE *f );
50 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
51 NULL, asic_save_state, asic_load_state };
53 #define G2_BIT5_TICKS 8
54 #define G2_BIT4_TICKS 16
55 #define G2_BIT0_ON_TICKS 24
56 #define G2_BIT0_OFF_TICKS 24
58 struct asic_g2_state {
59 unsigned int bit5_off_timer;
60 unsigned int bit4_on_timer;
61 unsigned int bit4_off_timer;
62 unsigned int bit0_on_timer;
63 unsigned int bit0_off_timer;
66 static struct asic_g2_state g2_state;
68 static void asic_init( void )
70 register_io_region( &mmio_region_ASIC );
71 register_io_region( &mmio_region_EXTDMA );
72 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
76 static void asic_reset( void )
78 memset( &g2_state, 0, sizeof(g2_state) );
81 static void asic_save_state( FILE *f )
83 fwrite( &g2_state, sizeof(g2_state), 1, f );
86 static int asic_load_state( FILE *f )
88 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
95 /* FIXME: Handle rollover */
96 void asic_g2_write_word()
98 g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
99 if( g2_state.bit4_off_timer < sh4r.icount )
100 g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
101 g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
102 if( g2_state.bit0_off_timer < sh4r.icount ) {
103 g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
104 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
106 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
108 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
111 static uint32_t g2_read_status()
113 uint32_t val = MMIO_READ( ASIC, G2STATUS );
114 if( g2_state.bit5_off_timer <= sh4r.icount )
116 if( g2_state.bit4_off_timer <= sh4r.icount )
118 else if( g2_state.bit4_on_timer <= sh4r.icount )
120 if( g2_state.bit0_off_timer <= sh4r.icount )
122 else if( g2_state.bit0_on_timer <= sh4r.icount )
128 void asic_event( int event )
130 int offset = ((event&0x60)>>3);
131 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
133 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
134 intc_raise_interrupt( INT_IRQ13 );
135 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
136 intc_raise_interrupt( INT_IRQ11 );
137 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
138 intc_raise_interrupt( INT_IRQ9 );
141 void asic_clear_event( int event ) {
142 int offset = ((event&0x60)>>3);
143 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
144 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
146 asic_check_cleared_events();
149 void asic_check_cleared_events( )
151 int i, setA = 0, setB = 0, setC = 0;
153 for( i=0; i<3; i++ ) {
154 bits = MMIO_READ( ASIC, PIRQ0 + i );
155 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
156 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
157 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
160 intc_clear_interrupt( INT_IRQ13 );
162 intc_clear_interrupt( INT_IRQ11 );
164 intc_clear_interrupt( INT_IRQ9 );
168 void asic_ide_dma_transfer( )
170 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
171 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
172 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
174 uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
175 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
176 int dir = MMIO_READ( EXTDMA, IDEDMADIR );
178 uint32_t xfer = ide_read_data_dma( addr, length );
179 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
180 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
182 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
189 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
193 val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
197 /* Clear any interrupts */
198 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
199 asic_check_cleared_events();
202 MMIO_WRITE( ASIC, reg, val );
204 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
205 // WARN( "Maple request initiated at %08X, halting", maple_addr );
206 maple_handle_buffer( maple_addr );
207 MMIO_WRITE( ASIC, reg, 0 );
210 case PVRDMACTL: /* Initiate PVR DMA transfer */
211 MMIO_WRITE( ASIC, reg, val );
213 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
214 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
215 char *data = alloca( count );
216 uint32_t rcount = DMAC_get_buffer( 2, data, count );
217 if( rcount != count )
218 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
219 mem_copy_to_sh4( dest_addr, data, rcount );
220 asic_event( EVENT_PVR_DMA );
223 case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
224 MMIO_WRITE( ASIC, reg, val );
227 MMIO_WRITE( ASIC, reg, val );
228 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
229 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
233 int32_t mmio_region_ASIC_read( uint32_t reg )
255 val = MMIO_READ(ASIC, reg);
256 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
257 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
260 return g2_read_status();
262 val = MMIO_READ(ASIC, reg);
263 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
264 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
270 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
272 // WARN( "EXTDMA write %08X <= %08X", reg, val );
275 case IDEALTSTATUS: /* Device control */
276 ide_write_control( val );
279 ide_write_data_pio( val );
282 if( ide_can_write_regs() )
283 idereg.feature = (uint8_t)val;
286 if( ide_can_write_regs() )
287 idereg.count = (uint8_t)val;
290 if( ide_can_write_regs() )
291 idereg.lba0 = (uint8_t)val;
294 if( ide_can_write_regs() )
295 idereg.lba1 = (uint8_t)val;
298 if( ide_can_write_regs() )
299 idereg.lba2 = (uint8_t)val;
302 if( ide_can_write_regs() )
303 idereg.device = (uint8_t)val;
306 if( ide_can_write_regs() ) {
307 ide_write_command( (uint8_t)val );
311 MMIO_WRITE( EXTDMA, reg, val );
313 MMIO_WRITE( EXTDMA, reg, val );
314 asic_ide_dma_transfer( );
317 MMIO_WRITE( EXTDMA, reg, val );
321 MMIO_REGION_READ_FN( EXTDMA, reg )
328 case IDEDATA: return ide_read_data_pio( );
329 case IDEFEAT: return idereg.error;
330 case IDECOUNT:return idereg.count;
331 case IDELBA0: return idereg.disc;
332 case IDELBA1: return idereg.lba1;
333 case IDELBA2: return idereg.lba2;
334 case IDEDEV: return idereg.device;
336 val = ide_read_status();
339 val = MMIO_READ( EXTDMA, reg );
.