lxdream.org :: lxdream/src/sh4/sh4stat.c r671:a530ea88eebd

tree revision 671:a530ea88eebd

filename	src/sh4/sh4stat.c
changeset	671:a530ea88eebd
prev	561:533f6b478071
next	673:44c579439d73
author	nkeynes
date	Thu May 15 10:22:39 2008 +0000 (15 years ago)
permissions	-rw-r--r--
last change	Permanently add SH4 instruction statistics tracking (enabled with --enable-sh4stats)

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     1 /**

     2  * $Id$

     3  *

     4  * Support module for collecting instruction stats

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    19 #include "dream.h"

    20 #include "sh4stat.h"

    21 #include "sh4core.h"

    23 static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];

    24 static uint64_t sh4_stats_total;

    25 static const char *sh4_stats_names[] = {

    26     "???",

    27 "ADD Rm, Rn",

    28 "ADD #imm, Rn",

    29 "ADDC Rm, Rn",

    30 "ADDV Rm, Rn",

    31 "AND Rm, Rn",

    32 "AND #imm, R0",

    33 "AND.B #imm, @(R0, GBR)",

    34 "BF disp",

    35 "BF/S disp",

    36 "BRA disp",

    37 "BRAF Rn",

    38 "BSR disp",

    39 "BSRF Rn",

    40 "BT disp",

    41 "BT/S disp",

    42 "CLRMAC",

    43 "CLRS",

    44 "CLRT",

    45 "CMP/EQ Rm, Rn",

    46 "CMP/EQ #imm, R0",

    47 "CMP/GE Rm, Rn",

    48 "CMP/GT Rm, Rn",

    49 "CMP/HI Rm, Rn",

    50 "CMP/HS Rm, Rn",

    51 "CMP/PL Rn",

    52 "CMP/PZ Rn",

    53 "CMP/STR Rm, Rn",

    54 "DIV0S Rm, Rn",

    55 "DIV0U",

    56 "DIV1 Rm, Rn",

    57 "DMULS.L Rm, Rn",

    58 "DMULU.L Rm, Rn",

    59 "DT Rn",

    60 "EXTS.B Rm, Rn",

    61 "EXTS.W Rm, Rn",

    62 "EXTU.B Rm, Rn",

    63 "EXTU.W Rm, Rn",

    64 "FABS FRn",

    65 "FADD FRm, FRn",

    66 "FCMP/EQ FRm, FRn",

    67 "FCMP/GT FRm, FRn",

    68 "FCNVDS FRm, FPUL",

    69 "FCNVSD FPUL, FRn",

    70 "FDIV FRm, FRn",

    71 "FIPR FVm, FVn",

    72 "FLDS FRm, FPUL",

    73 "FLDI0 FRn",

    74 "FLDI1 FRn",

    75 "FLOAT FPUL, FRn",

    76 "FMAC FR0, FRm, FRn",

    77 "FMOV FRm, FRn",

    78 "FMOV FRm, @Rn",

    79 "FMOV FRm, @-Rn",

    80 "FMOV FRm, @(R0, Rn)",

    81 "FMOV @Rm, FRn",

    82 "FMOV @Rm+, FRn",

    83 "FMOV @(R0, Rm), FRn",

    84 "FMUL FRm, FRn",

    85 "FNEG FRn",

    86 "FRCHG",

    87 "FSCA FPUL, FRn",

    88 "FSCHG",

    89 "FSQRT FRn",

    90 "FSRRA FRn",

    91 "FSTS FPUL, FRn",

    92 "FSUB FRm, FRn",

    93 "FTRC FRm, FPUL",

    94 "FTRV XMTRX, FVn",

    95 "JMP @Rn",

    96 "JSR @Rn",

    97 "LDC Rm, SR",

    98 "LDC Rm, *",

    99 "LDC.L @Rm+, SR",

   100 "LDC.L @Rm+, *",

   101 "LDS Rm, *",

   102 "LDS.L @Rm+, *",

   103 "LDTLB",

   104 "MAC.L @Rm+, @Rn+",

   105 "MAC.W @Rm+, @Rn+",

   106 "MOV Rm, Rn",

   107 "MOV #imm, Rn",

   108 "MOV.B ...",

   109 "MOV.L ...",

   110 "MOV.L @(disp, PC)",

   111 "MOV.W ...",

   112 "MOVA @(disp, PC), R0",

   113 "MOVCA.L R0, @Rn",

   114 "MOVT Rn",

   115 "MUL.L Rm, Rn",

   116 "MULS.W Rm, Rn",

   117 "MULU.W Rm, Rn",

   118 "NEG Rm, Rn",

   119 "NEGC Rm, Rn",

   120 "NOP",

   121 "NOT Rm, Rn",

   122 "OCBI @Rn",

   123 "OCBP @Rn",

   124 "OCBWB @Rn",

   125 "OR Rm, Rn",

   126 "OR #imm, R0",

   127 "OR.B #imm, @(R0, GBR)",

   128 "PREF @Rn",

   129 "ROTCL Rn",

   130 "ROTCR Rn",

   131 "ROTL Rn",

   132 "ROTR Rn",

   133 "RTE",

   134 "RTS",

   135 "SETS",

   136 "SETT",

   137 "SHAD Rm, Rn",

   138 "SHAL Rn",

   139 "SHAR Rn",

   140 "SHLD Rm, Rn",

   141 "SHLL* Rn",

   142 "SHLR* Rn",

   143 "SLEEP",

   144 "STC SR, Rn",

   145 "STC *, Rn",

   146 "STC.L SR, @-Rn",

   147 "STC.L *, @-Rn",

   148 "STS *, Rn",

   149 "STS.L *, @-Rn",

   150 "SUB Rm, Rn",

   151 "SUBC Rm, Rn",

   152 "SUBV Rm, Rn",

   153 "SWAP.B Rm, Rn",

   154 "SWAP.W Rm, Rn",

   155 "TAS.B @Rn",

   156 "TRAPA #imm",

   157 "TST Rm, Rn",

   158 "TST #imm, R0",

   159 "TST.B #imm, @(R0, GBR)",

   160 "XOR Rm, Rn",

   161 "XOR #imm, R0",

   162 "XOR.B #imm, @(R0, GBR)",

   163 "XTRCT Rm, Rn",

   164 "UNDEF"

   165 };

   167 void sh4_stats_reset( void )

   168 {

   169     int i;

   170     for( i=0; i<= I_UNDEF; i++ ) {

   171 	sh4_stats[i] = 0;

   172     }

   173     sh4_stats_total = 0;

   174 }

   176 void sh4_stats_print( FILE *out )

   177 {

   178     int i;

   179     for( i=0; i<= I_UNDEF; i++ ) {

   180 	fprintf( out, "%-20s\t%d\t%.2f%%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );

   181     }

   182     fprintf( out, "Total: %lld\n", sh4_stats_total );

   183 }

   185 void sh4_stats_add( sh4_inst_id item )

   186 {

   187     sh4_stats[item]++;

   188     sh4_stats_total++;

   189 }

   191 void sh4_stats_add_by_pc( uint32_t pc )

   192 {

   193     uint16_t ir = sh4_read_word(pc);

   194 #define UNDEF() sh4_stats[0]++

   195         switch( (ir&0xF000) >> 12 ) {

   196             case 0x0:

   197                 switch( ir&0xF ) {

   198                     case 0x2:

   199                         switch( (ir&0x80) >> 7 ) {

   200                             case 0x0:

   201                                 switch( (ir&0x70) >> 4 ) {

   202                                     case 0x0:

   203                                         { /* STC SR, Rn */

   204                                         uint32_t Rn = ((ir>>8)&0xF);

   205                                         sh4_stats[I_STCSR]++;

   206                                         }

   207                                         break;

   208                                     case 0x1:

   209                                         { /* STC GBR, Rn */

   210                                         uint32_t Rn = ((ir>>8)&0xF);

   211                                         sh4_stats[I_STC]++;

   212                                         }

   213                                         break;

   214                                     case 0x2:

   215                                         { /* STC VBR, Rn */

   216                                         uint32_t Rn = ((ir>>8)&0xF);

   217                                         sh4_stats[I_STC]++;

   218                                         }

   219                                         break;

   220                                     case 0x3:

   221                                         { /* STC SSR, Rn */

   222                                         uint32_t Rn = ((ir>>8)&0xF);

   223                                         sh4_stats[I_STC]++;

   224                                         }

   225                                         break;

   226                                     case 0x4:

   227                                         { /* STC SPC, Rn */

   228                                         uint32_t Rn = ((ir>>8)&0xF);

   229                                         sh4_stats[I_STC]++;

   230                                         }

   231                                         break;

   232                                     default:

   233                                         UNDEF();

   234                                         break;

   235                                 }

   236                                 break;

   237                             case 0x1:

   238                                 { /* STC Rm_BANK, Rn */

   239                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   240                                 sh4_stats[I_STC]++;

   241                                 }

   242                                 break;

   243                         }

   244                         break;

   245                     case 0x3:

   246                         switch( (ir&0xF0) >> 4 ) {

   247                             case 0x0:

   248                                 { /* BSRF Rn */

   249                                 uint32_t Rn = ((ir>>8)&0xF);

   250                                 sh4_stats[I_BSRF]++;

   251                                 }

   252                                 break;

   253                             case 0x2:

   254                                 { /* BRAF Rn */

   255                                 uint32_t Rn = ((ir>>8)&0xF);

   256                                 sh4_stats[I_BRAF]++;

   257                                 }

   258                                 break;

   259                             case 0x8:

   260                                 { /* PREF @Rn */

   261                                 uint32_t Rn = ((ir>>8)&0xF);

   262                                 sh4_stats[I_PREF]++;

   263                                 }

   264                                 break;

   265                             case 0x9:

   266                                 { /* OCBI @Rn */

   267                                 uint32_t Rn = ((ir>>8)&0xF);

   268                                 sh4_stats[I_OCBI]++;

   269                                 }

   270                                 break;

   271                             case 0xA:

   272                                 { /* OCBP @Rn */

   273                                 uint32_t Rn = ((ir>>8)&0xF);

   274                                 sh4_stats[I_OCBP]++;

   275                                 }

   276                                 break;

   277                             case 0xB:

   278                                 { /* OCBWB @Rn */

   279                                 uint32_t Rn = ((ir>>8)&0xF);

   280                                 sh4_stats[I_OCBWB]++;

   281                                 }

   282                                 break;

   283                             case 0xC:

   284                                 { /* MOVCA.L R0, @Rn */

   285                                 uint32_t Rn = ((ir>>8)&0xF);

   286                                 sh4_stats[I_MOVCA]++;

   287                                 }

   288                                 break;

   289                             default:

   290                                 UNDEF();

   291                                 break;

   292                         }

   293                         break;

   294                     case 0x4:

   295                         { /* MOV.B Rm, @(R0, Rn) */

   296                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   297                         sh4_stats[I_MOVB]++;

   298                         }

   299                         break;

   300                     case 0x5:

   301                         { /* MOV.W Rm, @(R0, Rn) */

   302                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   303                         sh4_stats[I_MOVW]++;

   304                         }

   305                         break;

   306                     case 0x6:

   307                         { /* MOV.L Rm, @(R0, Rn) */

   308                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   309                         sh4_stats[I_MOVL]++;

   310                         }

   311                         break;

   312                     case 0x7:

   313                         { /* MUL.L Rm, Rn */

   314                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   315                         sh4_stats[I_MULL]++;

   316                         }

   317                         break;

   318                     case 0x8:

   319                         switch( (ir&0xFF0) >> 4 ) {

   320                             case 0x0:

   321                                 { /* CLRT */

   322                                 sh4_stats[I_CLRT]++;

   323                                 }

   324                                 break;

   325                             case 0x1:

   326                                 { /* SETT */

   327                                 sh4_stats[I_SETT]++;

   328                                 }

   329                                 break;

   330                             case 0x2:

   331                                 { /* CLRMAC */

   332                                 sh4_stats[I_CLRMAC]++;

   333                                 }

   334                                 break;

   335                             case 0x3:

   336                                 { /* LDTLB */

   337                                 sh4_stats[I_LDTLB]++;

   338                                 }

   339                                 break;

   340                             case 0x4:

   341                                 { /* CLRS */

   342                                 sh4_stats[I_CLRS]++;

   343                                 }

   344                                 break;

   345                             case 0x5:

   346                                 { /* SETS */

   347                                 sh4_stats[I_SETS]++;

   348                                 }

   349                                 break;

   350                             default:

   351                                 UNDEF();

   352                                 break;

   353                         }

   354                         break;

   355                     case 0x9:

   356                         switch( (ir&0xF0) >> 4 ) {

   357                             case 0x0:

   358                                 { /* NOP */

   359                                 sh4_stats[I_NOP]++;

   360                                 }

   361                                 break;

   362                             case 0x1:

   363                                 { /* DIV0U */

   364                                 sh4_stats[I_DIV0U]++;

   365                                 }

   366                                 break;

   367                             case 0x2:

   368                                 { /* MOVT Rn */

   369                                 uint32_t Rn = ((ir>>8)&0xF);

   370                                 sh4_stats[I_MOVT]++;

   371                                 }

   372                                 break;

   373                             default:

   374                                 UNDEF();

   375                                 break;

   376                         }

   377                         break;

   378                     case 0xA:

   379                         switch( (ir&0xF0) >> 4 ) {

   380                             case 0x0:

   381                                 { /* STS MACH, Rn */

   382                                 uint32_t Rn = ((ir>>8)&0xF);

   383                                 sh4_stats[I_STS]++;

   384                                 }

   385                                 break;

   386                             case 0x1:

   387                                 { /* STS MACL, Rn */

   388                                 uint32_t Rn = ((ir>>8)&0xF);

   389                                 sh4_stats[I_STS]++;

   390                                 }

   391                                 break;

   392                             case 0x2:

   393                                 { /* STS PR, Rn */

   394                                 uint32_t Rn = ((ir>>8)&0xF);

   395                                 sh4_stats[I_STS]++;

   396                                 }

   397                                 break;

   398                             case 0x3:

   399                                 { /* STC SGR, Rn */

   400                                 uint32_t Rn = ((ir>>8)&0xF);

   401                                 sh4_stats[I_STC]++;

   402                                 }

   403                                 break;

   404                             case 0x5:

   405                                 { /* STS FPUL, Rn */

   406                                 uint32_t Rn = ((ir>>8)&0xF);

   407                                 sh4_stats[I_STS]++;

   408                                 }

   409                                 break;

   410                             case 0x6:

   411                                 { /* STS FPSCR, Rn */

   412                                 uint32_t Rn = ((ir>>8)&0xF);

   413                                 sh4_stats[I_STS]++;

   414                                 }

   415                                 break;

   416                             case 0xF:

   417                                 { /* STC DBR, Rn */

   418                                 uint32_t Rn = ((ir>>8)&0xF);

   419                                 sh4_stats[I_STC]++;

   420                                 }

   421                                 break;

   422                             default:

   423                                 UNDEF();

   424                                 break;

   425                         }

   426                         break;

   427                     case 0xB:

   428                         switch( (ir&0xFF0) >> 4 ) {

   429                             case 0x0:

   430                                 { /* RTS */

   431                                 sh4_stats[I_RTS]++;

   432                                 }

   433                                 break;

   434                             case 0x1:

   435                                 { /* SLEEP */

   436                                 sh4_stats[I_SLEEP]++;

   437                                 }

   438                                 break;

   439                             case 0x2:

   440                                 { /* RTE */

   441                                 sh4_stats[I_RTE]++;

   442                                 }

   443                                 break;

   444                             default:

   445                                 UNDEF();

   446                                 break;

   447                         }

   448                         break;

   449                     case 0xC:

   450                         { /* MOV.B @(R0, Rm), Rn */

   451                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   452                         sh4_stats[I_MOVB]++;

   453                         }

   454                         break;

   455                     case 0xD:

   456                         { /* MOV.W @(R0, Rm), Rn */

   457                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   458                         sh4_stats[I_MOVW]++;

   459                         }

   460                         break;

   461                     case 0xE:

   462                         { /* MOV.L @(R0, Rm), Rn */

   463                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   464                         sh4_stats[I_MOVL]++;

   465                         }

   466                         break;

   467                     case 0xF:

   468                         { /* MAC.L @Rm+, @Rn+ */

   469                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   470                         sh4_stats[I_MACL]++;

   471                         }

   472                         break;

   473                     default:

   474                         UNDEF();

   475                         break;

   476                 }

   477                 break;

   478             case 0x1:

   479                 { /* MOV.L Rm, @(disp, Rn) */

   480                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   481                 sh4_stats[I_MOVL]++;

   482                 }

   483                 break;

   484             case 0x2:

   485                 switch( ir&0xF ) {

   486                     case 0x0:

   487                         { /* MOV.B Rm, @Rn */

   488                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   489                         sh4_stats[I_MOVB]++;

   490                         }

   491                         break;

   492                     case 0x1:

   493                         { /* MOV.W Rm, @Rn */

   494                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   495                         sh4_stats[I_MOVW]++;

   496                         }

   497                         break;

   498                     case 0x2:

   499                         { /* MOV.L Rm, @Rn */

   500                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   501                         sh4_stats[I_MOVL]++;

   502                         }

   503                         break;

   504                     case 0x4:

   505                         { /* MOV.B Rm, @-Rn */

   506                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   507                         sh4_stats[I_MOVB]++;

   508                         }

   509                         break;

   510                     case 0x5:

   511                         { /* MOV.W Rm, @-Rn */

   512                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   513                         sh4_stats[I_MOVW]++;

   514                         }

   515                         break;

   516                     case 0x6:

   517                         { /* MOV.L Rm, @-Rn */

   518                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   519                         sh4_stats[I_MOVL]++;

   520                         }

   521                         break;

   522                     case 0x7:

   523                         { /* DIV0S Rm, Rn */

   524                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   525                         sh4_stats[I_DIV0S]++;

   526                         }

   527                         break;

   528                     case 0x8:

   529                         { /* TST Rm, Rn */

   530                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   531                         sh4_stats[I_TST]++;

   532                         }

   533                         break;

   534                     case 0x9:

   535                         { /* AND Rm, Rn */

   536                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   537                         sh4_stats[I_AND]++;

   538                         }

   539                         break;

   540                     case 0xA:

   541                         { /* XOR Rm, Rn */

   542                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   543                         sh4_stats[I_XOR]++;

   544                         }

   545                         break;

   546                     case 0xB:

   547                         { /* OR Rm, Rn */

   548                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   549                         sh4_stats[I_OR]++;

   550                         }

   551                         break;

   552                     case 0xC:

   553                         { /* CMP/STR Rm, Rn */

   554                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   555                         sh4_stats[I_CMPSTR]++;

   556                         }

   557                         break;

   558                     case 0xD:

   559                         { /* XTRCT Rm, Rn */

   560                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   561                         sh4_stats[I_XTRCT]++;

   562                         }

   563                         break;

   564                     case 0xE:

   565                         { /* MULU.W Rm, Rn */

   566                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   567                         sh4_stats[I_MULUW]++;

   568                         }

   569                         break;

   570                     case 0xF:

   571                         { /* MULS.W Rm, Rn */

   572                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   573                         sh4_stats[I_MULSW]++;

   574                         }

   575                         break;

   576                     default:

   577                         UNDEF();

   578                         break;

   579                 }

   580                 break;

   581             case 0x3:

   582                 switch( ir&0xF ) {

   583                     case 0x0:

   584                         { /* CMP/EQ Rm, Rn */

   585                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   586                         sh4_stats[I_CMPEQ]++;

   587                         }

   588                         break;

   589                     case 0x2:

   590                         { /* CMP/HS Rm, Rn */

   591                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   592                         sh4_stats[I_CMPHS]++;

   593                         }

   594                         break;

   595                     case 0x3:

   596                         { /* CMP/GE Rm, Rn */

   597                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   598                         sh4_stats[I_CMPGE]++;

   599                         }

   600                         break;

   601                     case 0x4:

   602                         { /* DIV1 Rm, Rn */

   603                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   604                         sh4_stats[I_DIV1]++;

   605                         }

   606                         break;

   607                     case 0x5:

   608                         { /* DMULU.L Rm, Rn */

   609                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   610                         sh4_stats[I_DMULU]++;

   611                         }

   612                         break;

   613                     case 0x6:

   614                         { /* CMP/HI Rm, Rn */

   615                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   616                         sh4_stats[I_CMPHI]++;

   617                         }

   618                         break;

   619                     case 0x7:

   620                         { /* CMP/GT Rm, Rn */

   621                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   622                         sh4_stats[I_CMPGT]++;

   623                         }

   624                         break;

   625                     case 0x8:

   626                         { /* SUB Rm, Rn */

   627                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   628                         sh4_stats[I_SUB]++;

   629                         }

   630                         break;

   631                     case 0xA:

   632                         { /* SUBC Rm, Rn */

   633                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   634                         sh4_stats[I_SUBC]++;

   635                         }

   636                         break;

   637                     case 0xB:

   638                         { /* SUBV Rm, Rn */

   639                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   640                         sh4_stats[I_SUBV]++;

   641                         }

   642                         break;

   643                     case 0xC:

   644                         { /* ADD Rm, Rn */

   645                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   646                         sh4_stats[I_ADD]++;

   647                         }

   648                         break;

   649                     case 0xD:

   650                         { /* DMULS.L Rm, Rn */

   651                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   652                         sh4_stats[I_DMULS]++;

   653                         }

   654                         break;

   655                     case 0xE:

   656                         { /* ADDC Rm, Rn */

   657                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   658                         sh4_stats[I_ADDC]++;

   659                         }

   660                         break;

   661                     case 0xF:

   662                         { /* ADDV Rm, Rn */

   663                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   664                         sh4_stats[I_ADDV]++;

   665                         }

   666                         break;

   667                     default:

   668                         UNDEF();

   669                         break;

   670                 }

   671                 break;

   672             case 0x4:

   673                 switch( ir&0xF ) {

   674                     case 0x0:

   675                         switch( (ir&0xF0) >> 4 ) {

   676                             case 0x0:

   677                                 { /* SHLL Rn */

   678                                 uint32_t Rn = ((ir>>8)&0xF);

   679                                 sh4_stats[I_SHLL]++;

   680                                 }

   681                                 break;

   682                             case 0x1:

   683                                 { /* DT Rn */

   684                                 uint32_t Rn = ((ir>>8)&0xF);

   685                                 sh4_stats[I_DT]++;

   686                                 }

   687                                 break;

   688                             case 0x2:

   689                                 { /* SHAL Rn */

   690                                 uint32_t Rn = ((ir>>8)&0xF);

   691                                 sh4_stats[I_SHAL]++;

   692                                 }

   693                                 break;

   694                             default:

   695                                 UNDEF();

   696                                 break;

   697                         }

   698                         break;

   699                     case 0x1:

   700                         switch( (ir&0xF0) >> 4 ) {

   701                             case 0x0:

   702                                 { /* SHLR Rn */

   703                                 uint32_t Rn = ((ir>>8)&0xF);

   704                                 sh4_stats[I_SHLR]++;

   705                                 }

   706                                 break;

   707                             case 0x1:

   708                                 { /* CMP/PZ Rn */

   709                                 uint32_t Rn = ((ir>>8)&0xF);

   710                                 sh4_stats[I_CMPPZ]++;

   711                                 }

   712                                 break;

   713                             case 0x2:

   714                                 { /* SHAR Rn */

   715                                 uint32_t Rn = ((ir>>8)&0xF);

   716                                 sh4_stats[I_SHAR]++;

   717                                 }

   718                                 break;

   719                             default:

   720                                 UNDEF();

   721                                 break;

   722                         }

   723                         break;

   724                     case 0x2:

   725                         switch( (ir&0xF0) >> 4 ) {

   726                             case 0x0:

   727                                 { /* STS.L MACH, @-Rn */

   728                                 uint32_t Rn = ((ir>>8)&0xF);

   729                                 sh4_stats[I_STSM]++;

   730                                 }

   731                                 break;

   732                             case 0x1:

   733                                 { /* STS.L MACL, @-Rn */

   734                                 uint32_t Rn = ((ir>>8)&0xF);

   735                                 sh4_stats[I_STSM]++;

   736                                 }

   737                                 break;

   738                             case 0x2:

   739                                 { /* STS.L PR, @-Rn */

   740                                 uint32_t Rn = ((ir>>8)&0xF);

   741                                 sh4_stats[I_STSM]++;

   742                                 }

   743                                 break;

   744                             case 0x3:

   745                                 { /* STC.L SGR, @-Rn */

   746                                 uint32_t Rn = ((ir>>8)&0xF);

   747                                 sh4_stats[I_STCM]++;

   748                                 }

   749                                 break;

   750                             case 0x5:

   751                                 { /* STS.L FPUL, @-Rn */

   752                                 uint32_t Rn = ((ir>>8)&0xF);

   753                                 sh4_stats[I_STSM]++;

   754                                 }

   755                                 break;

   756                             case 0x6:

   757                                 { /* STS.L FPSCR, @-Rn */

   758                                 uint32_t Rn = ((ir>>8)&0xF);

   759                                 sh4_stats[I_STSM]++;

   760                                 }

   761                                 break;

   762                             case 0xF:

   763                                 { /* STC.L DBR, @-Rn */

   764                                 uint32_t Rn = ((ir>>8)&0xF);

   765                                 sh4_stats[I_STCM]++;

   766                                 }

   767                                 break;

   768                             default:

   769                                 UNDEF();

   770                                 break;

   771                         }

   772                         break;

   773                     case 0x3:

   774                         switch( (ir&0x80) >> 7 ) {

   775                             case 0x0:

   776                                 switch( (ir&0x70) >> 4 ) {

   777                                     case 0x0:

   778                                         { /* STC.L SR, @-Rn */

   779                                         uint32_t Rn = ((ir>>8)&0xF);

   780                                         sh4_stats[I_STCSRM]++;

   781                                         }

   782                                         break;

   783                                     case 0x1:

   784                                         { /* STC.L GBR, @-Rn */

   785                                         uint32_t Rn = ((ir>>8)&0xF);

   786                                         sh4_stats[I_STCM]++;

   787                                         }

   788                                         break;

   789                                     case 0x2:

   790                                         { /* STC.L VBR, @-Rn */

   791                                         uint32_t Rn = ((ir>>8)&0xF);

   792                                         sh4_stats[I_STCM]++;

   793                                         }

   794                                         break;

   795                                     case 0x3:

   796                                         { /* STC.L SSR, @-Rn */

   797                                         uint32_t Rn = ((ir>>8)&0xF);

   798                                         sh4_stats[I_STCM]++;

   799                                         }

   800                                         break;

   801                                     case 0x4:

   802                                         { /* STC.L SPC, @-Rn */

   803                                         uint32_t Rn = ((ir>>8)&0xF);

   804                                         sh4_stats[I_STCM]++;

   805                                         }

   806                                         break;

   807                                     default:

   808                                         UNDEF();

   809                                         break;

   810                                 }

   811                                 break;

   812                             case 0x1:

   813                                 { /* STC.L Rm_BANK, @-Rn */

   814                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   815                                 sh4_stats[I_STCM]++;

   816                                 }

   817                                 break;

   818                         }

   819                         break;

   820                     case 0x4:

   821                         switch( (ir&0xF0) >> 4 ) {

   822                             case 0x0:

   823                                 { /* ROTL Rn */

   824                                 uint32_t Rn = ((ir>>8)&0xF);

   825                                 sh4_stats[I_ROTL]++;

   826                                 }

   827                                 break;

   828                             case 0x2:

   829                                 { /* ROTCL Rn */

   830                                 uint32_t Rn = ((ir>>8)&0xF);

   831                                 sh4_stats[I_ROTCL]++;

   832                                 }

   833                                 break;

   834                             default:

   835                                 UNDEF();

   836                                 break;

   837                         }

   838                         break;

   839                     case 0x5:

   840                         switch( (ir&0xF0) >> 4 ) {

   841                             case 0x0:

   842                                 { /* ROTR Rn */

   843                                 uint32_t Rn = ((ir>>8)&0xF);

   844                                 sh4_stats[I_ROTR]++;

   845                                 }

   846                                 break;

   847                             case 0x1:

   848                                 { /* CMP/PL Rn */

   849                                 uint32_t Rn = ((ir>>8)&0xF);

   850                                 sh4_stats[I_CMPPL]++;

   851                                 }

   852                                 break;

   853                             case 0x2:

   854                                 { /* ROTCR Rn */

   855                                 uint32_t Rn = ((ir>>8)&0xF);

   856                                 sh4_stats[I_ROTCR]++;

   857                                 }

   858                                 break;

   859                             default:

   860                                 UNDEF();

   861                                 break;

   862                         }

   863                         break;

   864                     case 0x6:

   865                         switch( (ir&0xF0) >> 4 ) {

   866                             case 0x0:

   867                                 { /* LDS.L @Rm+, MACH */

   868                                 uint32_t Rm = ((ir>>8)&0xF);

   869                                 sh4_stats[I_LDSM]++;

   870                                 }

   871                                 break;

   872                             case 0x1:

   873                                 { /* LDS.L @Rm+, MACL */

   874                                 uint32_t Rm = ((ir>>8)&0xF);

   875                                 sh4_stats[I_LDSM]++;

   876                                 }

   877                                 break;

   878                             case 0x2:

   879                                 { /* LDS.L @Rm+, PR */

   880                                 uint32_t Rm = ((ir>>8)&0xF);

   881                                 sh4_stats[I_LDSM]++;

   882                                 }

   883                                 break;

   884                             case 0x3:

   885                                 { /* LDC.L @Rm+, SGR */

   886                                 uint32_t Rm = ((ir>>8)&0xF);

   887                                 sh4_stats[I_LDCM]++;

   888                                 }

   889                                 break;

   890                             case 0x5:

   891                                 { /* LDS.L @Rm+, FPUL */

   892                                 uint32_t Rm = ((ir>>8)&0xF);

   893                                 sh4_stats[I_LDSM]++;

   894                                 }

   895                                 break;

   896                             case 0x6:

   897                                 { /* LDS.L @Rm+, FPSCR */

   898                                 uint32_t Rm = ((ir>>8)&0xF);

   899                                 sh4_stats[I_LDSM]++;

   900                                 }

   901                                 break;

   902                             case 0xF:

   903                                 { /* LDC.L @Rm+, DBR */

   904                                 uint32_t Rm = ((ir>>8)&0xF);

   905                                 sh4_stats[I_LDCM]++;

   906                                 }

   907                                 break;

   908                             default:

   909                                 UNDEF();

   910                                 break;

   911                         }

   912                         break;

   913                     case 0x7:

   914                         switch( (ir&0x80) >> 7 ) {

   915                             case 0x0:

   916                                 switch( (ir&0x70) >> 4 ) {

   917                                     case 0x0:

   918                                         { /* LDC.L @Rm+, SR */

   919                                         uint32_t Rm = ((ir>>8)&0xF);

   920                                         sh4_stats[I_LDCSRM]++;

   921                                         }

   922                                         break;

   923                                     case 0x1:

   924                                         { /* LDC.L @Rm+, GBR */

   925                                         uint32_t Rm = ((ir>>8)&0xF);

   926                                         sh4_stats[I_LDCM]++;

   927                                         }

   928                                         break;

   929                                     case 0x2:

   930                                         { /* LDC.L @Rm+, VBR */

   931                                         uint32_t Rm = ((ir>>8)&0xF);

   932                                         sh4_stats[I_LDCM]++;

   933                                         }

   934                                         break;

   935                                     case 0x3:

   936                                         { /* LDC.L @Rm+, SSR */

   937                                         uint32_t Rm = ((ir>>8)&0xF);

   938                                         sh4_stats[I_LDCM]++;

   939                                         }

   940                                         break;

   941                                     case 0x4:

   942                                         { /* LDC.L @Rm+, SPC */

   943                                         uint32_t Rm = ((ir>>8)&0xF);

   944                                         sh4_stats[I_LDCM]++;

   945                                         }

   946                                         break;

   947                                     default:

   948                                         UNDEF();

   949                                         break;

   950                                 }

   951                                 break;

   952                             case 0x1:

   953                                 { /* LDC.L @Rm+, Rn_BANK */

   954                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

   955                                 sh4_stats[I_LDCM]++;

   956                                 }

   957                                 break;

   958                         }

   959                         break;

   960                     case 0x8:

   961                         switch( (ir&0xF0) >> 4 ) {

   962                             case 0x0:

   963                                 { /* SHLL2 Rn */

   964                                 uint32_t Rn = ((ir>>8)&0xF);

   965                                 sh4_stats[I_SHLL]++;

   966                                 }

   967                                 break;

   968                             case 0x1:

   969                                 { /* SHLL8 Rn */

   970                                 uint32_t Rn = ((ir>>8)&0xF);

   971                                 sh4_stats[I_SHLL]++;

   972                                 }

   973                                 break;

   974                             case 0x2:

   975                                 { /* SHLL16 Rn */

   976                                 uint32_t Rn = ((ir>>8)&0xF);

   977                                 sh4_stats[I_SHLL]++;

   978                                 }

   979                                 break;

   980                             default:

   981                                 UNDEF();

   982                                 break;

   983                         }

   984                         break;

   985                     case 0x9:

   986                         switch( (ir&0xF0) >> 4 ) {

   987                             case 0x0:

   988                                 { /* SHLR2 Rn */

   989                                 uint32_t Rn = ((ir>>8)&0xF);

   990                                 sh4_stats[I_SHLR]++;

   991                                 }

   992                                 break;

   993                             case 0x1:

   994                                 { /* SHLR8 Rn */

   995                                 uint32_t Rn = ((ir>>8)&0xF);

   996                                 sh4_stats[I_SHLR]++;

   997                                 }

   998                                 break;

   999                             case 0x2:

  1000                                 { /* SHLR16 Rn */

  1001                                 uint32_t Rn = ((ir>>8)&0xF);

  1002                                 sh4_stats[I_SHLR]++;

  1003                                 }

  1004                                 break;

  1005                             default:

  1006                                 UNDEF();

  1007                                 break;

  1008                         }

  1009                         break;

  1010                     case 0xA:

  1011                         switch( (ir&0xF0) >> 4 ) {

  1012                             case 0x0:

  1013                                 { /* LDS Rm, MACH */

  1014                                 uint32_t Rm = ((ir>>8)&0xF);

  1015                                 sh4_stats[I_LDS]++;

  1016                                 }

  1017                                 break;

  1018                             case 0x1:

  1019                                 { /* LDS Rm, MACL */

  1020                                 uint32_t Rm = ((ir>>8)&0xF);

  1021                                 sh4_stats[I_LDS]++;

  1022                                 }

  1023                                 break;

  1024                             case 0x2:

  1025                                 { /* LDS Rm, PR */

  1026                                 uint32_t Rm = ((ir>>8)&0xF);

  1027                                 sh4_stats[I_LDS]++;

  1028                                 }

  1029                                 break;

  1030                             case 0x3:

  1031                                 { /* LDC Rm, SGR */

  1032                                 uint32_t Rm = ((ir>>8)&0xF);

  1033                                 sh4_stats[I_LDC]++;

  1034                                 }

  1035                                 break;

  1036                             case 0x5:

  1037                                 { /* LDS Rm, FPUL */

  1038                                 uint32_t Rm = ((ir>>8)&0xF);

  1039                                 sh4_stats[I_LDS]++;

  1040                                 }

  1041                                 break;

  1042                             case 0x6:

  1043                                 { /* LDS Rm, FPSCR */

  1044                                 uint32_t Rm = ((ir>>8)&0xF);

  1045                                 sh4_stats[I_LDS]++;

  1046                                 }

  1047                                 break;

  1048                             case 0xF:

  1049                                 { /* LDC Rm, DBR */

  1050                                 uint32_t Rm = ((ir>>8)&0xF);

  1051                                 sh4_stats[I_LDC]++;

  1052                                 }

  1053                                 break;

  1054                             default:

  1055                                 UNDEF();

  1056                                 break;

  1057                         }

  1058                         break;

  1059                     case 0xB:

  1060                         switch( (ir&0xF0) >> 4 ) {

  1061                             case 0x0:

  1062                                 { /* JSR @Rn */

  1063                                 uint32_t Rn = ((ir>>8)&0xF);

  1064                                 sh4_stats[I_JSR]++;

  1065                                 }

  1066                                 break;

  1067                             case 0x1:

  1068                                 { /* TAS.B @Rn */

  1069                                 uint32_t Rn = ((ir>>8)&0xF);

  1070                                 sh4_stats[I_TASB]++;

  1071                                 }

  1072                                 break;

  1073                             case 0x2:

  1074                                 { /* JMP @Rn */

  1075                                 uint32_t Rn = ((ir>>8)&0xF);

  1076                                 sh4_stats[I_JMP]++;

  1077                                 }

  1078                                 break;

  1079                             default:

  1080                                 UNDEF();

  1081                                 break;

  1082                         }

  1083                         break;

  1084                     case 0xC:

  1085                         { /* SHAD Rm, Rn */

  1086                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1087                         sh4_stats[I_SHAD]++;

  1088                         }

  1089                         break;

  1090                     case 0xD:

  1091                         { /* SHLD Rm, Rn */

  1092                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1093                         sh4_stats[I_SHLD]++;

  1094                         }

  1095                         break;

  1096                     case 0xE:

  1097                         switch( (ir&0x80) >> 7 ) {

  1098                             case 0x0:

  1099                                 switch( (ir&0x70) >> 4 ) {

  1100                                     case 0x0:

  1101                                         { /* LDC Rm, SR */

  1102                                         uint32_t Rm = ((ir>>8)&0xF);

  1103                                         sh4_stats[I_LDCSR]++;

  1104                                         }

  1105                                         break;

  1106                                     case 0x1:

  1107                                         { /* LDC Rm, GBR */

  1108                                         uint32_t Rm = ((ir>>8)&0xF);

  1109                                         sh4_stats[I_LDC]++;

  1110                                         }

  1111                                         break;

  1112                                     case 0x2:

  1113                                         { /* LDC Rm, VBR */

  1114                                         uint32_t Rm = ((ir>>8)&0xF);

  1115                                         sh4_stats[I_LDC]++;

  1116                                         }

  1117                                         break;

  1118                                     case 0x3:

  1119                                         { /* LDC Rm, SSR */

  1120                                         uint32_t Rm = ((ir>>8)&0xF);

  1121                                         sh4_stats[I_LDC]++;

  1122                                         }

  1123                                         break;

  1124                                     case 0x4:

  1125                                         { /* LDC Rm, SPC */

  1126                                         uint32_t Rm = ((ir>>8)&0xF);

  1127                                         sh4_stats[I_LDC]++;

  1128                                         }

  1129                                         break;

  1130                                     default:

  1131                                         UNDEF();

  1132                                         break;

  1133                                 }

  1134                                 break;

  1135                             case 0x1:

  1136                                 { /* LDC Rm, Rn_BANK */

  1137                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1138                                 sh4_stats[I_LDC]++;

  1139                                 }

  1140                                 break;

  1141                         }

  1142                         break;

  1143                     case 0xF:

  1144                         { /* MAC.W @Rm+, @Rn+ */

  1145                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1146                         sh4_stats[I_MACW]++;

  1147                         }

  1148                         break;

  1149                 }

  1150                 break;

  1151             case 0x5:

  1152                 { /* MOV.L @(disp, Rm), Rn */

  1153                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1154                 sh4_stats[I_MOVL]++;

  1155                 }

  1156                 break;

  1157             case 0x6:

  1158                 switch( ir&0xF ) {

  1159                     case 0x0:

  1160                         { /* MOV.B @Rm, Rn */

  1161                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1162                         sh4_stats[I_MOVB]++;

  1163                         }

  1164                         break;

  1165                     case 0x1:

  1166                         { /* MOV.W @Rm, Rn */

  1167                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1168                         sh4_stats[I_MOVW]++;

  1169                         }

  1170                         break;

  1171                     case 0x2:

  1172                         { /* MOV.L @Rm, Rn */

  1173                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1174                         sh4_stats[I_MOVL]++;

  1175                         }

  1176                         break;

  1177                     case 0x3:

  1178                         { /* MOV Rm, Rn */

  1179                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1180                         sh4_stats[I_MOV]++;

  1181                         }

  1182                         break;

  1183                     case 0x4:

  1184                         { /* MOV.B @Rm+, Rn */

  1185                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1186                         sh4_stats[I_MOVB]++;

  1187                         }

  1188                         break;

  1189                     case 0x5:

  1190                         { /* MOV.W @Rm+, Rn */

  1191                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1192                         sh4_stats[I_MOVW]++;

  1193                         }

  1194                         break;

  1195                     case 0x6:

  1196                         { /* MOV.L @Rm+, Rn */

  1197                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1198                         sh4_stats[I_MOVL]++;

  1199                         }

  1200                         break;

  1201                     case 0x7:

  1202                         { /* NOT Rm, Rn */

  1203                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1204                         sh4_stats[I_NOT]++;

  1205                         }

  1206                         break;

  1207                     case 0x8:

  1208                         { /* SWAP.B Rm, Rn */

  1209                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1210                         sh4_stats[I_SWAPB]++;

  1211                         }

  1212                         break;

  1213                     case 0x9:

  1214                         { /* SWAP.W Rm, Rn */

  1215                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1216                         sh4_stats[I_SWAPW]++;

  1217                         }

  1218                         break;

  1219                     case 0xA:

  1220                         { /* NEGC Rm, Rn */

  1221                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1222                         sh4_stats[I_NEGC]++;

  1223                         }

  1224                         break;

  1225                     case 0xB:

  1226                         { /* NEG Rm, Rn */

  1227                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1228                         sh4_stats[I_NEG]++;

  1229                         }

  1230                         break;

  1231                     case 0xC:

  1232                         { /* EXTU.B Rm, Rn */

  1233                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1234                         sh4_stats[I_EXTUB]++;

  1235                         }

  1236                         break;

  1237                     case 0xD:

  1238                         { /* EXTU.W Rm, Rn */

  1239                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1240                         sh4_stats[I_EXTUW]++;

  1241                         }

  1242                         break;

  1243                     case 0xE:

  1244                         { /* EXTS.B Rm, Rn */

  1245                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1246                         sh4_stats[I_EXTSB]++;

  1247                         }

  1248                         break;

  1249                     case 0xF:

  1250                         { /* EXTS.W Rm, Rn */

  1251                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1252                         sh4_stats[I_EXTSW]++;

  1253                         }

  1254                         break;

  1255                 }

  1256                 break;

  1257             case 0x7:

  1258                 { /* ADD #imm, Rn */

  1259                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1260                 sh4_stats[I_ADDI]++;

  1261                 }

  1262                 break;

  1263             case 0x8:

  1264                 switch( (ir&0xF00) >> 8 ) {

  1265                     case 0x0:

  1266                         { /* MOV.B R0, @(disp, Rn) */

  1267                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1268                         sh4_stats[I_MOVB]++;

  1269                         }

  1270                         break;

  1271                     case 0x1:

  1272                         { /* MOV.W R0, @(disp, Rn) */

  1273                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1274                         sh4_stats[I_MOVW]++;

  1275                         }

  1276                         break;

  1277                     case 0x4:

  1278                         { /* MOV.B @(disp, Rm), R0 */

  1279                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1280                         sh4_stats[I_MOVB]++;

  1281                         }

  1282                         break;

  1283                     case 0x5:

  1284                         { /* MOV.W @(disp, Rm), R0 */

  1285                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1286                         sh4_stats[I_MOVW]++;

  1287                         }

  1288                         break;

  1289                     case 0x8:

  1290                         { /* CMP/EQ #imm, R0 */

  1291                         int32_t imm = SIGNEXT8(ir&0xFF);

  1292                         sh4_stats[I_CMPEQI]++;

  1293                         }

  1294                         break;

  1295                     case 0x9:

  1296                         { /* BT disp */

  1297                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1298                         sh4_stats[I_BT]++;

  1299                         }

  1300                         break;

  1301                     case 0xB:

  1302                         { /* BF disp */

  1303                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1304                         sh4_stats[I_BF]++;

  1305                         }

  1306                         break;

  1307                     case 0xD:

  1308                         { /* BT/S disp */

  1309                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1310                         sh4_stats[I_BTS]++;

  1311                         }

  1312                         break;

  1313                     case 0xF:

  1314                         { /* BF/S disp */

  1315                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1316                         sh4_stats[I_BFS]++;

  1317                         }

  1318                         break;

  1319                     default:

  1320                         UNDEF();

  1321                         break;

  1322                 }

  1323                 break;

  1324             case 0x9:

  1325                 { /* MOV.W @(disp, PC), Rn */

  1326                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1327                 sh4_stats[I_MOVW]++;

  1328                 }

  1329                 break;

  1330             case 0xA:

  1331                 { /* BRA disp */

  1332                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1333                 sh4_stats[I_BRA]++;

  1334                 }

  1335                 break;

  1336             case 0xB:

  1337                 { /* BSR disp */

  1338                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1339                 sh4_stats[I_BSR]++;

  1340                 }

  1341                 break;

  1342             case 0xC:

  1343                 switch( (ir&0xF00) >> 8 ) {

  1344                     case 0x0:

  1345                         { /* MOV.B R0, @(disp, GBR) */

  1346                         uint32_t disp = (ir&0xFF);

  1347                         sh4_stats[I_MOVB]++;

  1348                         }

  1349                         break;

  1350                     case 0x1:

  1351                         { /* MOV.W R0, @(disp, GBR) */

  1352                         uint32_t disp = (ir&0xFF)<<1;

  1353                         sh4_stats[I_MOVW]++;

  1354                         }

  1355                         break;

  1356                     case 0x2:

  1357                         { /* MOV.L R0, @(disp, GBR) */

  1358                         uint32_t disp = (ir&0xFF)<<2;

  1359                         sh4_stats[I_MOVL]++;

  1360                         }

  1361                         break;

  1362                     case 0x3:

  1363                         { /* TRAPA #imm */

  1364                         uint32_t imm = (ir&0xFF);

  1365                         sh4_stats[I_TRAPA]++;

  1366                         }

  1367                         break;

  1368                     case 0x4:

  1369                         { /* MOV.B @(disp, GBR), R0 */

  1370                         uint32_t disp = (ir&0xFF);

  1371                         sh4_stats[I_MOVB]++;

  1372                         }

  1373                         break;

  1374                     case 0x5:

  1375                         { /* MOV.W @(disp, GBR), R0 */

  1376                         uint32_t disp = (ir&0xFF)<<1;

  1377                         sh4_stats[I_MOVW]++;

  1378                         }

  1379                         break;

  1380                     case 0x6:

  1381                         { /* MOV.L @(disp, GBR), R0 */

  1382                         uint32_t disp = (ir&0xFF)<<2;

  1383                         sh4_stats[I_MOVL]++;

  1384                         }

  1385                         break;

  1386                     case 0x7:

  1387                         { /* MOVA @(disp, PC), R0 */

  1388                         uint32_t disp = (ir&0xFF)<<2;

  1389                         sh4_stats[I_MOVA]++;

  1390                         }

  1391                         break;

  1392                     case 0x8:

  1393                         { /* TST #imm, R0 */

  1394                         uint32_t imm = (ir&0xFF);

  1395                         sh4_stats[I_TSTI]++;

  1396                         }

  1397                         break;

  1398                     case 0x9:

  1399                         { /* AND #imm, R0 */

  1400                         uint32_t imm = (ir&0xFF);

  1401                         sh4_stats[I_ANDI]++;

  1402                         }

  1403                         break;

  1404                     case 0xA:

  1405                         { /* XOR #imm, R0 */

  1406                         uint32_t imm = (ir&0xFF);

  1407                         sh4_stats[I_XORI]++;

  1408                         }

  1409                         break;

  1410                     case 0xB:

  1411                         { /* OR #imm, R0 */

  1412                         uint32_t imm = (ir&0xFF);

  1413                         sh4_stats[I_ORI]++;

  1414                         }

  1415                         break;

  1416                     case 0xC:

  1417                         { /* TST.B #imm, @(R0, GBR) */

  1418                         uint32_t imm = (ir&0xFF);

  1419                         sh4_stats[I_TSTB]++;

  1420                         }

  1421                         break;

  1422                     case 0xD:

  1423                         { /* AND.B #imm, @(R0, GBR) */

  1424                         uint32_t imm = (ir&0xFF);

  1425                         sh4_stats[I_ANDB]++;

  1426                         }

  1427                         break;

  1428                     case 0xE:

  1429                         { /* XOR.B #imm, @(R0, GBR) */

  1430                         uint32_t imm = (ir&0xFF);

  1431                         sh4_stats[I_XORB]++;

  1432                         }

  1433                         break;

  1434                     case 0xF:

  1435                         { /* OR.B #imm, @(R0, GBR) */

  1436                         uint32_t imm = (ir&0xFF);

  1437                         sh4_stats[I_ORB]++;

  1438                         }

  1439                         break;

  1440                 }

  1441                 break;

  1442             case 0xD:

  1443                 { /* MOV.L @(disp, PC), Rn */

  1444                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1445                 sh4_stats[I_MOVLPC]++;

  1446                 }

  1447                 break;

  1448             case 0xE:

  1449                 { /* MOV #imm, Rn */

  1450                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1451                 sh4_stats[I_MOVI]++;

  1452                 }

  1453                 break;

  1454             case 0xF:

  1455                 switch( ir&0xF ) {

  1456                     case 0x0:

  1457                         { /* FADD FRm, FRn */

  1458                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1459                         sh4_stats[I_FADD]++;

  1460                         }

  1461                         break;

  1462                     case 0x1:

  1463                         { /* FSUB FRm, FRn */

  1464                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1465                         sh4_stats[I_FSUB]++;

  1466                         }

  1467                         break;

  1468                     case 0x2:

  1469                         { /* FMUL FRm, FRn */

  1470                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1471                         sh4_stats[I_FMUL]++;

  1472                         }

  1473                         break;

  1474                     case 0x3:

  1475                         { /* FDIV FRm, FRn */

  1476                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1477                         sh4_stats[I_FDIV]++;

  1478                         }

  1479                         break;

  1480                     case 0x4:

  1481                         { /* FCMP/EQ FRm, FRn */

  1482                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1483                         sh4_stats[I_FCMPEQ]++;

  1484                         }

  1485                         break;

  1486                     case 0x5:

  1487                         { /* FCMP/GT FRm, FRn */

  1488                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1489                         sh4_stats[I_FCMPGT]++;

  1490                         }

  1491                         break;

  1492                     case 0x6:

  1493                         { /* FMOV @(R0, Rm), FRn */

  1494                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1495                         sh4_stats[I_FMOV7]++;

  1496                         }

  1497                         break;

  1498                     case 0x7:

  1499                         { /* FMOV FRm, @(R0, Rn) */

  1500                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1501                         sh4_stats[I_FMOV4]++;

  1502                         }

  1503                         break;

  1504                     case 0x8:

  1505                         { /* FMOV @Rm, FRn */

  1506                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1507                         sh4_stats[I_FMOV5]++;

  1508                         }

  1509                         break;

  1510                     case 0x9:

  1511                         { /* FMOV @Rm+, FRn */

  1512                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1513                         sh4_stats[I_FMOV6]++;

  1514                         }

  1515                         break;

  1516                     case 0xA:

  1517                         { /* FMOV FRm, @Rn */

  1518                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1519                         sh4_stats[I_FMOV2]++;

  1520                         }

  1521                         break;

  1522                     case 0xB:

  1523                         { /* FMOV FRm, @-Rn */

  1524                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1525                         sh4_stats[I_FMOV3]++;

  1526                         }

  1527                         break;

  1528                     case 0xC:

  1529                         { /* FMOV FRm, FRn */

  1530                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1531                         sh4_stats[I_FMOV1]++;

  1532                         }

  1533                         break;

  1534                     case 0xD:

  1535                         switch( (ir&0xF0) >> 4 ) {

  1536                             case 0x0:

  1537                                 { /* FSTS FPUL, FRn */

  1538                                 uint32_t FRn = ((ir>>8)&0xF);

  1539                                 sh4_stats[I_FSTS]++;

  1540                                 }

  1541                                 break;

  1542                             case 0x1:

  1543                                 { /* FLDS FRm, FPUL */

  1544                                 uint32_t FRm = ((ir>>8)&0xF);

  1545                                 sh4_stats[I_FLDS]++;

  1546                                 }

  1547                                 break;

  1548                             case 0x2:

  1549                                 { /* FLOAT FPUL, FRn */

  1550                                 uint32_t FRn = ((ir>>8)&0xF);

  1551                                 sh4_stats[I_FLOAT]++;

  1552                                 }

  1553                                 break;

  1554                             case 0x3:

  1555                                 { /* FTRC FRm, FPUL */

  1556                                 uint32_t FRm = ((ir>>8)&0xF);

  1557                                 sh4_stats[I_FTRC]++;

  1558                                 }

  1559                                 break;

  1560                             case 0x4:

  1561                                 { /* FNEG FRn */

  1562                                 uint32_t FRn = ((ir>>8)&0xF);

  1563                                 sh4_stats[I_FNEG]++;

  1564                                 }

  1565                                 break;

  1566                             case 0x5:

  1567                                 { /* FABS FRn */

  1568                                 uint32_t FRn = ((ir>>8)&0xF);

  1569                                 sh4_stats[I_FABS]++;

  1570                                 }

  1571                                 break;

  1572                             case 0x6:

  1573                                 { /* FSQRT FRn */

  1574                                 uint32_t FRn = ((ir>>8)&0xF);

  1575                                 sh4_stats[I_FSQRT]++;

  1576                                 }

  1577                                 break;

  1578                             case 0x7:

  1579                                 { /* FSRRA FRn */

  1580                                 uint32_t FRn = ((ir>>8)&0xF);

  1581                                 sh4_stats[I_FSRRA]++;

  1582                                 }

  1583                                 break;

  1584                             case 0x8:

  1585                                 { /* FLDI0 FRn */

  1586                                 uint32_t FRn = ((ir>>8)&0xF);

  1587                                 sh4_stats[I_FLDI0]++;

  1588                                 }

  1589                                 break;

  1590                             case 0x9:

  1591                                 { /* FLDI1 FRn */

  1592                                 uint32_t FRn = ((ir>>8)&0xF);

  1593                                 sh4_stats[I_FLDI1]++;

  1594                                 }

  1595                                 break;

  1596                             case 0xA:

  1597                                 { /* FCNVSD FPUL, FRn */

  1598                                 uint32_t FRn = ((ir>>8)&0xF);

  1599                                 sh4_stats[I_FCNVSD]++;

  1600                                 }

  1601                                 break;

  1602                             case 0xB:

  1603                                 { /* FCNVDS FRm, FPUL */

  1604                                 uint32_t FRm = ((ir>>8)&0xF);

  1605                                 sh4_stats[I_FCNVDS]++;

  1606                                 }

  1607                                 break;

  1608                             case 0xE:

  1609                                 { /* FIPR FVm, FVn */

  1610                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  1611                                 sh4_stats[I_FIPR]++;

  1612                                 }

  1613                                 break;

  1614                             case 0xF:

  1615                                 switch( (ir&0x100) >> 8 ) {

  1616                                     case 0x0:

  1617                                         { /* FSCA FPUL, FRn */

  1618                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  1619                                         sh4_stats[I_FSCA]++;

  1620                                         }

  1621                                         break;

  1622                                     case 0x1:

  1623                                         switch( (ir&0x200) >> 9 ) {

  1624                                             case 0x0:

  1625                                                 { /* FTRV XMTRX, FVn */

  1626                                                 uint32_t FVn = ((ir>>10)&0x3);

  1627                                                 sh4_stats[I_FTRV]++;

  1628                                                 }

  1629                                                 break;

  1630                                             case 0x1:

  1631                                                 switch( (ir&0xC00) >> 10 ) {

  1632                                                     case 0x0:

  1633                                                         { /* FSCHG */

  1634                                                         sh4_stats[I_FSCHG]++;

  1635                                                         }

  1636                                                         break;

  1637                                                     case 0x2:

  1638                                                         { /* FRCHG */

  1639                                                         sh4_stats[I_FRCHG]++;

  1640                                                         }

  1641                                                         break;

  1642                                                     case 0x3:

  1643                                                         { /* UNDEF */

  1644                                                         sh4_stats[I_UNDEF]++;

  1645                                                         }

  1646                                                         break;

  1647                                                     default:

  1648                                                         UNDEF();

  1649                                                         break;

  1650                                                 }

  1651                                                 break;

  1652                                         }

  1653                                         break;

  1654                                 }

  1655                                 break;

  1656                             default:

  1657                                 UNDEF();

  1658                                 break;

  1659                         }

  1660                         break;

  1661                     case 0xE:

  1662                         { /* FMAC FR0, FRm, FRn */

  1663                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1664                         sh4_stats[I_FMAC]++;

  1665                         }

  1666                         break;

  1667                     default:

  1668                         UNDEF();

  1669                         break;

  1670                 }

  1671                 break;

  1672         }

  1675 sh4_stats_total++;

  1676 }