4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
29 #include "sh4/sh4core.h"
30 #include "sh4/sh4mmio.h"
31 #include "sh4/sh4stat.h"
34 #define SH4_CALLTRACE 1
36 #define MAX_INT 0x7FFFFFFF
37 #define MIN_INT 0x80000000
38 #define MAX_INTF 2147483647.0
39 #define MIN_INTF -2147483648.0
41 /********************** SH4 Module Definition ****************************/
43 uint32_t sh4_emulate_run_slice( uint32_t nanosecs )
47 if( sh4_breakpoint_count == 0 ) {
48 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
49 if( SH4_EVENT_PENDING() ) {
50 if( sh4r.event_types & PENDING_EVENT ) {
53 /* Eventq execute may (quite likely) deliver an immediate IRQ */
54 if( sh4r.event_types & PENDING_IRQ ) {
55 sh4_accept_interrupt();
58 if( !sh4_execute_instruction() ) {
63 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
64 if( SH4_EVENT_PENDING() ) {
65 if( sh4r.event_types & PENDING_EVENT ) {
68 /* Eventq execute may (quite likely) deliver an immediate IRQ */
69 if( sh4r.event_types & PENDING_IRQ ) {
70 sh4_accept_interrupt();
74 if( !sh4_execute_instruction() )
76 #ifdef ENABLE_DEBUG_MODE
77 for( i=0; i<sh4_breakpoint_count; i++ ) {
78 if( sh4_breakpoints[i].address == sh4r.pc ) {
82 if( i != sh4_breakpoint_count ) {
83 sh4_core_exit( CORE_EXIT_BREAKPOINT );
89 /* If we aborted early, but the cpu is still technically running,
90 * we're doing a hard abort - cut the timeslice back to what we
93 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
94 nanosecs = sh4r.slice_cycle;
96 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
97 TMU_run_slice( nanosecs );
98 SCIF_run_slice( nanosecs );
103 /********************** SH4 emulation core ****************************/
105 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
106 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }while(0)
108 #if(SH4_CALLTRACE == 1)
109 #define MAX_CALLSTACK 32
110 static struct call_stack {
112 sh4addr_t target_addr;
113 sh4addr_t stack_pointer;
114 } call_stack[MAX_CALLSTACK];
116 static int call_stack_depth = 0;
117 int sh4_call_trace_on = 0;
119 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
121 if( call_stack_depth < MAX_CALLSTACK ) {
122 call_stack[call_stack_depth].call_addr = source;
123 call_stack[call_stack_depth].target_addr = dest;
124 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
129 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
131 if( call_stack_depth > 0 ) {
136 void fprint_stack_trace( FILE *f )
138 int i = call_stack_depth -1;
139 if( i >= MAX_CALLSTACK )
140 i = MAX_CALLSTACK - 1;
141 for( ; i >= 0; i-- ) {
142 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
143 (call_stack_depth - i), call_stack[i].call_addr,
144 call_stack[i].target_addr, call_stack[i].stack_pointer );
148 #define TRACE_CALL( source, dest ) trace_call(source, dest)
149 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
151 #define TRACE_CALL( dest, rts )
152 #define TRACE_RETURN( source, dest )
155 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
156 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
157 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
158 #define CHECKRALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
159 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
160 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
161 #define CHECKWALIGN64(addr) if( (addr)&0x07 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
163 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
164 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_core_exit(CORE_EXIT_HALT); return FALSE; }
165 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
167 #define ADDRSPACE (IS_SH4_PRIVMODE() ? sh4_address_space : sh4_user_address_space)
168 #define SQADDRSPACE (IS_SH4_PRIVMODE() ? storequeue_address_space : storequeue_user_address_space)
170 #ifdef HAVE_FRAME_ADDRESS
171 static FASTCALL __attribute__((noinline)) void *__first_arg(void *a, void *b) { return a; }
172 #define INIT_EXCEPTIONS(label) goto *__first_arg(&&fnstart,&&label); fnstart:
173 #define MEM_READ_BYTE( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_byte)((addr), &&except)
174 #define MEM_READ_WORD( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_word)((addr), &&except)
175 #define MEM_READ_LONG( addr, val ) val = ((mem_read_exc_fn_t)ADDRSPACE[(addr)>>12]->read_long)((addr), &&except)
176 #define MEM_WRITE_BYTE( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_byte)((addr), (val), &&except)
177 #define MEM_WRITE_WORD( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_word)((addr), (val), &&except)
178 #define MEM_WRITE_LONG( addr, val ) ((mem_write_exc_fn_t)ADDRSPACE[(addr)>>12]->write_long)((addr), (val), &&except)
180 #define INIT_EXCEPTIONS(label)
181 #define MEM_READ_BYTE( addr, val ) val = ADDRSPACE[(addr)>>12]->read_byte(addr)
182 #define MEM_READ_WORD( addr, val ) val = ADDRSPACE[(addr)>>12]->read_word(addr)
183 #define MEM_READ_LONG( addr, val ) val = ADDRSPACE[(addr)>>12]->read_long(addr)
184 #define MEM_WRITE_BYTE( addr, val ) ADDRSPACE[(addr)>>12]->write_byte(addr, val)
185 #define MEM_WRITE_WORD( addr, val ) ADDRSPACE[(addr)>>12]->write_word(addr, val)
186 #define MEM_WRITE_LONG( addr, val ) ADDRSPACE[(addr)>>12]->write_long(addr, val)
193 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
195 #define MEM_FP_READ( addr, reg ) \
196 if( IS_FPU_DOUBLESIZE() ) { \
197 CHECKRALIGN64(addr); \
199 MEM_READ_LONG( addr, *((uint32_t *)&XF((reg) & 0x0E)) ); \
200 MEM_READ_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
202 MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
203 MEM_READ_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
206 CHECKRALIGN32(addr); \
207 MEM_READ_LONG( addr, *((uint32_t *)&FR(reg)) ); \
209 #define MEM_FP_WRITE( addr, reg ) \
210 if( IS_FPU_DOUBLESIZE() ) { \
211 CHECKWALIGN64(addr); \
213 MEM_WRITE_LONG( addr, *((uint32_t *)&XF((reg)&0x0E)) ); \
214 MEM_WRITE_LONG( addr+4, *((uint32_t *)&XF(reg)) ); \
216 MEM_WRITE_LONG( addr, *((uint32_t *)&FR(reg)) ); \
217 MEM_WRITE_LONG( addr+4, *((uint32_t *)&FR((reg)|0x01)) ); \
220 CHECKWALIGN32(addr); \
221 MEM_WRITE_LONG(addr, *((uint32_t *)&FR((reg))) ); \
224 gboolean sh4_execute_instruction( void )
231 int64_t memtmp; // temporary holder for memory reads
233 INIT_EXCEPTIONS(except)
237 if( pc > 0xFFFFFF00 ) {
239 syscall_invoke( pc );
240 sh4r.in_delay_slot = 0;
241 pc = sh4r.pc = sh4r.pr;
242 sh4r.new_pc = sh4r.pc + 2;
247 #ifdef ENABLE_SH4STATS
248 sh4_stats_add_by_pc(sh4r.pc);
251 /* Read instruction */
252 if( !IS_IN_ICACHE(pc) ) {
253 if( !mmu_update_icache(pc) ) {
254 // Fault - look for the fault handler
255 if( !mmu_update_icache(sh4r.pc) ) {
256 // double fault - halt
257 ERROR( "Double fault - halting" );
258 sh4_core_exit(CORE_EXIT_HALT);
264 assert( IS_IN_ICACHE(pc) );
265 ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
267 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
268 AND #imm, R0 {: R0 &= imm; :}
269 AND.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp ); :}
270 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
271 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
272 OR #imm, R0 {: R0 |= imm; :}
273 OR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp ); :}
275 MEM_READ_BYTE( sh4r.r[Rn], tmp );
276 sh4r.t = ( tmp == 0 ? 1 : 0 );
277 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
279 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
280 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
281 TST.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 ); :}
282 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
283 XOR #imm, R0 {: R0 ^= imm; :}
284 XOR.B #imm, @(R0, GBR) {: MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp ); :}
285 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
288 sh4r.t = sh4r.r[Rn] >> 31;
290 sh4r.r[Rn] |= sh4r.t;
293 sh4r.t = sh4r.r[Rn] & 0x00000001;
295 sh4r.r[Rn] |= (sh4r.t << 31);
298 tmp = sh4r.r[Rn] >> 31;
300 sh4r.r[Rn] |= sh4r.t;
304 tmp = sh4r.r[Rn] & 0x00000001;
306 sh4r.r[Rn] |= (sh4r.t << 31 );
311 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
312 else if( (tmp & 0x1F) == 0 )
313 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
315 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
319 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
320 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
321 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
324 sh4r.t = sh4r.r[Rn] >> 31;
328 sh4r.t = sh4r.r[Rn] & 0x00000001;
329 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
331 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
332 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
333 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
334 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
335 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
336 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
337 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
338 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
340 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
341 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
342 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
343 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
344 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
345 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
347 CLRT {: sh4r.t = 0; :}
348 SETT {: sh4r.t = 1; :}
349 CLRMAC {: sh4r.mac = 0; :}
350 LDTLB {: MMU_ldtlb(); :}
351 CLRS {: sh4r.s = 0; :}
352 SETS {: sh4r.s = 1; :}
353 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
358 if( (tmp & 0xFC000000) == 0xE0000000 ) {
359 sh4_flush_store_queue(tmp);
368 MEM_WRITE_LONG( tmp, R0 );
370 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
371 MOV.W Rm, @(R0, Rn) {:
372 CHECKWALIGN16( R0 + sh4r.r[Rn] );
373 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
375 MOV.L Rm, @(R0, Rn) {:
376 CHECKWALIGN32( R0 + sh4r.r[Rn] );
377 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
379 MOV.B @(R0, Rm), Rn {: MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] ); :}
380 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
381 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
383 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
384 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
386 MOV.L Rm, @(disp, Rn) {:
387 tmp = sh4r.r[Rn] + disp;
388 CHECKWALIGN32( tmp );
389 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
391 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
392 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
393 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
394 MOV.B Rm, @-Rn {: MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--; :}
395 MOV.W Rm, @-Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2; :}
396 MOV.L Rm, @-Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4; :}
397 MOV.L @(disp, Rm), Rn {:
398 tmp = sh4r.r[Rm] + disp;
399 CHECKRALIGN32( tmp );
400 MEM_READ_LONG( tmp, sh4r.r[Rn] );
402 MOV.B @Rm, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); :}
403 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); :}
404 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); :}
405 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
406 MOV.B @Rm+, Rn {: MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++; :}
407 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2; :}
408 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4; :}
409 MOV.L @(disp, PC), Rn {:
411 tmp = (pc&0xFFFFFFFC) + disp + 4;
412 MEM_READ_LONG( tmp, sh4r.r[Rn] );
414 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
415 MOV.W R0, @(disp, GBR) {:
416 tmp = sh4r.gbr + disp;
417 CHECKWALIGN16( tmp );
418 MEM_WRITE_WORD( tmp, R0 );
420 MOV.L R0, @(disp, GBR) {:
421 tmp = sh4r.gbr + disp;
422 CHECKWALIGN32( tmp );
423 MEM_WRITE_LONG( tmp, R0 );
425 MOV.B @(disp, GBR), R0 {: MEM_READ_BYTE( sh4r.gbr + disp, R0 ); :}
426 MOV.W @(disp, GBR), R0 {:
427 tmp = sh4r.gbr + disp;
428 CHECKRALIGN16( tmp );
429 MEM_READ_WORD( tmp, R0 );
431 MOV.L @(disp, GBR), R0 {:
432 tmp = sh4r.gbr + disp;
433 CHECKRALIGN32( tmp );
434 MEM_READ_LONG( tmp, R0 );
436 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
437 MOV.W R0, @(disp, Rn) {:
438 tmp = sh4r.r[Rn] + disp;
439 CHECKWALIGN16( tmp );
440 MEM_WRITE_WORD( tmp, R0 );
442 MOV.B @(disp, Rm), R0 {: MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 ); :}
443 MOV.W @(disp, Rm), R0 {:
444 tmp = sh4r.r[Rm] + disp;
445 CHECKRALIGN16( tmp );
446 MEM_READ_WORD( tmp, R0 );
448 MOV.W @(disp, PC), Rn {:
451 MEM_READ_WORD( tmp, sh4r.r[Rn] );
453 MOVA @(disp, PC), R0 {:
455 R0 = (pc&0xFFFFFFFC) + disp + 4;
457 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
459 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
460 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
461 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
462 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
463 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
464 FMOV FRm, @-Rn {: MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH; :}
466 if( IS_FPU_DOUBLESIZE() )
472 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
473 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
474 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
475 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
476 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
477 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
478 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
479 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
481 /* set T = 1 if any byte in RM & RN is the same */
482 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
483 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
484 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
487 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
488 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
491 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
492 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
495 tmp = sh4r.r[Rn] + sh4r.r[Rm];
496 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
499 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
501 sh4r.q = sh4r.r[Rn]>>31;
502 sh4r.m = sh4r.r[Rm]>>31;
503 sh4r.t = sh4r.q ^ sh4r.m;
506 /* This is derived from the sh4 manual with some simplifications */
507 uint32_t tmp0, tmp1, tmp2, dir;
509 dir = sh4r.q ^ sh4r.m;
510 sh4r.q = (sh4r.r[Rn] >> 31);
512 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
516 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
519 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
521 sh4r.q ^= sh4r.m ^ tmp1;
522 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
524 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
525 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
528 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
533 CHECKRALIGN16(sh4r.r[Rn]);
534 MEM_READ_WORD( sh4r.r[Rn], tmp );
535 stmp = SIGNEXT16(tmp);
536 MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
537 stmp *= SIGNEXT16(tmp);
540 CHECKRALIGN16( sh4r.r[Rn] );
541 CHECKRALIGN16( sh4r.r[Rm] );
542 MEM_READ_WORD(sh4r.r[Rn], tmp);
543 stmp = SIGNEXT16(tmp);
544 MEM_READ_WORD(sh4r.r[Rm], tmp);
545 stmp = stmp * SIGNEXT16(tmp);
550 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
551 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
552 sh4r.mac = 0x000000017FFFFFFFLL;
553 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
554 sh4r.mac = 0x0000000180000000LL;
556 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
557 ((uint32_t)(sh4r.mac + stmp));
560 sh4r.mac += SIGNEXT32(stmp);
566 CHECKRALIGN32( sh4r.r[Rn] );
567 MEM_READ_LONG(sh4r.r[Rn], tmp);
568 tmpl = SIGNEXT32(tmp);
569 MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
570 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
573 CHECKRALIGN32( sh4r.r[Rm] );
574 CHECKRALIGN32( sh4r.r[Rn] );
575 MEM_READ_LONG(sh4r.r[Rn], tmp);
576 tmpl = SIGNEXT32(tmp);
577 MEM_READ_LONG(sh4r.r[Rm], tmp);
578 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
583 /* 48-bit Saturation. Yuch */
584 if( tmpl < (int64_t)0xFFFF800000000000LL )
585 tmpl = 0xFFFF800000000000LL;
586 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
587 tmpl = 0x00007FFFFFFFFFFFLL;
591 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
592 (sh4r.r[Rm] * sh4r.r[Rn]); :}
594 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
595 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
598 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
599 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
602 tmp = 0 - sh4r.r[Rm];
603 sh4r.r[Rn] = tmp - sh4r.t;
604 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
606 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
607 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
610 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
611 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
616 CHECKDEST( pc + 4 + sh4r.r[Rn] );
617 sh4r.in_delay_slot = 1;
618 sh4r.pc = sh4r.new_pc;
619 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
624 CHECKDEST( pc + 4 + sh4r.r[Rn] );
625 sh4r.in_delay_slot = 1;
626 sh4r.pr = sh4r.pc + 4;
627 sh4r.pc = sh4r.new_pc;
628 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
629 TRACE_CALL( pc, sh4r.new_pc );
635 CHECKDEST( sh4r.pc + disp + 4 )
637 sh4r.new_pc = sh4r.pc + 2;
644 CHECKDEST( sh4r.pc + disp + 4 )
646 sh4r.new_pc = sh4r.pc + 2;
653 CHECKDEST( sh4r.pc + disp + 4 )
654 sh4r.in_delay_slot = 1;
655 sh4r.pc = sh4r.new_pc;
656 sh4r.new_pc = pc + disp + 4;
657 sh4r.in_delay_slot = 1;
664 CHECKDEST( sh4r.pc + disp + 4 )
665 sh4r.in_delay_slot = 1;
666 sh4r.pc = sh4r.new_pc;
667 sh4r.new_pc = pc + disp + 4;
673 CHECKDEST( sh4r.pc + disp + 4 );
674 sh4r.in_delay_slot = 1;
675 sh4r.pc = sh4r.new_pc;
676 sh4r.new_pc = pc + 4 + disp;
680 CHECKDEST( sh4r.pc + disp + 4 );
682 sh4r.in_delay_slot = 1;
684 sh4r.pc = sh4r.new_pc;
685 sh4r.new_pc = pc + 4 + disp;
686 TRACE_CALL( pc, sh4r.new_pc );
692 sh4_raise_trap( imm );
697 CHECKDEST( sh4r.pr );
698 sh4r.in_delay_slot = 1;
699 sh4r.pc = sh4r.new_pc;
700 sh4r.new_pc = sh4r.pr;
701 TRACE_RETURN( pc, sh4r.new_pc );
705 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
706 sh4r.sh4_state = SH4_STATE_STANDBY;
708 sh4r.sh4_state = SH4_STATE_SLEEP;
710 return FALSE; /* Halt CPU */
714 CHECKDEST( sh4r.spc );
716 sh4r.in_delay_slot = 1;
717 sh4r.pc = sh4r.new_pc;
718 sh4r.new_pc = sh4r.spc;
719 sh4_write_sr( sh4r.ssr );
723 CHECKDEST( sh4r.r[Rn] );
725 sh4r.in_delay_slot = 1;
726 sh4r.pc = sh4r.new_pc;
727 sh4r.new_pc = sh4r.r[Rn];
731 CHECKDEST( sh4r.r[Rn] );
733 sh4r.in_delay_slot = 1;
734 sh4r.pc = sh4r.new_pc;
735 sh4r.new_pc = sh4r.r[Rn];
737 TRACE_CALL( pc, sh4r.new_pc );
740 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
742 CHECKWALIGN32( sh4r.r[Rn] );
743 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
748 CHECKWALIGN32( sh4r.r[Rn] );
749 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
753 CHECKRALIGN32( sh4r.r[Rm] );
754 MEM_READ_LONG(sh4r.r[Rm], tmp);
755 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
756 (((uint64_t)tmp)<<32);
762 CHECKWALIGN32( sh4r.r[Rm] );
763 MEM_READ_LONG(sh4r.r[Rm], tmp);
768 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
769 (((uint64_t)sh4r.r[Rm])<<32);
774 sh4_write_sr( sh4r.r[Rm] );
778 sh4r.sgr = sh4r.r[Rm];
782 CHECKRALIGN32( sh4r.r[Rm] );
783 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
786 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
788 CHECKWALIGN32( sh4r.r[Rn] );
789 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
793 CHECKWALIGN32( sh4r.r[Rn] );
794 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
798 CHECKRALIGN32( sh4r.r[Rm] );
799 MEM_READ_LONG(sh4r.r[Rm], tmp);
800 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
801 (uint64_t)((uint32_t)tmp);
805 CHECKRALIGN32( sh4r.r[Rm] );
806 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
810 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
811 (uint64_t)((uint32_t)(sh4r.r[Rm]));
813 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
814 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
816 CHECKWALIGN32( sh4r.r[Rn] );
817 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
822 CHECKWALIGN32( sh4r.r[Rn] );
823 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
827 CHECKRALIGN32( sh4r.r[Rm] );
828 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
833 CHECKRALIGN32( sh4r.r[Rm] );
834 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
837 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
840 sh4r.vbr = sh4r.r[Rm];
844 sh4r.r[Rn] = sh4r.sgr;
848 CHECKWALIGN32( sh4r.r[Rn] );
849 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
854 CHECKWALIGN32( sh4r.r[Rn] );
855 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
860 CHECKRALIGN32( sh4r.r[Rm] );
861 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
866 sh4r.ssr = sh4r.r[Rm];
870 CHECKWALIGN32( sh4r.r[Rn] );
871 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
876 CHECKRALIGN32( sh4r.r[Rm] );
877 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
882 sh4r.spc = sh4r.r[Rm];
890 CHECKWALIGN32( sh4r.r[Rn] );
891 MEM_WRITE_LONG( sh4r.r[Rn]-4, FPULi );
896 CHECKRALIGN32( sh4r.r[Rm] );
897 MEM_READ_LONG(sh4r.r[Rm], FPULi);
906 sh4r.r[Rn] = sh4r.fpscr;
910 CHECKWALIGN32( sh4r.r[Rn] );
911 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
916 CHECKRALIGN32( sh4r.r[Rm] );
917 MEM_READ_LONG(sh4r.r[Rm], tmp);
919 sh4_write_fpscr( tmp );
923 sh4_write_fpscr( sh4r.r[Rm] );
925 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
928 CHECKWALIGN32( sh4r.r[Rn] );
929 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
934 CHECKRALIGN32( sh4r.r[Rm] );
935 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
940 sh4r.dbr = sh4r.r[Rm];
942 STC.L Rm_BANK, @-Rn {:
944 CHECKWALIGN32( sh4r.r[Rn] );
945 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
948 LDC.L @Rm+, Rn_BANK {:
950 CHECKRALIGN32( sh4r.r[Rm] );
951 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
956 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
960 sh4r.r[Rn] = sh4_read_sr();
963 sh4r.r[Rn] = sh4r.gbr;
967 sh4r.r[Rn] = sh4r.vbr;
971 sh4r.r[Rn] = sh4r.ssr;
975 sh4r.r[Rn] = sh4r.spc;
979 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
984 if( IS_FPU_DOUBLEPREC() ) {
992 if( IS_FPU_DOUBLEPREC() ) {
1001 if( IS_FPU_DOUBLEPREC() ) {
1010 if( IS_FPU_DOUBLEPREC() ) {
1019 if( IS_FPU_DOUBLEPREC() ) {
1020 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1022 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1028 if( IS_FPU_DOUBLEPREC() ) {
1029 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1031 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1035 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1036 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1039 if( IS_FPU_DOUBLEPREC() ) {
1040 if( FRn&1 ) { // No, really...
1041 dtmp = (double)FPULi;
1042 FR(FRn) = *(((float *)&dtmp)+1);
1044 DRF(FRn>>1) = (double)FPULi;
1047 FR(FRn) = (float)FPULi;
1052 if( IS_FPU_DOUBLEPREC() ) {
1055 *(((float *)&dtmp)+1) = FR(FRm);
1059 if( dtmp >= MAX_INTF )
1061 else if( dtmp <= MIN_INTF )
1064 FPULi = (int32_t)dtmp;
1067 if( ftmp >= MAX_INTF )
1069 else if( ftmp <= MIN_INTF )
1072 FPULi = (int32_t)ftmp;
1077 if( IS_FPU_DOUBLEPREC() ) {
1085 if( IS_FPU_DOUBLEPREC() ) {
1086 DR(FRn) = fabs(DR(FRn));
1088 FR(FRn) = fabsf(FR(FRn));
1093 if( IS_FPU_DOUBLEPREC() ) {
1094 DR(FRn) = sqrt(DR(FRn));
1096 FR(FRn) = sqrtf(FR(FRn));
1101 if( IS_FPU_DOUBLEPREC() ) {
1109 if( IS_FPU_DOUBLEPREC() ) {
1115 FMAC FR0, FRm, FRn {:
1117 if( IS_FPU_DOUBLEPREC() ) {
1118 DR(FRn) += DR(FRm)*DR(0);
1120 FR(FRn) += FR(FRm)*FR(0);
1125 sh4r.fpscr ^= FPSCR_FR;
1126 sh4_switch_fr_banks();
1128 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1131 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1132 DR(FRn) = (double)FPULf;
1137 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1138 FPULf = (float)DR(FRm);
1144 if( !IS_FPU_DOUBLEPREC() ) {
1145 FR(FRn) = 1.0/sqrtf(FR(FRn));
1150 if( !IS_FPU_DOUBLEPREC() ) {
1153 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1154 FR(tmp+1)*FR(tmp2+1) +
1155 FR(tmp+2)*FR(tmp2+2) +
1156 FR(tmp+3)*FR(tmp2+3);
1161 if( !IS_FPU_DOUBLEPREC() ) {
1162 sh4_fsca( FPULi, (float *)&(DRF(FRn>>1)) );
1164 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1165 FR(FRn) = sinf(angle);
1166 FR((FRn)+1) = cosf(angle);
1172 if( !IS_FPU_DOUBLEPREC() ) {
1173 sh4_ftrv((float *)&(DRF(FVn<<1)) );
1180 sh4r.pc = sh4r.new_pc;
1184 sh4r.in_delay_slot = 0;
.