lxdream 0.9.1| filename | src/aica/armcore.h |
| changeset | 86:f151e63f9754 |
| prev | 73:0bb57e51ac9e |
| next | 431:248dd77a9e44 |
| author | nkeynes |
| date | Wed Jan 03 09:00:17 2007 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Adjust timers when they're read rather than waiting until the next time slice. Also temporarily cut the CPU time by 4. Initialize the FRQCR register to 0x0E0A for convenience |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: armcore.h,v 1.14 2006-01-22 22:40:05 nkeynes Exp $
3 *
4 * Interface definitions for the ARM CPU emulation core proper.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef dream_armcore_H
20 #define dream_armcore_H 1
22 #include "dream.h"
23 #include <stdint.h>
24 #include <stdio.h>
26 #define ARM_BASE_RATE 2 /* MHZ */
27 extern uint32_t arm_cpu_freq;
28 extern uint32_t arm_cpu_period;
30 #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) )
32 struct arm_registers {
33 uint32_t r[16]; /* Current register bank */
35 uint32_t cpsr;
36 uint32_t spsr;
38 /* Various banked versions of the registers. Note that these are used
39 * to save the registers for the named bank when leaving the mode, they're
40 * not actually used actively.
41 **/
42 uint32_t user_r[7]; /* User/System bank 8..14 */
43 uint32_t svc_r[3]; /* SVC bank 13..14, SPSR */
44 uint32_t abt_r[3]; /* ABT bank 13..14, SPSR */
45 uint32_t und_r[3]; /* UND bank 13..14, SPSR */
46 uint32_t irq_r[3]; /* IRQ bank 13..14, SPSR */
47 uint32_t fiq_r[8]; /* FIQ bank 8..14, SPSR */
49 uint32_t c,n,z,v,t;
51 /* "fake" registers */
52 uint32_t int_pending; /* Mask of CPSR_I and CPSR_F */
53 uint32_t shift_c; /* used for temporary storage of shifter results */
54 uint32_t icount; /* Instruction counter */
55 gboolean running; /* Indicates that the ARM is operational, as opposed to
56 * halted */
57 };
59 #define CPSR_N 0x80000000 /* Negative flag */
60 #define CPSR_Z 0x40000000 /* Zero flag */
61 #define CPSR_C 0x20000000 /* Carry flag */
62 #define CPSR_V 0x10000000 /* Overflow flag */
63 #define CPSR_I 0x00000080 /* Interrupt disable bit */
64 #define CPSR_F 0x00000040 /* Fast interrupt disable bit */
65 #define CPSR_T 0x00000020 /* Thumb mode */
66 #define CPSR_MODE 0x0000001F /* Current execution mode */
67 #define CPSR_COMPACT_MASK 0x0FFFFFDF /* Mask excluding all separated flags */
69 #define MODE_USER 0x10 /* User mode */
70 #define MODE_FIQ 0x11 /* Fast IRQ mode */
71 #define MODE_IRQ 0x12 /* IRQ mode */
72 #define MODE_SVC 0x13 /* Supervisor mode */
73 #define MODE_ABT 0x17 /* Abort mode */
74 #define MODE_UND 0x1B /* Undefined mode */
75 #define MODE_SYS 0x1F /* System mode */
77 #define IS_PRIVILEGED_MODE() ((armr.cpsr & CPSR_MODE) != MODE_USER)
78 #define IS_EXCEPTION_MODE() (IS_PRIVILEGED_MODE() && (armr.cpsr & CPSR_MODE) != MODE_SYS)
79 #define IS_FIQ_MODE() ((armr.cpsr & CPSR_MODE) == MODE_FIQ)
81 extern struct arm_registers armr;
83 #define CARRY_FLAG (armr.cpsr&CPSR_C)
85 /* ARM core functions */
86 void arm_reset( void );
87 uint32_t arm_run_slice( uint32_t nanosecs );
88 void arm_save_state( FILE *f );
89 int arm_load_state( FILE *f );
90 gboolean arm_execute_instruction( void );
91 void arm_set_breakpoint( uint32_t pc, int type );
92 gboolean arm_clear_breakpoint( uint32_t pc, int type );
93 int arm_get_breakpoint( uint32_t pc );
95 /* ARM Memory */
96 uint32_t arm_read_long( uint32_t addr );
97 uint32_t arm_read_word( uint32_t addr );
98 uint32_t arm_read_byte( uint32_t addr );
99 uint32_t arm_read_long_user( uint32_t addr );
100 uint32_t arm_read_byte_user( uint32_t addr );
101 void arm_write_long( uint32_t addr, uint32_t val );
102 void arm_write_word( uint32_t addr, uint32_t val );
103 void arm_write_byte( uint32_t addr, uint32_t val );
104 void arm_write_long_user( uint32_t addr, uint32_t val );
105 void arm_write_byte_user( uint32_t addr, uint32_t val );
106 int32_t arm_read_phys_word( uint32_t addr );
107 int arm_has_page( uint32_t addr );
109 #endif /* !dream_armcore_H */
.