lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 653:3202ff01d48e |
| prev | 586:2a3ba82cf243 |
| next | 669:ab344e42bca9 |
| author | nkeynes |
| date | Tue Apr 01 01:04:13 2008 +0000 (16 years ago) |
| permissions | -rw-r--r-- |
| last change | Load mipmap textures from largest-to-smallest (instead of the other way around) - works around bug in the ATI drivers |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include <assert.h>
21 #include "dream.h"
22 #include "eventq.h"
23 #include "display.h"
24 #include "mem.h"
25 #include "asic.h"
26 #include "clock.h"
27 #include "pvr2/pvr2.h"
28 #include "sh4/sh4.h"
29 #define MMIO_IMPL
30 #include "pvr2/pvr2mmio.h"
32 unsigned char *video_base;
34 #define MAX_RENDER_BUFFERS 4
36 #define HPOS_PER_FRAME 0
37 #define HPOS_PER_LINECOUNT 1
39 static void pvr2_init( void );
40 static void pvr2_reset( void );
41 static uint32_t pvr2_run_slice( uint32_t );
42 static void pvr2_save_state( FILE *f );
43 static int pvr2_load_state( FILE *f );
44 static void pvr2_update_raster_posn( uint32_t nanosecs );
45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
47 static render_buffer_t pvr2_next_render_buffer( );
48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
49 uint32_t pvr2_get_sync_status();
51 void pvr2_display_frame( void );
53 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
55 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
56 pvr2_run_slice, NULL,
57 pvr2_save_state, pvr2_load_state };
60 display_driver_t display_driver = NULL;
62 struct pvr2_state {
63 uint32_t frame_count;
64 uint32_t line_count;
65 uint32_t line_remainder;
66 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
67 uint32_t irq_hpos_line;
68 uint32_t irq_hpos_line_count;
69 uint32_t irq_hpos_mode;
70 uint32_t irq_hpos_time_ns; /* Time within the line */
71 uint32_t irq_vpos1;
72 uint32_t irq_vpos2;
73 uint32_t odd_even_field; /* 1 = odd, 0 = even */
74 gboolean palette_changed; /* TRUE if palette has changed since last render */
75 gchar *save_next_render_filename;
76 /* timing */
77 uint32_t dot_clock;
78 uint32_t total_lines;
79 uint32_t line_size;
80 uint32_t line_time_ns;
81 uint32_t vsync_lines;
82 uint32_t hsync_width_ns;
83 uint32_t front_porch_ns;
84 uint32_t back_porch_ns;
85 uint32_t retrace_start_line;
86 uint32_t retrace_end_line;
87 gboolean interlaced;
88 } pvr2_state;
90 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
91 static int render_buffer_count = 0;
92 static render_buffer_t displayed_render_buffer = NULL;
93 static uint32_t displayed_border_colour = 0;
95 /**
96 * Event handler for the hpos callback
97 */
98 static void pvr2_hpos_callback( int eventid ) {
99 asic_event( eventid );
100 pvr2_update_raster_posn(sh4r.slice_cycle);
101 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
102 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
103 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
104 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
105 }
106 }
107 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
108 pvr2_state.irq_hpos_time_ns );
109 }
111 /**
112 * Event handler for the scanline callbacks. Fires the corresponding
113 * ASIC event, and resets the timer for the next field.
114 */
115 static void pvr2_scanline_callback( int eventid ) {
116 asic_event( eventid );
117 pvr2_update_raster_posn(sh4r.slice_cycle);
118 if( eventid == EVENT_SCANLINE1 ) {
119 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
120 } else {
121 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
122 }
123 }
125 static void pvr2_init( void )
126 {
127 int i;
128 register_io_region( &mmio_region_PVR2 );
129 register_io_region( &mmio_region_PVR2PAL );
130 register_io_region( &mmio_region_PVR2TA );
131 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
132 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
133 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
134 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
135 texcache_init();
136 pvr2_reset();
137 pvr2_ta_reset();
138 pvr2_state.save_next_render_filename = NULL;
139 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
140 render_buffers[i] = NULL;
141 }
142 render_buffer_count = 0;
143 displayed_render_buffer = NULL;
144 displayed_border_colour = 0;
145 }
147 static void pvr2_reset( void )
148 {
149 int i;
150 pvr2_state.line_count = 0;
151 pvr2_state.line_remainder = 0;
152 pvr2_state.cycles_run = 0;
153 pvr2_state.irq_vpos1 = 0;
154 pvr2_state.irq_vpos2 = 0;
155 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
156 pvr2_state.back_porch_ns = 4000;
157 pvr2_state.palette_changed = FALSE;
158 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
159 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
160 mmio_region_PVR2_write( YUV_ADDR, 0 );
161 mmio_region_PVR2_write( YUV_CFG, 0 );
163 pvr2_ta_init();
164 texcache_flush();
165 if( display_driver ) {
166 display_driver->display_blank(0);
167 for( i=0; i<render_buffer_count; i++ ) {
168 display_driver->destroy_render_buffer(render_buffers[i]);
169 render_buffers[i] = NULL;
170 }
171 render_buffer_count = 0;
172 }
173 }
175 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
176 {
177 struct frame_buffer fbuf;
179 fbuf.width = buffer->width;
180 fbuf.height = buffer->height;
181 fbuf.rowstride = fbuf.width*3;
182 fbuf.colour_format = COLFMT_BGR888;
183 fbuf.inverted = buffer->inverted;
184 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
186 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
187 write_png_to_stream( f, &fbuf );
188 g_free( fbuf.data );
190 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
191 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
192 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
193 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
194 fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
196 }
198 render_buffer_t pvr2_load_render_buffer( FILE *f )
199 {
200 frame_buffer_t frame = read_png_from_stream( f );
201 if( frame == NULL ) {
202 return NULL;
203 }
205 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
206 if( buffer != NULL ) {
207 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
208 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
209 fread( &buffer->address, sizeof(buffer->address), 1, f );
210 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
211 fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
212 } else {
213 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
214 sizeof(buffer->address)+sizeof(buffer->scale)+
215 sizeof(buffer->flushed), SEEK_CUR );
216 }
217 return buffer;
218 }
223 void pvr2_save_render_buffers( FILE *f )
224 {
225 int i;
226 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
227 if( displayed_render_buffer != NULL ) {
228 i = 1;
229 fwrite( &i, sizeof(i), 1, f );
230 pvr2_save_render_buffer( f, displayed_render_buffer );
231 } else {
232 i = 0;
233 fwrite( &i, sizeof(i), 1, f );
234 }
236 for( i=0; i<render_buffer_count; i++ ) {
237 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
238 pvr2_save_render_buffer( f, render_buffers[i] );
239 }
240 }
241 }
243 gboolean pvr2_load_render_buffers( FILE *f )
244 {
245 uint32_t count;
246 int i, has_frontbuffer;
248 fread( &count, sizeof(count), 1, f );
249 if( count > MAX_RENDER_BUFFERS ) {
250 return FALSE;
251 }
252 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
253 for( i=0; i<render_buffer_count; i++ ) {
254 display_driver->destroy_render_buffer(render_buffers[i]);
255 render_buffers[i] = NULL;
256 }
257 render_buffer_count = 0;
259 if( has_frontbuffer ) {
260 displayed_render_buffer = pvr2_load_render_buffer(f);
261 display_driver->display_render_buffer( displayed_render_buffer );
262 count--;
263 }
265 for( i=0; i<count; i++ ) {
266 pvr2_load_render_buffer( f );
267 }
268 return TRUE;
269 }
272 static void pvr2_save_state( FILE *f )
273 {
274 pvr2_save_render_buffers( f );
275 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
276 pvr2_ta_save_state( f );
277 pvr2_yuv_save_state( f );
278 }
280 static int pvr2_load_state( FILE *f )
281 {
282 if( !pvr2_load_render_buffers(f) )
283 return 1;
284 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
285 return 1;
286 if( pvr2_ta_load_state(f) ) {
287 return 1;
288 }
289 return pvr2_yuv_load_state(f);
290 }
292 /**
293 * Update the current raster position to the given number of nanoseconds,
294 * relative to the last time slice. (ie the raster will be adjusted forward
295 * by nanosecs - nanosecs_already_run_this_timeslice)
296 */
297 static void pvr2_update_raster_posn( uint32_t nanosecs )
298 {
299 uint32_t old_line_count = pvr2_state.line_count;
300 if( pvr2_state.line_time_ns == 0 ) {
301 return; /* do nothing */
302 }
303 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
304 pvr2_state.cycles_run = nanosecs;
305 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
306 pvr2_state.line_count ++;
307 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
308 }
310 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
311 pvr2_state.line_count -= pvr2_state.total_lines;
312 if( pvr2_state.interlaced ) {
313 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
314 }
315 }
316 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
317 (old_line_count < pvr2_state.retrace_end_line ||
318 old_line_count > pvr2_state.line_count) ) {
319 pvr2_state.frame_count++;
320 pvr2_display_frame();
321 }
322 }
324 static uint32_t pvr2_run_slice( uint32_t nanosecs )
325 {
326 pvr2_update_raster_posn( nanosecs );
327 pvr2_state.cycles_run = 0;
328 return nanosecs;
329 }
331 int pvr2_get_frame_count()
332 {
333 return pvr2_state.frame_count;
334 }
336 render_buffer_t pvr2_get_front_buffer()
337 {
338 return displayed_render_buffer;
339 }
341 uint32_t pvr2_get_border_colour()
342 {
343 return displayed_border_colour;
344 }
346 gboolean pvr2_save_next_scene( const gchar *filename )
347 {
348 if( pvr2_state.save_next_render_filename != NULL ) {
349 g_free( pvr2_state.save_next_render_filename );
350 }
351 pvr2_state.save_next_render_filename = g_strdup(filename);
352 return TRUE;
353 }
357 /**
358 * Display the next frame, copying the current contents of video ram to
359 * the window. If the video configuration has changed, first recompute the
360 * new frame size/depth.
361 */
362 void pvr2_display_frame( void )
363 {
364 int dispmode = MMIO_READ( PVR2, DISP_MODE );
365 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
366 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
368 if( display_driver == NULL ) {
369 return; /* can't really do anything much */
370 } else if( !bEnabled ) {
371 /* Output disabled == black */
372 displayed_render_buffer = NULL;
373 displayed_border_colour = 0;
374 display_driver->display_blank( 0 );
375 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
376 /* Enabled but blanked - border colour */
377 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
378 displayed_render_buffer = NULL;
379 display_driver->display_blank( displayed_border_colour );
380 } else {
381 /* Real output - determine dimensions etc */
382 struct frame_buffer fbuf;
383 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
384 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
385 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
387 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
388 fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
389 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
390 fbuf.size = vid_ppl << 2 * fbuf.height;
391 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
393 /* Determine the field to display, and deinterlace if possible */
394 if( pvr2_state.interlaced ) {
395 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
396 fbuf.height = fbuf.height << 1;
397 fbuf.rowstride = vid_ppl << 2;
398 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
399 } else {
400 /* Just display the field as is, folks. This is slightly tricky -
401 * we pick the field based on which frame is about to come through,
402 * which may not be the same as the odd_even_field.
403 */
404 gboolean oddfield = pvr2_state.odd_even_field;
405 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
406 oddfield = !oddfield;
407 }
408 if( oddfield ) {
409 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
410 } else {
411 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
412 }
413 }
414 } else {
415 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
416 }
417 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
418 fbuf.inverted = FALSE;
419 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
421 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
422 if( rbuf == NULL ) {
423 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
424 }
425 displayed_render_buffer = rbuf;
426 if( rbuf != NULL ) {
427 display_driver->display_render_buffer( rbuf );
428 }
429 }
430 }
432 /**
433 * This has to handle every single register individually as they all get masked
434 * off differently (and its easier to do it at write time)
435 */
436 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
437 {
438 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
439 MMIO_WRITE( PVR2, reg, val );
440 return;
441 }
443 switch(reg) {
444 case PVRID:
445 case PVRVER:
446 case GUNPOS: /* Read only registers */
447 break;
448 case PVRRESET:
449 val &= 0x00000007; /* Do stuff? */
450 MMIO_WRITE( PVR2, reg, val );
451 break;
452 case RENDER_START: /* Don't really care what value */
453 if( pvr2_state.save_next_render_filename != NULL ) {
454 if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
455 INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
456 }
457 g_free( pvr2_state.save_next_render_filename );
458 pvr2_state.save_next_render_filename = NULL;
459 }
460 pvr2_scene_read();
461 render_buffer_t buffer = pvr2_next_render_buffer();
462 if( buffer != NULL ) {
463 pvr2_scene_render( buffer );
464 }
465 asic_event( EVENT_PVR_RENDER_DONE );
466 break;
467 case RENDER_POLYBASE:
468 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
469 break;
470 case RENDER_TSPCFG:
471 MMIO_WRITE( PVR2, reg, val&0x00010101 );
472 break;
473 case DISP_BORDER:
474 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
475 break;
476 case DISP_MODE:
477 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
478 break;
479 case RENDER_MODE:
480 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
481 break;
482 case RENDER_SIZE:
483 MMIO_WRITE( PVR2, reg, val&0x000001FF );
484 break;
485 case DISP_ADDR1:
486 val &= 0x00FFFFFC;
487 MMIO_WRITE( PVR2, reg, val );
488 pvr2_update_raster_posn(sh4r.slice_cycle);
489 break;
490 case DISP_ADDR2:
491 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
492 pvr2_update_raster_posn(sh4r.slice_cycle);
493 break;
494 case DISP_SIZE:
495 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
496 break;
497 case RENDER_ADDR1:
498 case RENDER_ADDR2:
499 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
500 break;
501 case RENDER_HCLIP:
502 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
503 break;
504 case RENDER_VCLIP:
505 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
506 break;
507 case DISP_HPOSIRQ:
508 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
509 pvr2_state.irq_hpos_line = val & 0x03FF;
510 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
511 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
512 switch( pvr2_state.irq_hpos_mode ) {
513 case 3: /* Reserved - treat as 0 */
514 case 0: /* Once per frame at specified line */
515 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
516 break;
517 case 2: /* Once per line - as per-line-count */
518 pvr2_state.irq_hpos_line = 1;
519 pvr2_state.irq_hpos_mode = 1;
520 case 1: /* Once per N lines */
521 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
522 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
523 pvr2_state.irq_hpos_line_count;
524 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
525 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
526 }
527 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
528 }
529 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
530 pvr2_state.irq_hpos_time_ns );
531 break;
532 case DISP_VPOSIRQ:
533 val = val & 0x03FF03FF;
534 pvr2_state.irq_vpos1 = (val >> 16);
535 pvr2_state.irq_vpos2 = val & 0x03FF;
536 pvr2_update_raster_posn(sh4r.slice_cycle);
537 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
538 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
539 MMIO_WRITE( PVR2, reg, val );
540 break;
541 case RENDER_NEARCLIP:
542 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
543 break;
544 case RENDER_SHADOW:
545 MMIO_WRITE( PVR2, reg, val&0x000001FF );
546 break;
547 case RENDER_OBJCFG:
548 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
549 break;
550 case RENDER_TSPCLIP:
551 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
552 break;
553 case RENDER_FARCLIP:
554 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
555 break;
556 case RENDER_BGPLANE:
557 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
558 break;
559 case RENDER_ISPCFG:
560 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
561 break;
562 case VRAM_CFG1:
563 MMIO_WRITE( PVR2, reg, val&0x000000FF );
564 break;
565 case VRAM_CFG2:
566 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
567 break;
568 case VRAM_CFG3:
569 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
570 break;
571 case RENDER_FOGTBLCOL:
572 case RENDER_FOGVRTCOL:
573 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
574 break;
575 case RENDER_FOGCOEFF:
576 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
577 break;
578 case RENDER_CLAMPHI:
579 case RENDER_CLAMPLO:
580 MMIO_WRITE( PVR2, reg, val );
581 break;
582 case RENDER_TEXSIZE:
583 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
584 break;
585 case RENDER_PALETTE:
586 MMIO_WRITE( PVR2, reg, val&0x00000003 );
587 break;
588 case RENDER_ALPHA_REF:
589 MMIO_WRITE( PVR2, reg, val&0x000000FF );
590 break;
591 /********** CRTC registers *************/
592 case DISP_HBORDER:
593 case DISP_VBORDER:
594 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
595 break;
596 case DISP_TOTAL:
597 val = val & 0x03FF03FF;
598 MMIO_WRITE( PVR2, reg, val );
599 pvr2_update_raster_posn(sh4r.slice_cycle);
600 pvr2_state.total_lines = (val >> 16) + 1;
601 pvr2_state.line_size = (val & 0x03FF) + 1;
602 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
603 pvr2_state.retrace_end_line = 0x2A;
604 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
605 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
606 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
607 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
608 pvr2_state.irq_hpos_time_ns );
609 break;
610 case DISP_SYNCCFG:
611 MMIO_WRITE( PVR2, reg, val&0x000003FF );
612 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
613 break;
614 case DISP_SYNCTIME:
615 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
616 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
617 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
618 break;
619 case DISP_CFG2:
620 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
621 break;
622 case DISP_HPOS:
623 val = val & 0x03FF;
624 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
625 MMIO_WRITE( PVR2, reg, val );
626 break;
627 case DISP_VPOS:
628 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
629 break;
631 /*********** Tile accelerator registers ***********/
632 case TA_POLYPOS:
633 case TA_LISTPOS:
634 /* Readonly registers */
635 break;
636 case TA_TILEBASE:
637 case TA_LISTEND:
638 case TA_LISTBASE:
639 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
640 break;
641 case RENDER_TILEBASE:
642 case TA_POLYBASE:
643 case TA_POLYEND:
644 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
645 break;
646 case TA_TILESIZE:
647 MMIO_WRITE( PVR2, reg, val&0x000F003F );
648 break;
649 case TA_TILECFG:
650 MMIO_WRITE( PVR2, reg, val&0x00133333 );
651 break;
652 case TA_INIT:
653 if( val & 0x80000000 )
654 pvr2_ta_init();
655 break;
656 case TA_REINIT:
657 break;
658 /**************** Scaler registers? ****************/
659 case RENDER_SCALER:
660 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
661 break;
663 case YUV_ADDR:
664 val = val & 0x00FFFFF8;
665 MMIO_WRITE( PVR2, reg, val );
666 pvr2_yuv_init( val );
667 break;
668 case YUV_CFG:
669 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
670 pvr2_yuv_set_config(val);
671 break;
673 /**************** Unknowns ***************/
674 case PVRUNK1:
675 MMIO_WRITE( PVR2, reg, val&0x000007FF );
676 break;
677 case PVRUNK2:
678 MMIO_WRITE( PVR2, reg, val&0x00000007 );
679 break;
680 case PVRUNK3:
681 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
682 break;
683 case PVRUNK5:
684 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
685 break;
686 case PVRUNK7:
687 MMIO_WRITE( PVR2, reg, val&0x00000001 );
688 break;
689 }
690 }
692 /**
693 * Calculate the current read value of the syncstat register, using
694 * the current SH4 clock time as an offset from the last timeslice.
695 * The register reads (LSB to MSB) as:
696 * 0..9 Current scan line
697 * 10 Odd/even field (1 = odd, 0 = even)
698 * 11 Display active (including border and overscan)
699 * 12 Horizontal sync off
700 * 13 Vertical sync off
701 * Note this method is probably incorrect for anything other than straight
702 * interlaced PAL/NTSC, and needs further testing.
703 */
704 uint32_t pvr2_get_sync_status()
705 {
706 pvr2_update_raster_posn(sh4r.slice_cycle);
707 uint32_t result = pvr2_state.line_count;
709 if( pvr2_state.odd_even_field ) {
710 result |= 0x0400;
711 }
712 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
713 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
714 result |= 0x1000; /* !HSYNC */
715 }
716 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
717 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
718 result |= 0x2800; /* Display active */
719 } else {
720 result |= 0x2000; /* Front porch */
721 }
722 }
723 } else {
724 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
725 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
726 result |= 0x3800; /* Display active */
727 } else {
728 result |= 0x3000;
729 }
730 } else {
731 result |= 0x1000; /* Back porch */
732 }
733 }
734 return result;
735 }
737 /**
738 * Schedule a "scanline" event. This actually goes off at
739 * 2 * line in even fields and 2 * line + 1 in odd fields.
740 * Otherwise this behaves as per pvr2_schedule_line_event().
741 * The raster position should be updated before calling this
742 * method.
743 * @param eventid Event to fire at the specified time
744 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
745 * displays).
746 * @param hpos_ns Nanoseconds into the line at which to fire.
747 */
748 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
749 {
750 uint32_t field = pvr2_state.odd_even_field;
751 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
752 field = !field;
753 }
754 if( hpos_ns > pvr2_state.line_time_ns ) {
755 hpos_ns = pvr2_state.line_time_ns;
756 }
758 line <<= 1;
759 if( field ) {
760 line += 1;
761 }
763 if( line < pvr2_state.total_lines ) {
764 uint32_t lines;
765 uint32_t time;
766 if( line <= pvr2_state.line_count ) {
767 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
768 } else {
769 lines = (line - pvr2_state.line_count);
770 }
771 if( lines <= minimum_lines ) {
772 lines += pvr2_state.total_lines;
773 }
774 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
775 event_schedule( eventid, time );
776 } else {
777 event_cancel( eventid );
778 }
779 }
781 MMIO_REGION_READ_FN( PVR2, reg )
782 {
783 switch( reg ) {
784 case DISP_SYNCSTAT:
785 return pvr2_get_sync_status();
786 default:
787 return MMIO_READ( PVR2, reg );
788 }
789 }
791 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
792 {
793 MMIO_WRITE( PVR2PAL, reg, val );
794 pvr2_state.palette_changed = TRUE;
795 }
797 void pvr2_check_palette_changed()
798 {
799 if( pvr2_state.palette_changed ) {
800 texcache_invalidate_palette();
801 pvr2_state.palette_changed = FALSE;
802 }
803 }
805 MMIO_REGION_READ_DEFFN( PVR2PAL );
807 void pvr2_set_base_address( uint32_t base )
808 {
809 mmio_region_PVR2_write( DISP_ADDR1, base );
810 }
815 int32_t mmio_region_PVR2TA_read( uint32_t reg )
816 {
817 return 0xFFFFFFFF;
818 }
820 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
821 {
822 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
823 }
825 /**
826 * Find the render buffer corresponding to the requested output frame
827 * (does not consider texture renders).
828 * @return the render_buffer if found, or null if no such buffer.
829 *
830 * Note: Currently does not consider "partial matches", ie partial
831 * frame overlap - it probably needs to do this.
832 */
833 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
834 {
835 int i;
836 for( i=0; i<render_buffer_count; i++ ) {
837 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
838 return render_buffers[i];
839 }
840 }
841 return NULL;
842 }
844 /**
845 * Allocate a render buffer with the requested parameters.
846 * The order of preference is:
847 * 1. An existing buffer with the same address. (not flushed unless the new
848 * size is smaller than the old one).
849 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
850 * is flushed to vram.
851 * 3. A new buffer if one can be created.
852 * 4. The current display buff
853 * Note: The current display field(s) will never be overwritten except as a last
854 * resort.
855 */
856 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
857 {
858 int i;
859 render_buffer_t result = NULL;
861 /* Check existing buffers for an available buffer */
862 for( i=0; i<render_buffer_count; i++ ) {
863 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
864 /* needs to be the right dimensions */
865 if( render_buffers[i]->address == render_addr ) {
866 if( displayed_render_buffer == render_buffers[i] ) {
867 /* Same address, but we can't use it because the
868 * display has it. Mark it as unaddressed for later.
869 */
870 render_buffers[i]->address = -1;
871 } else {
872 /* perfect */
873 result = render_buffers[i];
874 break;
875 }
876 } else if( render_buffers[i]->address == -1 && result == NULL &&
877 displayed_render_buffer != render_buffers[i] ) {
878 result = render_buffers[i];
879 }
881 } else if( render_buffers[i]->address == render_addr ) {
882 /* right address, wrong size - if it's larger, flush it, otherwise
883 * nuke it quietly */
884 if( render_buffers[i]->width * render_buffers[i]->height >
885 width*height ) {
886 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
887 }
888 render_buffers[i]->address = -1;
889 }
890 }
892 /* Nothing available - make one */
893 if( result == NULL ) {
894 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
895 /* maximum buffers reached - need to throw one away */
896 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
897 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
898 for( i=0; i<render_buffer_count; i++ ) {
899 if( render_buffers[i]->address != field1_addr &&
900 render_buffers[i]->address != field2_addr &&
901 render_buffers[i] != displayed_render_buffer ) {
902 /* Never throw away the current "front buffer(s)" */
903 result = render_buffers[i];
904 if( !result->flushed ) {
905 pvr2_render_buffer_copy_to_sh4( result );
906 }
907 if( result->width != width || result->height != height ) {
908 display_driver->destroy_render_buffer(render_buffers[i]);
909 result = display_driver->create_render_buffer(width,height);
910 render_buffers[i] = result;
911 }
912 break;
913 }
914 }
915 } else {
916 result = display_driver->create_render_buffer(width,height);
917 if( result != NULL ) {
918 render_buffers[render_buffer_count++] = result;
919 }
920 }
921 }
923 if( result != NULL ) {
924 result->address = render_addr;
925 }
926 return result;
927 }
929 /**
930 * Allocate a render buffer based on the current rendering settings
931 */
932 render_buffer_t pvr2_next_render_buffer()
933 {
934 render_buffer_t result = NULL;
935 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
936 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
937 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
938 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
940 if( render_addr & 0x01000000 ) { /* vram64 */
941 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
942 } else { /* vram32 */
943 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
944 }
946 int width = pvr2_scene_buffer_width();
947 int height = pvr2_scene_buffer_height();
948 int colour_format = pvr2_render_colour_format[render_mode&0x07];
950 result = pvr2_alloc_render_buffer( render_addr, width, height );
951 /* Setup the buffer */
952 if( result != NULL ) {
953 result->rowstride = render_stride;
954 result->colour_format = colour_format;
955 result->scale = render_scale;
956 result->size = width * height * colour_formats[colour_format].bpp;
957 result->flushed = FALSE;
958 result->inverted = TRUE; // render buffers are inverted normally
959 }
960 return result;
961 }
963 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
964 {
965 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
966 if( result != NULL ) {
967 int bpp = colour_formats[frame->colour_format].bpp;
968 result->rowstride = frame->rowstride;
969 result->colour_format = frame->colour_format;
970 result->scale = 0x400;
971 result->size = frame->width * frame->height * bpp;
972 result->flushed = TRUE;
973 result->inverted = frame->inverted;
974 display_driver->load_frame_buffer( frame, result );
975 }
976 return result;
977 }
980 /**
981 * Invalidate any caching on the supplied address. Specifically, if it falls
982 * within any of the render buffers, flush the buffer back to PVR2 ram.
983 */
984 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
985 {
986 int i;
987 address = address & 0x1FFFFFFF;
988 for( i=0; i<render_buffer_count; i++ ) {
989 uint32_t bufaddr = render_buffers[i]->address;
990 if( bufaddr != -1 && bufaddr <= address &&
991 (bufaddr + render_buffers[i]->size) > address ) {
992 if( !render_buffers[i]->flushed ) {
993 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
994 render_buffers[i]->flushed = TRUE;
995 }
996 if( isWrite ) {
997 render_buffers[i]->address = -1; /* Invalid */
998 }
999 return TRUE; /* should never have overlapping buffers */
1000 }
1001 }
1002 return FALSE;
1003 }
.