2 * $Id: asic.c,v 1.23 2007-01-14 02:54:40 nkeynes Exp $
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE asic_module
28 #include "dreamcast.h"
29 #include "maple/maple.h"
30 #include "gdrom/ide.h"
36 * 1) Does changing the mask after event occurance result in the
37 * interrupt being delivered immediately?
38 * TODO: Logic diagram of ASIC event/interrupt logic.
40 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
41 * practically nothing is publicly known...
44 static void asic_check_cleared_events( void );
45 static void asic_init( void );
46 static void asic_reset( void );
47 static void asic_save_state( FILE *f );
48 static int asic_load_state( FILE *f );
50 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
51 NULL, asic_save_state, asic_load_state };
53 #define G2_BIT5_TICKS 8
54 #define G2_BIT4_TICKS 16
55 #define G2_BIT0_ON_TICKS 24
56 #define G2_BIT0_OFF_TICKS 24
58 struct asic_g2_state {
59 unsigned int last_update_time;
60 unsigned int bit5_off_timer;
61 unsigned int bit4_on_timer;
62 unsigned int bit4_off_timer;
63 unsigned int bit0_on_timer;
64 unsigned int bit0_off_timer;
67 static struct asic_g2_state g2_state;
69 static void asic_init( void )
71 register_io_region( &mmio_region_ASIC );
72 register_io_region( &mmio_region_EXTDMA );
76 static void asic_reset( void )
78 memset( &g2_state, 0, sizeof(g2_state) );
81 static void asic_save_state( FILE *f )
83 fwrite( &g2_state, sizeof(g2_state), 1, f );
86 static int asic_load_state( FILE *f )
88 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
95 /* FIXME: Handle rollover */
96 void asic_g2_write_word()
98 g2_state.last_update_time = sh4r.icount;
99 g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
100 if( g2_state.bit4_off_timer < sh4r.icount )
101 g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
102 g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
103 if( g2_state.bit0_off_timer < sh4r.icount ) {
104 g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
105 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
107 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
109 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
112 static uint32_t g2_read_status()
114 if( sh4r.icount < g2_state.last_update_time ) {
116 if( g2_state.last_update_time < g2_state.bit5_off_timer )
117 g2_state.bit5_off_timer = 0;
118 if( g2_state.last_update_time < g2_state.bit4_off_timer )
119 g2_state.bit4_off_timer = 0;
120 if( g2_state.last_update_time < g2_state.bit4_on_timer )
121 g2_state.bit4_on_timer = 0;
122 if( g2_state.last_update_time < g2_state.bit0_off_timer )
123 g2_state.bit0_off_timer = 0;
124 if( g2_state.last_update_time < g2_state.bit0_on_timer )
125 g2_state.bit0_on_timer = 0;
127 uint32_t val = MMIO_READ( ASIC, G2STATUS );
128 if( g2_state.bit5_off_timer <= sh4r.icount )
130 if( g2_state.bit4_off_timer <= sh4r.icount ||
131 (sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
133 else if( g2_state.bit4_on_timer <= sh4r.icount )
135 if( g2_state.bit0_off_timer <= sh4r.icount )
137 else if( g2_state.bit0_on_timer <= sh4r.icount )
143 void asic_event( int event )
145 int offset = ((event&0x60)>>3);
146 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
148 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
149 intc_raise_interrupt( INT_IRQ13 );
150 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
151 intc_raise_interrupt( INT_IRQ11 );
152 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
153 intc_raise_interrupt( INT_IRQ9 );
156 void asic_clear_event( int event ) {
157 int offset = ((event&0x60)>>3);
158 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
159 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
161 asic_check_cleared_events();
164 void asic_check_cleared_events( )
166 int i, setA = 0, setB = 0, setC = 0;
168 for( i=0; i<3; i++ ) {
169 bits = MMIO_READ( ASIC, PIRQ0 + i );
170 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
171 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
172 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
175 intc_clear_interrupt( INT_IRQ13 );
177 intc_clear_interrupt( INT_IRQ11 );
179 intc_clear_interrupt( INT_IRQ9 );
182 void g2_dma_transfer( int channel )
184 uint32_t offset = channel << 5;
186 if( MMIO_READ( EXTDMA, SPUDMA0CTL1 + offset ) == 1 ) {
187 if( MMIO_READ( EXTDMA, SPUDMA0CTL2 + offset ) == 1 ) {
188 uint32_t extaddr = MMIO_READ( EXTDMA, SPUDMA0EXT + offset );
189 uint32_t sh4addr = MMIO_READ( EXTDMA, SPUDMA0SH4 + offset );
190 uint32_t length = MMIO_READ( EXTDMA, SPUDMA0SIZ + offset ) & 0x1FFFFFFF;
191 uint32_t dir = MMIO_READ( EXTDMA, SPUDMA0DIR + offset );
192 uint32_t mode = MMIO_READ( EXTDMA, SPUDMA0MOD + offset );
194 if( dir == 0 ) { /* SH4 to device */
195 mem_copy_from_sh4( buf, sh4addr, length );
196 mem_copy_to_sh4( extaddr, buf, length );
197 } else { /* Device to SH4 */
198 mem_copy_from_sh4( buf, extaddr, length );
199 mem_copy_to_sh4( sh4addr, buf, length );
201 MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
202 asic_event( EVENT_SPU_DMA0 + channel );
204 MMIO_WRITE( EXTDMA, SPUDMA0CTL2 + offset, 0 );
209 void asic_ide_dma_transfer( )
211 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
212 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
213 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
215 uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
216 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
217 int dir = MMIO_READ( EXTDMA, IDEDMADIR );
219 uint32_t xfer = ide_read_data_dma( addr, length );
220 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
221 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
223 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
230 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
234 val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
238 /* Clear any interrupts */
239 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
240 asic_check_cleared_events();
243 if( val == 0x7611 ) {
245 sh4r.new_pc = sh4r.pc;
247 WARN( "Unknown value %08X written to SYSRESET port", val );
251 MMIO_WRITE( ASIC, reg, val );
253 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
254 maple_handle_buffer( maple_addr );
255 MMIO_WRITE( ASIC, reg, 0 );
258 case PVRDMACTL: /* Initiate PVR DMA transfer */
259 MMIO_WRITE( ASIC, reg, val );
261 uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
262 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
263 char *data = alloca( count );
264 uint32_t rcount = DMAC_get_buffer( 2, data, count );
265 if( rcount != count )
266 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
267 mem_copy_to_sh4( dest_addr, data, rcount );
268 asic_event( EVENT_PVR_DMA );
269 MMIO_WRITE( ASIC, PVRDMACTL, 0 );
270 MMIO_WRITE( ASIC, PVRDMACNT, 0 );
273 case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
274 MMIO_WRITE( ASIC, reg, val );
277 MMIO_WRITE( ASIC, reg, val );
281 int32_t mmio_region_ASIC_read( uint32_t reg )
303 val = MMIO_READ(ASIC, reg);
306 return g2_read_status();
308 val = MMIO_READ(ASIC, reg);
314 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
316 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
317 return; /* disabled */
321 case IDEALTSTATUS: /* Device control */
322 ide_write_control( val );
325 ide_write_data_pio( val );
328 if( ide_can_write_regs() )
329 idereg.feature = (uint8_t)val;
332 if( ide_can_write_regs() )
333 idereg.count = (uint8_t)val;
336 if( ide_can_write_regs() )
337 idereg.lba0 = (uint8_t)val;
340 if( ide_can_write_regs() )
341 idereg.lba1 = (uint8_t)val;
344 if( ide_can_write_regs() )
345 idereg.lba2 = (uint8_t)val;
348 if( ide_can_write_regs() )
349 idereg.device = (uint8_t)val;
352 if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
353 ide_write_command( (uint8_t)val );
358 MMIO_WRITE( EXTDMA, reg, val );
359 asic_ide_dma_transfer( );
362 if( val == 0x001FFFFF ) {
363 idereg.interface_enabled = TRUE;
364 /* Conventional wisdom says that this is necessary but not
365 * sufficient to enable the IDE interface.
367 } else if( val == 0x000042FE ) {
368 idereg.interface_enabled = FALSE;
373 MMIO_WRITE( EXTDMA, reg, val );
374 g2_dma_transfer( 0 );
380 MMIO_WRITE( EXTDMA, reg, val );
381 g2_dma_transfer( 1 );
388 MMIO_WRITE( EXTDMA, reg, val );
389 g2_dma_transfer( 2 );
395 MMIO_WRITE( EXTDMA, reg, val );
396 g2_dma_transfer( 3 );
403 ERROR( "Write to unimplemented DMA control register %08X", reg );
409 MMIO_WRITE( EXTDMA, reg, val );
413 MMIO_REGION_READ_FN( EXTDMA, reg )
416 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
417 return 0xFFFFFFFF; /* disabled */
424 case IDEDATA: return ide_read_data_pio( );
425 case IDEFEAT: return idereg.error;
426 case IDECOUNT:return idereg.count;
427 case IDELBA0: return idereg.disc;
428 case IDELBA1: return idereg.lba1;
429 case IDELBA2: return idereg.lba2;
430 case IDEDEV: return idereg.device;
432 val = ide_read_status();
435 val = MMIO_READ( EXTDMA, reg );
.