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lxdream.org :: lxdream :: r163:cf6b5e87f58d
lxdream 0.9.1
released Jun 29
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changeset163:cf6b5e87f58d
parent162:f7781f928f7e
child164:84f6b203cfe1
authornkeynes
dateSun Jun 18 11:58:47 2006 +0000 (13 years ago)
Handle G2 timer rollover
src/asic.c
1.1 --- a/src/asic.c Sun Jun 18 11:57:55 2006 +0000
1.2 +++ b/src/asic.c Sun Jun 18 11:58:47 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.16 2006-06-15 10:32:38 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.17 2006-06-18 11:58:47 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -56,6 +56,7 @@
1.11 #define G2_BIT0_OFF_TICKS 24
1.12
1.13 struct asic_g2_state {
1.14 + unsigned int last_update_time;
1.15 unsigned int bit5_off_timer;
1.16 unsigned int bit4_on_timer;
1.17 unsigned int bit4_off_timer;
1.18 @@ -69,7 +70,6 @@
1.19 {
1.20 register_io_region( &mmio_region_ASIC );
1.21 register_io_region( &mmio_region_EXTDMA );
1.22 - mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
1.23 asic_reset();
1.24 }
1.25
1.26 @@ -95,6 +95,7 @@
1.27 /* FIXME: Handle rollover */
1.28 void asic_g2_write_word()
1.29 {
1.30 + g2_state.last_update_time = sh4r.icount;
1.31 g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
1.32 if( g2_state.bit4_off_timer < sh4r.icount )
1.33 g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
1.34 @@ -110,10 +111,24 @@
1.35
1.36 static uint32_t g2_read_status()
1.37 {
1.38 + if( sh4r.icount < g2_state.last_update_time ) {
1.39 + /* Rollover */
1.40 + if( g2_state.last_update_time < g2_state.bit5_off_timer )
1.41 + g2_state.bit5_off_timer = 0;
1.42 + if( g2_state.last_update_time < g2_state.bit4_off_timer )
1.43 + g2_state.bit4_off_timer = 0;
1.44 + if( g2_state.last_update_time < g2_state.bit4_on_timer )
1.45 + g2_state.bit4_on_timer = 0;
1.46 + if( g2_state.last_update_time < g2_state.bit0_off_timer )
1.47 + g2_state.bit0_off_timer = 0;
1.48 + if( g2_state.last_update_time < g2_state.bit0_on_timer )
1.49 + g2_state.bit0_on_timer = 0;
1.50 + }
1.51 uint32_t val = MMIO_READ( ASIC, G2STATUS );
1.52 if( g2_state.bit5_off_timer <= sh4r.icount )
1.53 val = val & (~0x20);
1.54 - if( g2_state.bit4_off_timer <= sh4r.icount )
1.55 + if( g2_state.bit4_off_timer <= sh4r.icount ||
1.56 + (sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
1.57 val = val & (~0x10);
1.58 else if( g2_state.bit4_on_timer <= sh4r.icount )
1.59 val = val | 0x10;
1.60 @@ -225,8 +240,6 @@
1.61 break;
1.62 default:
1.63 MMIO_WRITE( ASIC, reg, val );
1.64 - WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
1.65 - reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
1.66 }
1.67 }
1.68
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