filename | src/pvr2/pvr2.c |
changeset | 35:21a4be098304 |
prev | 31:495e480360d7 |
next | 56:3224dceaf2a3 |
author | nkeynes |
date | Mon Dec 26 03:54:55 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Remove modules.h - move definitions into dream.h Add source string to output list (taken from module name) ARM Work in progress |
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nkeynes@31 | 1 | /** |
nkeynes@35 | 2 | * $Id: pvr2.c,v 1.10 2005-12-26 03:54:52 nkeynes Exp $ |
nkeynes@31 | 3 | * |
nkeynes@31 | 4 | * PVR2 (Video) MMIO and supporting functions. |
nkeynes@31 | 5 | * |
nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@31 | 7 | * |
nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify |
nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by |
nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@31 | 11 | * (at your option) any later version. |
nkeynes@31 | 12 | * |
nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful, |
nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@31 | 16 | * GNU General Public License for more details. |
nkeynes@31 | 17 | */ |
nkeynes@35 | 18 | #define MODULE pvr2_module |
nkeynes@31 | 19 | |
nkeynes@1 | 20 | #include "dream.h" |
nkeynes@1 | 21 | #include "video.h" |
nkeynes@1 | 22 | #include "mem.h" |
nkeynes@1 | 23 | #include "asic.h" |
nkeynes@1 | 24 | #include "pvr2.h" |
nkeynes@1 | 25 | #define MMIO_IMPL |
nkeynes@1 | 26 | #include "pvr2.h" |
nkeynes@1 | 27 | |
nkeynes@1 | 28 | char *video_base; |
nkeynes@1 | 29 | |
nkeynes@15 | 30 | void pvr2_init( void ); |
nkeynes@30 | 31 | uint32_t pvr2_run_slice( uint32_t ); |
nkeynes@23 | 32 | void pvr2_next_frame( void ); |
nkeynes@15 | 33 | |
nkeynes@23 | 34 | struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, |
nkeynes@23 | 35 | pvr2_run_slice, NULL, |
nkeynes@15 | 36 | NULL, NULL }; |
nkeynes@15 | 37 | |
nkeynes@1 | 38 | void pvr2_init( void ) |
nkeynes@1 | 39 | { |
nkeynes@1 | 40 | register_io_region( &mmio_region_PVR2 ); |
nkeynes@1 | 41 | video_base = mem_get_region_by_name( MEM_REGION_VIDEO ); |
nkeynes@1 | 42 | } |
nkeynes@1 | 43 | |
nkeynes@23 | 44 | uint32_t pvr2_time_counter = 0; |
nkeynes@30 | 45 | uint32_t pvr2_time_per_frame = 20000000; |
nkeynes@23 | 46 | |
nkeynes@30 | 47 | uint32_t pvr2_run_slice( uint32_t nanosecs ) |
nkeynes@23 | 48 | { |
nkeynes@30 | 49 | pvr2_time_counter += nanosecs; |
nkeynes@30 | 50 | while( pvr2_time_counter >= pvr2_time_per_frame ) { |
nkeynes@23 | 51 | pvr2_next_frame(); |
nkeynes@23 | 52 | pvr2_time_counter -= pvr2_time_per_frame; |
nkeynes@23 | 53 | } |
nkeynes@30 | 54 | return nanosecs; |
nkeynes@23 | 55 | } |
nkeynes@23 | 56 | |
nkeynes@1 | 57 | uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col; |
nkeynes@1 | 58 | int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0; |
nkeynes@1 | 59 | char *frame_start; /* current video start address (in real memory) */ |
nkeynes@1 | 60 | |
nkeynes@1 | 61 | /* |
nkeynes@1 | 62 | * Display the next frame, copying the current contents of video ram to |
nkeynes@1 | 63 | * the window. If the video configuration has changed, first recompute the |
nkeynes@1 | 64 | * new frame size/depth. |
nkeynes@1 | 65 | */ |
nkeynes@1 | 66 | void pvr2_next_frame( void ) |
nkeynes@1 | 67 | { |
nkeynes@1 | 68 | if( bChanged ) { |
nkeynes@1 | 69 | int dispsize = MMIO_READ( PVR2, DISPSIZE ); |
nkeynes@1 | 70 | int dispmode = MMIO_READ( PVR2, DISPMODE ); |
nkeynes@1 | 71 | int vidcfg = MMIO_READ( PVR2, VIDCFG ); |
nkeynes@1 | 72 | vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1; |
nkeynes@1 | 73 | vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1; |
nkeynes@1 | 74 | vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1; |
nkeynes@1 | 75 | vid_col = (dispmode & DISPMODE_COL); |
nkeynes@1 | 76 | frame_start = video_base + MMIO_READ( PVR2, DISPADDR1 ); |
nkeynes@1 | 77 | interlaced = (vidcfg & VIDCFG_I ? 1 : 0); |
nkeynes@1 | 78 | bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & VIDCFG_VO ) ? 1 : 0; |
nkeynes@1 | 79 | vid_size = (vid_ppl * vid_lpf) << (interlaced ? 3 : 2); |
nkeynes@1 | 80 | vid_hres = vid_ppl; |
nkeynes@1 | 81 | vid_vres = vid_lpf; |
nkeynes@1 | 82 | if( interlaced ) vid_vres <<= 1; |
nkeynes@1 | 83 | switch( vid_col ) { |
nkeynes@1 | 84 | case MODE_RGB15: |
nkeynes@1 | 85 | case MODE_RGB16: vid_hres <<= 1; break; |
nkeynes@1 | 86 | case MODE_RGB24: vid_hres *= 3; break; |
nkeynes@1 | 87 | case MODE_RGB32: vid_hres <<= 2; break; |
nkeynes@1 | 88 | } |
nkeynes@1 | 89 | vid_hres >>= 2; |
nkeynes@1 | 90 | video_update_size( vid_hres, vid_vres, vid_col ); |
nkeynes@1 | 91 | bChanged = 0; |
nkeynes@1 | 92 | } |
nkeynes@1 | 93 | if( bEnabled ) { |
nkeynes@1 | 94 | /* Assume bit depths match for now... */ |
nkeynes@1 | 95 | memcpy( video_data, frame_start, vid_size ); |
nkeynes@1 | 96 | } else { |
nkeynes@1 | 97 | memset( video_data, 0, vid_size ); |
nkeynes@1 | 98 | } |
nkeynes@1 | 99 | video_update_frame(); |
nkeynes@1 | 100 | asic_event( EVENT_SCANLINE1 ); |
nkeynes@1 | 101 | asic_event( EVENT_SCANLINE2 ); |
nkeynes@1 | 102 | asic_event( EVENT_RETRACE ); |
nkeynes@1 | 103 | } |
nkeynes@1 | 104 | |
nkeynes@1 | 105 | void mmio_region_PVR2_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 106 | { |
nkeynes@1 | 107 | if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */ |
nkeynes@1 | 108 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@1 | 109 | /* I don't want to hear about these */ |
nkeynes@1 | 110 | return; |
nkeynes@1 | 111 | } |
nkeynes@1 | 112 | |
nkeynes@1 | 113 | INFO( "PVR2 write to %08X <= %08X [%s: %s]", reg, val, |
nkeynes@1 | 114 | MMIO_REGID(PVR2,reg), MMIO_REGDESC(PVR2,reg) ); |
nkeynes@1 | 115 | |
nkeynes@1 | 116 | switch(reg) { |
nkeynes@1 | 117 | case DISPSIZE: bChanged = 1; |
nkeynes@1 | 118 | case DISPMODE: bChanged = 1; |
nkeynes@1 | 119 | case DISPADDR1: bChanged = 1; |
nkeynes@1 | 120 | case DISPADDR2: bChanged = 1; |
nkeynes@1 | 121 | case VIDCFG: bChanged = 1; |
nkeynes@1 | 122 | break; |
nkeynes@1 | 123 | |
nkeynes@1 | 124 | } |
nkeynes@1 | 125 | MMIO_WRITE( PVR2, reg, val ); |
nkeynes@1 | 126 | } |
nkeynes@1 | 127 | |
nkeynes@1 | 128 | MMIO_REGION_READ_FN( PVR2, reg ) |
nkeynes@1 | 129 | { |
nkeynes@1 | 130 | switch( reg ) { |
nkeynes@1 | 131 | case BEAMPOS: |
nkeynes@2 | 132 | return sh4r.icount&0x20 ? 0x2000 : 1; |
nkeynes@1 | 133 | default: |
nkeynes@1 | 134 | return MMIO_READ( PVR2, reg ); |
nkeynes@1 | 135 | } |
nkeynes@1 | 136 | } |
nkeynes@19 | 137 | |
nkeynes@19 | 138 | void pvr2_set_base_address( uint32_t base ) |
nkeynes@19 | 139 | { |
nkeynes@19 | 140 | mmio_region_PVR2_write( DISPADDR1, base ); |
nkeynes@19 | 141 | } |
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