filename | src/sh4/mem.h |
changeset | 2:42349f6ea216 |
prev | 1:eea311cfd33e |
author | nkeynes |
date | Thu Dec 08 13:38:00 2005 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Generalise the core debug window to allow multiple instances. Add cpu description structure to define different cpus for use by the debug window, in preparation for ARM implementation |
file | annotate | diff | log | raw |
nkeynes@1 | 1 | #ifndef dream_sh4_mem_H |
nkeynes@1 | 2 | #define dream_sh4_mem_H |
nkeynes@1 | 3 | |
nkeynes@1 | 4 | #include <stdint.h> |
nkeynes@1 | 5 | #include "sh4mmio.h" |
nkeynes@1 | 6 | |
nkeynes@1 | 7 | #ifdef __cplusplus |
nkeynes@1 | 8 | extern "C" { |
nkeynes@1 | 9 | #if 0 |
nkeynes@1 | 10 | } |
nkeynes@1 | 11 | #endif |
nkeynes@1 | 12 | #endif |
nkeynes@1 | 13 | |
nkeynes@2 | 14 | typedef struct mem_region { |
nkeynes@1 | 15 | uint32_t base; |
nkeynes@1 | 16 | uint32_t size; |
nkeynes@1 | 17 | char *name; |
nkeynes@1 | 18 | char *mem; |
nkeynes@1 | 19 | int flags; |
nkeynes@2 | 20 | } *mem_region_t; |
nkeynes@1 | 21 | |
nkeynes@1 | 22 | #define MAX_IO_REGIONS 24 |
nkeynes@1 | 23 | #define MAX_MEM_REGIONS 8 |
nkeynes@1 | 24 | |
nkeynes@1 | 25 | #define MEM_REGION_MAIN "System RAM" |
nkeynes@1 | 26 | #define MEM_REGION_VIDEO "Video RAM" |
nkeynes@1 | 27 | #define MEM_REGION_AUDIO "Audio RAM" |
nkeynes@1 | 28 | #define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM" |
nkeynes@1 | 29 | |
nkeynes@1 | 30 | #define MB * (1024 * 1024) |
nkeynes@1 | 31 | #define KB * 1024 |
nkeynes@1 | 32 | |
nkeynes@1 | 33 | int32_t mem_read_long( uint32_t addr ); |
nkeynes@1 | 34 | int32_t mem_read_word( uint32_t addr ); |
nkeynes@1 | 35 | int32_t mem_read_byte( uint32_t addr ); |
nkeynes@1 | 36 | void mem_write_long( uint32_t addr, uint32_t val ); |
nkeynes@1 | 37 | void mem_write_word( uint32_t addr, uint32_t val ); |
nkeynes@1 | 38 | void mem_write_byte( uint32_t addr, uint32_t val ); |
nkeynes@1 | 39 | |
nkeynes@1 | 40 | int32_t mem_read_phys_word( uint32_t addr ); |
nkeynes@1 | 41 | void *mem_create_ram_region( uint32_t base, uint32_t size, char *name ); |
nkeynes@1 | 42 | void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc ); |
nkeynes@1 | 43 | char *mem_get_region( uint32_t addr ); |
nkeynes@1 | 44 | char *mem_get_region_by_name( char *name ); |
nkeynes@1 | 45 | void mem_set_cache_mode( int ); |
nkeynes@1 | 46 | int mem_has_page( uint32_t addr ); |
nkeynes@1 | 47 | |
nkeynes@1 | 48 | void mem_init( void ); |
nkeynes@1 | 49 | void mem_reset( void ); |
nkeynes@1 | 50 | |
nkeynes@2 | 51 | #define ENABLE_WATCH 1 |
nkeynes@2 | 52 | |
nkeynes@2 | 53 | #define WATCH_WRITE 1 |
nkeynes@2 | 54 | #define WATCH_READ 2 |
nkeynes@2 | 55 | #define WATCH_EXEC 3 /* AKA Breakpoint :) */ |
nkeynes@2 | 56 | |
nkeynes@2 | 57 | typedef struct watch_point *watch_point_t; |
nkeynes@2 | 58 | |
nkeynes@2 | 59 | watch_point_t mem_new_watch( uint32_t start, uint32_t end, int flags ); |
nkeynes@2 | 60 | void mem_delete_watch( watch_point_t watch ); |
nkeynes@2 | 61 | watch_point_t mem_is_watched( uint32_t addr, int size, int op ); |
nkeynes@1 | 62 | |
nkeynes@1 | 63 | /* mmucr register bits */ |
nkeynes@1 | 64 | #define MMUCR_AT 0x00000001 /* Address Translation enabled */ |
nkeynes@1 | 65 | #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */ |
nkeynes@1 | 66 | #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */ |
nkeynes@1 | 67 | #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */ |
nkeynes@1 | 68 | #define MMUCR_URC 0x0000FC00 /* UTLB access counter */ |
nkeynes@1 | 69 | #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */ |
nkeynes@1 | 70 | #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */ |
nkeynes@1 | 71 | #define MMUCR_MASK 0xFCFCFF05 |
nkeynes@1 | 72 | #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */ |
nkeynes@1 | 73 | |
nkeynes@1 | 74 | #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT) |
nkeynes@1 | 75 | |
nkeynes@1 | 76 | /* ccr register bits */ |
nkeynes@1 | 77 | #define CCR_IIX 0x00008000 /* IC index enable */ |
nkeynes@1 | 78 | #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */ |
nkeynes@1 | 79 | #define CCR_ICE 0x00000100 /* IC enable */ |
nkeynes@1 | 80 | #define CCR_OIX 0x00000080 /* OC index enable */ |
nkeynes@1 | 81 | #define CCR_ORA 0x00000020 /* OC RAM enable */ |
nkeynes@1 | 82 | #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */ |
nkeynes@1 | 83 | #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */ |
nkeynes@1 | 84 | #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */ |
nkeynes@1 | 85 | #define CCR_OCE 0x00000001 /* OC enable */ |
nkeynes@1 | 86 | #define CCR_MASK 0x000089AF |
nkeynes@1 | 87 | #define CCR_RMASK 0x000081A7 /* Read mask */ |
nkeynes@1 | 88 | |
nkeynes@1 | 89 | #define MEM_OC_DISABLED 0 |
nkeynes@1 | 90 | #define MEM_OC_INDEX0 CCR_ORA |
nkeynes@1 | 91 | #define MEM_OC_INDEX1 CCR_ORA|CCR_OIX |
nkeynes@1 | 92 | |
nkeynes@1 | 93 | #ifdef __cplusplus |
nkeynes@1 | 94 | } |
nkeynes@1 | 95 | #endif |
nkeynes@1 | 96 | #endif |
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