nkeynes@30 | 1 | /**
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nkeynes@54 | 2 | * $Id: sh4mmio.c,v 1.7 2006-01-01 08:08:40 nkeynes Exp $
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nkeynes@30 | 3 | *
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nkeynes@30 | 4 | * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
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nkeynes@30 | 5 | * responsible for including the IMPL side of the SH4 MMIO pages.
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nkeynes@30 | 6 | * Most of these will eventually be split off into their own files.
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nkeynes@30 | 7 | *
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nkeynes@30 | 8 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@30 | 9 | *
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nkeynes@30 | 10 | * This program is free software; you can redistribute it and/or modify
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nkeynes@30 | 11 | * it under the terms of the GNU General Public License as published by
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nkeynes@30 | 12 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@30 | 13 | * (at your option) any later version.
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nkeynes@30 | 14 | *
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nkeynes@30 | 15 | * This program is distributed in the hope that it will be useful,
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nkeynes@30 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@30 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@30 | 18 | * GNU General Public License for more details.
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nkeynes@30 | 19 | */
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nkeynes@35 | 20 | #define MODULE sh4_module
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nkeynes@30 | 21 |
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nkeynes@1 | 22 | #include "dream.h"
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nkeynes@1 | 23 | #include "mem.h"
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nkeynes@19 | 24 | #include "clock.h"
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nkeynes@1 | 25 | #include "sh4core.h"
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nkeynes@1 | 26 | #include "sh4mmio.h"
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nkeynes@1 | 27 | #define MMIO_IMPL
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nkeynes@1 | 28 | #include "sh4mmio.h"
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nkeynes@1 | 29 |
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nkeynes@1 | 30 | /********************************* MMU *************************************/
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nkeynes@1 | 31 |
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nkeynes@1 | 32 | MMIO_REGION_READ_STUBFN( MMU )
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nkeynes@1 | 33 |
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nkeynes@10 | 34 | #define OCRAM_START (0x1C000000>>PAGE_BITS)
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nkeynes@10 | 35 | #define OCRAM_END (0x20000000>>PAGE_BITS)
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nkeynes@10 | 36 |
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nkeynes@10 | 37 | static char *cache = NULL;
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nkeynes@10 | 38 |
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nkeynes@1 | 39 | void mmio_region_MMU_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 40 | {
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nkeynes@1 | 41 | switch(reg) {
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nkeynes@1 | 42 | case CCR:
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nkeynes@10 | 43 | mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
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nkeynes@1 | 44 | INFO( "Cache mode set to %08X", val );
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nkeynes@1 | 45 | break;
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nkeynes@1 | 46 | default:
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nkeynes@1 | 47 | break;
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nkeynes@1 | 48 | }
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nkeynes@1 | 49 | MMIO_WRITE( MMU, reg, val );
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nkeynes@1 | 50 | }
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nkeynes@1 | 51 |
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nkeynes@1 | 52 |
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nkeynes@10 | 53 | void mmu_init()
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nkeynes@10 | 54 | {
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nkeynes@19 | 55 | cache = mem_alloc_pages(2);
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nkeynes@10 | 56 | }
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nkeynes@10 | 57 |
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nkeynes@10 | 58 | void mmu_set_cache_mode( int mode )
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nkeynes@10 | 59 | {
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nkeynes@10 | 60 | uint32_t i;
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nkeynes@10 | 61 | switch( mode ) {
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nkeynes@10 | 62 | case MEM_OC_INDEX0: /* OIX=0 */
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nkeynes@10 | 63 | for( i=OCRAM_START; i<OCRAM_END; i++ )
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nkeynes@10 | 64 | page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
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nkeynes@10 | 65 | break;
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nkeynes@10 | 66 | case MEM_OC_INDEX1: /* OIX=1 */
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nkeynes@10 | 67 | for( i=OCRAM_START; i<OCRAM_END; i++ )
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nkeynes@10 | 68 | page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
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nkeynes@10 | 69 | break;
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nkeynes@10 | 70 | default: /* disabled */
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nkeynes@10 | 71 | for( i=OCRAM_START; i<OCRAM_END; i++ )
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nkeynes@10 | 72 | page_map[i] = NULL;
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nkeynes@10 | 73 | break;
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nkeynes@10 | 74 | }
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nkeynes@10 | 75 | }
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nkeynes@10 | 76 |
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nkeynes@10 | 77 |
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nkeynes@1 | 78 | /********************************* BSC *************************************/
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nkeynes@1 | 79 |
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nkeynes@1 | 80 | uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
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nkeynes@1 | 81 | uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
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nkeynes@1 | 82 | uint32_t bsc_output = 0, bsc_input = 0x0300;
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nkeynes@1 | 83 |
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nkeynes@1 | 84 | void bsc_out( int output, int mask )
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nkeynes@1 | 85 | {
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nkeynes@1 | 86 | /* Go figure... The BIOS won't start without this mess though */
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nkeynes@1 | 87 | if( ((output | (~mask)) & 0x03) == 3 ) {
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nkeynes@1 | 88 | bsc_output |= 0x03;
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nkeynes@1 | 89 | } else {
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nkeynes@1 | 90 | bsc_output &= ~0x03;
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nkeynes@1 | 91 | }
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nkeynes@1 | 92 | }
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nkeynes@1 | 93 |
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nkeynes@1 | 94 | void mmio_region_BSC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 95 | {
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nkeynes@1 | 96 | int i;
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nkeynes@1 | 97 | switch( reg ) {
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nkeynes@1 | 98 | case PCTRA:
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nkeynes@1 | 99 | bsc_input_mask_lo = bsc_output_mask_lo = 0;
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nkeynes@1 | 100 | for( i=0; i<16; i++ ) {
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nkeynes@1 | 101 | int bits = (val >> (i<<1)) & 0x03;
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nkeynes@1 | 102 | if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
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nkeynes@1 | 103 | else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
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nkeynes@1 | 104 | }
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nkeynes@1 | 105 | bsc_output = (bsc_output&0x000F0000) |
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nkeynes@1 | 106 | (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
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nkeynes@1 | 107 | bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
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nkeynes@1 | 108 | bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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nkeynes@1 | 109 | break;
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nkeynes@1 | 110 | case PCTRB:
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nkeynes@1 | 111 | bsc_input_mask_hi = bsc_output_mask_hi = 0;
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nkeynes@1 | 112 | for( i=0; i<4; i++ ) {
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nkeynes@1 | 113 | int bits = (val >> (i>>1)) & 0x03;
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nkeynes@1 | 114 | if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
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nkeynes@1 | 115 | else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
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nkeynes@1 | 116 | }
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nkeynes@1 | 117 | bsc_output = (bsc_output&0xFFFF) |
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nkeynes@1 | 118 | ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
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nkeynes@1 | 119 | break;
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nkeynes@1 | 120 | case PDTRA:
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nkeynes@1 | 121 | bsc_output = (bsc_output&0x000F0000) |
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nkeynes@1 | 122 | (val & bsc_output_mask_lo );
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nkeynes@1 | 123 | bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
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nkeynes@1 | 124 | bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
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nkeynes@1 | 125 | break;
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nkeynes@1 | 126 | case PDTRB:
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nkeynes@1 | 127 | bsc_output = (bsc_output&0xFFFF) |
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nkeynes@1 | 128 | ( (val & bsc_output_mask_hi)<<16 );
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nkeynes@1 | 129 | break;
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nkeynes@1 | 130 | }
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nkeynes@1 | 131 | WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
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nkeynes@1 | 132 | reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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nkeynes@1 | 133 | MMIO_WRITE( BSC, reg, val );
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nkeynes@1 | 134 | }
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nkeynes@1 | 135 |
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nkeynes@1 | 136 | int32_t mmio_region_BSC_read( uint32_t reg )
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nkeynes@1 | 137 | {
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nkeynes@1 | 138 | int32_t val;
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nkeynes@1 | 139 | switch( reg ) {
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nkeynes@1 | 140 | case PDTRA:
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nkeynes@1 | 141 | val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
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nkeynes@1 | 142 | break;
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nkeynes@1 | 143 | case PDTRB:
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nkeynes@1 | 144 | val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
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nkeynes@1 | 145 | break;
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nkeynes@1 | 146 | default:
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nkeynes@1 | 147 | val = MMIO_READ( BSC, reg );
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nkeynes@1 | 148 | }
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nkeynes@1 | 149 | WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 150 | reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
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nkeynes@1 | 151 | return val;
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nkeynes@1 | 152 | }
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nkeynes@1 | 153 |
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nkeynes@1 | 154 | /********************************* UBC *************************************/
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nkeynes@1 | 155 |
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nkeynes@1 | 156 | MMIO_REGION_STUBFNS( UBC )
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nkeynes@1 | 157 |
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nkeynes@1 | 158 |
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nkeynes@1 | 159 | /********************************** SCI *************************************/
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nkeynes@1 | 160 |
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nkeynes@1 | 161 | MMIO_REGION_STUBFNS( SCI )
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nkeynes@1 | 162 |
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