nkeynes@1 | 1 | #include <assert.h>
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nkeynes@1 | 2 | #include "dream.h"
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nkeynes@1 | 3 | #include "mem.h"
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nkeynes@1 | 4 | #include "sh4/intc.h"
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nkeynes@2 | 5 | #include "dreamcast.h"
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nkeynes@15 | 6 | #include "modules.h"
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nkeynes@1 | 7 | #include "maple.h"
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nkeynes@2 | 8 | #include "ide.h"
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nkeynes@15 | 9 | #include "asic.h"
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nkeynes@1 | 10 | #define MMIO_IMPL
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nkeynes@1 | 11 | #include "asic.h"
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nkeynes@1 | 12 | /*
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nkeynes@1 | 13 | * Open questions:
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nkeynes@1 | 14 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 15 | * interrupt being delivered immediately?
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nkeynes@1 | 16 | * 2) If the pending register is not cleared after an interrupt, does
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nkeynes@1 | 17 | * the interrupt line remain high? (ie does the IRQ reoccur?)
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nkeynes@1 | 18 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 19 | *
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nkeynes@1 | 20 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 21 | * practically nothing is publicly known...
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nkeynes@1 | 22 | */
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nkeynes@1 | 23 |
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nkeynes@15 | 24 | struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
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nkeynes@15 | 25 | NULL, NULL };
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nkeynes@15 | 26 |
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nkeynes@1 | 27 | void asic_init( void )
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nkeynes@1 | 28 | {
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nkeynes@1 | 29 | register_io_region( &mmio_region_ASIC );
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nkeynes@1 | 30 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@1 | 31 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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nkeynes@1 | 32 | asic_event( EVENT_GDROM_CMD );
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nkeynes@1 | 33 | }
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nkeynes@1 | 34 |
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nkeynes@1 | 35 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 36 | {
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nkeynes@1 | 37 | switch( reg ) {
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nkeynes@1 | 38 | case PIRQ0:
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nkeynes@1 | 39 | case PIRQ1:
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nkeynes@1 | 40 | case PIRQ2:
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nkeynes@1 | 41 | /* Clear any interrupts */
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nkeynes@1 | 42 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@1 | 43 | break;
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nkeynes@1 | 44 | case MAPLE_STATE:
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nkeynes@1 | 45 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 46 | if( val & 1 ) {
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nkeynes@1 | 47 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@2 | 48 | WARN( "Maple request initiated at %08X, halting", maple_addr );
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nkeynes@2 | 49 | maple_handle_buffer( maple_addr );
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nkeynes@1 | 50 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@2 | 51 | // dreamcast_stop();
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nkeynes@1 | 52 | }
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nkeynes@1 | 53 | break;
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nkeynes@1 | 54 | default:
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nkeynes@1 | 55 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 56 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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nkeynes@1 | 57 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 58 | }
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nkeynes@1 | 59 | }
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nkeynes@1 | 60 |
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nkeynes@1 | 61 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 62 | {
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nkeynes@1 | 63 | int32_t val;
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nkeynes@1 | 64 | switch( reg ) {
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nkeynes@2 | 65 | /*
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nkeynes@2 | 66 | case 0x89C:
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nkeynes@2 | 67 | sh4_stop();
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nkeynes@2 | 68 | return 0x000000B;
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nkeynes@2 | 69 | */
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nkeynes@1 | 70 | case PIRQ0:
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nkeynes@1 | 71 | case PIRQ1:
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nkeynes@1 | 72 | case PIRQ2:
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nkeynes@1 | 73 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 74 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 75 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 76 | return val;
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nkeynes@1 | 77 | case G2STATUS:
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nkeynes@1 | 78 | return 0; /* find out later if there's any cases we actually need to care about */
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nkeynes@1 | 79 | default:
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nkeynes@1 | 80 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 81 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 82 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 83 | return val;
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nkeynes@1 | 84 | }
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nkeynes@1 | 85 |
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nkeynes@1 | 86 | }
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nkeynes@1 | 87 |
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nkeynes@1 | 88 | void asic_event( int event )
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nkeynes@1 | 89 | {
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nkeynes@1 | 90 | int offset = ((event&0x60)>>3);
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nkeynes@1 | 91 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@1 | 92 |
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nkeynes@1 | 93 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@1 | 94 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@1 | 95 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@1 | 96 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@1 | 97 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@1 | 98 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@1 | 99 | }
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nkeynes@1 | 100 |
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nkeynes@1 | 101 |
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nkeynes@1 | 102 |
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nkeynes@1 | 103 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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nkeynes@1 | 104 | {
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nkeynes@2 | 105 | switch( reg ) {
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nkeynes@2 | 106 | case IDEALTSTATUS: /* Device control */
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nkeynes@2 | 107 | ide_write_control( val );
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nkeynes@2 | 108 | break;
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nkeynes@2 | 109 | case IDEDATA:
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nkeynes@2 | 110 | ide_write_data_pio( val );
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nkeynes@2 | 111 | break;
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nkeynes@2 | 112 | case IDEFEAT:
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nkeynes@2 | 113 | if( ide_can_write_regs() )
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nkeynes@2 | 114 | idereg.feature = (uint8_t)val;
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nkeynes@2 | 115 | break;
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nkeynes@2 | 116 | case IDECOUNT:
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nkeynes@2 | 117 | if( ide_can_write_regs() )
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nkeynes@2 | 118 | idereg.count = (uint8_t)val;
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nkeynes@2 | 119 | break;
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nkeynes@2 | 120 | case IDELBA0:
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nkeynes@2 | 121 | if( ide_can_write_regs() )
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nkeynes@2 | 122 | idereg.lba0 = (uint8_t)val;
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nkeynes@2 | 123 | break;
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nkeynes@2 | 124 | case IDELBA1:
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nkeynes@2 | 125 | if( ide_can_write_regs() )
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nkeynes@2 | 126 | idereg.lba1 = (uint8_t)val;
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nkeynes@2 | 127 | break;
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nkeynes@2 | 128 | case IDELBA2:
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nkeynes@2 | 129 | if( ide_can_write_regs() )
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nkeynes@2 | 130 | idereg.lba2 = (uint8_t)val;
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nkeynes@2 | 131 | break;
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nkeynes@2 | 132 | case IDEDEV:
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nkeynes@2 | 133 | if( ide_can_write_regs() )
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nkeynes@2 | 134 | idereg.device = (uint8_t)val;
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nkeynes@2 | 135 | break;
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nkeynes@2 | 136 | case IDECMD:
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nkeynes@2 | 137 | if( ide_can_write_regs() ) {
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nkeynes@2 | 138 | ide_clear_interrupt();
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nkeynes@2 | 139 | ide_write_command( (uint8_t)val );
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nkeynes@2 | 140 | }
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nkeynes@2 | 141 | break;
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nkeynes@2 | 142 |
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nkeynes@2 | 143 | default:
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nkeynes@2 | 144 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@2 | 145 | }
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nkeynes@1 | 146 | }
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nkeynes@1 | 147 |
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nkeynes@1 | 148 | MMIO_REGION_READ_FN( EXTDMA, reg )
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nkeynes@1 | 149 | {
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nkeynes@1 | 150 | switch( reg ) {
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nkeynes@2 | 151 | case IDEALTSTATUS: return idereg.status;
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nkeynes@2 | 152 | case IDEDATA: return ide_read_data_pio( );
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nkeynes@2 | 153 | case IDEFEAT: return idereg.error;
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nkeynes@2 | 154 | case IDECOUNT:return idereg.count;
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nkeynes@2 | 155 | case IDELBA0: return idereg.disc;
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nkeynes@2 | 156 | case IDELBA1: return idereg.lba1;
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nkeynes@2 | 157 | case IDELBA2: return idereg.lba2;
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nkeynes@2 | 158 | case IDEDEV: return idereg.device;
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nkeynes@2 | 159 | case IDECMD:
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nkeynes@2 | 160 | ide_clear_interrupt();
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nkeynes@2 | 161 | return idereg.status;
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nkeynes@1 | 162 | default:
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nkeynes@1 | 163 | return MMIO_READ( EXTDMA, reg );
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nkeynes@1 | 164 | }
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nkeynes@1 | 165 | }
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nkeynes@1 | 166 |
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