nkeynes@31 | 1 | /**
|
nkeynes@56 | 2 | * $Id: pvr2.h,v 1.4 2006-01-01 08:09:42 nkeynes Exp $
|
nkeynes@31 | 3 | *
|
nkeynes@31 | 4 | * PVR2 (video chip) MMIO registers and functions.
|
nkeynes@31 | 5 | *
|
nkeynes@31 | 6 | * Copyright (c) 2005 Nathan Keynes.
|
nkeynes@31 | 7 | *
|
nkeynes@31 | 8 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@31 | 9 | * it under the terms of the GNU General Public License as published by
|
nkeynes@31 | 10 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@31 | 11 | * (at your option) any later version.
|
nkeynes@31 | 12 | *
|
nkeynes@31 | 13 | * This program is distributed in the hope that it will be useful,
|
nkeynes@31 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@31 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@31 | 16 | * GNU General Public License for more details.
|
nkeynes@31 | 17 | */
|
nkeynes@31 | 18 |
|
nkeynes@1 | 19 | #include "mmio.h"
|
nkeynes@1 | 20 |
|
nkeynes@1 | 21 | MMIO_REGION_BEGIN( 0x005F8000, PVR2, "Power VR/2" )
|
nkeynes@1 | 22 | LONG_PORT( 0x000, PVRID, PORT_MR, 0x17FD11DB, "PVR2 Core ID" )
|
nkeynes@1 | 23 | LONG_PORT( 0x004, PVRVER, PORT_MR, 0x00000011, "PVR2 Core Version" )
|
nkeynes@1 | 24 | LONG_PORT( 0x008, PVRRST, PORT_MR, 0, "PVR2 Reset" )
|
nkeynes@1 | 25 | LONG_PORT( 0x014, RENDST, PORT_W, 0, "Start render" )
|
nkeynes@1 | 26 | LONG_PORT( 0x020, OBJBASE, PORT_MRW, 0, "Object buffer base offset" )
|
nkeynes@1 | 27 | LONG_PORT( 0x02C, TILEBASE, PORT_MRW, 0, "Tile buffer base offset" )
|
nkeynes@1 | 28 | LONG_PORT( 0x040, PVRBCOL, PORT_MRW, 0, "Border Colour (RGB)" )
|
nkeynes@1 | 29 | LONG_PORT( 0x044, DISPMODE, PORT_MRW, 0, "Display Mode" )
|
nkeynes@1 | 30 | LONG_PORT( 0x048, RENDMODE, PORT_MRW, 0, "Rendering Mode" )
|
nkeynes@1 | 31 | LONG_PORT( 0x04C, RENDSIZE, PORT_MRW, 0, "Rendering width (bytes/2)" )
|
nkeynes@1 | 32 | LONG_PORT( 0x050, DISPADDR1, PORT_MRW, 0, "Video memory base 1" )
|
nkeynes@1 | 33 | LONG_PORT( 0x054, DISPADDR2, PORT_MRW, 0, "Video memory base 2" )
|
nkeynes@1 | 34 | LONG_PORT( 0x05C, DISPSIZE, PORT_MRW, 0, "Display size" )
|
nkeynes@1 | 35 | LONG_PORT( 0x060, RENDADDR1, PORT_MRW, 0, "Rendering memory base 1" )
|
nkeynes@1 | 36 | LONG_PORT( 0x064, RENDADDR2, PORT_MRW, 0, "Rendering memory base 2" )
|
nkeynes@1 | 37 | LONG_PORT( 0x068, HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
|
nkeynes@1 | 38 | LONG_PORT( 0x06C, VCLIP, PORT_MRW, 0, "Vertical clipping area" )
|
nkeynes@56 | 39 | LONG_PORT( 0x074, SHADOW, PORT_MRW, 0, "Shadowing" )
|
nkeynes@1 | 40 | LONG_PORT( 0x078, OBJCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
|
nkeynes@1 | 41 | LONG_PORT( 0x084, TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
|
nkeynes@1 | 42 | LONG_PORT( 0x088, BGPLANEZ, PORT_MRW, 0, "Background plane depth (float32)" )
|
nkeynes@1 | 43 | LONG_PORT( 0x08C, BGPLANECFG, PORT_MRW, 0, "Background plane config" )
|
nkeynes@1 | 44 | LONG_PORT( 0x0B0, FGTBLCOL, PORT_MRW, 0, "Fog table colour" )
|
nkeynes@1 | 45 | LONG_PORT( 0x0B4, FGVRTCOL, PORT_MRW, 0, "Fog vertex colour" )
|
nkeynes@1 | 46 | LONG_PORT( 0x0B8, FGCOEFF, PORT_MRW, 0, "Fog density coefficient (float16)" )
|
nkeynes@1 | 47 | LONG_PORT( 0x0BC, CLAMPHI, PORT_MRW, 0, "Clamp high colour" )
|
nkeynes@1 | 48 | LONG_PORT( 0x0C0, CLAMPLO, PORT_MRW, 0, "Clamp low colour" )
|
nkeynes@1 | 49 | LONG_PORT( 0x0C4, GUNPOS, PORT_MRW, 0, "Lightgun position" )
|
nkeynes@1 | 50 | LONG_PORT( 0x0CC, EVTPOS, PORT_MRW, 0, "Raster event position" )
|
nkeynes@1 | 51 | LONG_PORT( 0x0D0, VIDCFG, PORT_MRW, 0, "Sync configuration & enable" )
|
nkeynes@1 | 52 | LONG_PORT( 0x0D4, HBORDER, PORT_MRW, 0, "Horizontal border area" )
|
nkeynes@1 | 53 | LONG_PORT( 0x0D8, REFRESH, PORT_MRW, 0, "Refresh rates?" )
|
nkeynes@1 | 54 | LONG_PORT( 0x0DC, VBORDER, PORT_MRW, 0, "Vertical border area" )
|
nkeynes@1 | 55 | LONG_PORT( 0x0E0, SYNCPOS, PORT_MRW, 0, "Sync pulse timing" )
|
nkeynes@1 | 56 | LONG_PORT( 0x0E4, TSPCFG, PORT_MRW, 0, "Texture modulo width" )
|
nkeynes@1 | 57 | LONG_PORT( 0x0E8, VIDCFG2, PORT_MRW, 0, "Video configuration 2" )
|
nkeynes@1 | 58 | LONG_PORT( 0x0F0, VPOS, PORT_MRW, 0, "Vertical display position" )
|
nkeynes@1 | 59 | LONG_PORT( 0x0F4, SCALERCFG, PORT_MRW, 0, "Scaler configuration (?)" )
|
nkeynes@1 | 60 | LONG_PORT( 0x10C, BEAMPOS, PORT_R, 0, "Raster beam position" )
|
nkeynes@1 | 61 | LONG_PORT( 0x124, TAOPBST, PORT_MRW, 0, "TA Object Pointer Buffer start" )
|
nkeynes@1 | 62 | LONG_PORT( 0x128, TAOBST, PORT_MRW, 0, "TA Object Buffer start" )
|
nkeynes@1 | 63 | LONG_PORT( 0x12C, TAOPBEN, PORT_MRW, 0, "TA Object Pointer Buffer end" )
|
nkeynes@1 | 64 | LONG_PORT( 0x130, TAOBEN, PORT_MRW, 0, "TA Object Buffer end" )
|
nkeynes@1 | 65 | LONG_PORT( 0x134, TAOPBPOS, PORT_MRW, 0, "TA Object Pointer Buffer position" )
|
nkeynes@1 | 66 | LONG_PORT( 0x138, TAOBPOS, PORT_MRW, 0, "TA Object Buffer position" )
|
nkeynes@1 | 67 | LONG_PORT( 0x13C, TATBSZ, PORT_MRW, 0, "TA Tile Buffer size" )
|
nkeynes@1 | 68 | LONG_PORT( 0x140, TAOPBCFG, PORT_MRW, 0, "TA Object Pointer Buffer config" )
|
nkeynes@1 | 69 | LONG_PORT( 0x144, TAINIT, PORT_MRW, 0, "TA Initialize" )
|
nkeynes@1 | 70 | LONG_PORT( 0x164, TAOPLST, PORT_MRW, 0, "TA Object Pointer List start" )
|
nkeynes@1 | 71 | MMIO_REGION_END
|
nkeynes@1 | 72 |
|
nkeynes@56 | 73 | MMIO_REGION_BEGIN( 0x10000000, PVR2TA, "Power VR/2 TA Command port" )
|
nkeynes@56 | 74 | LONG_PORT( 0x000, TACMD, PORT_MRW, 0, "TA Command port" )
|
nkeynes@56 | 75 | MMIO_REGION_END
|
nkeynes@1 | 76 |
|
nkeynes@1 | 77 | #define DISPMODE_DE 0x00000001 /* Display enable */
|
nkeynes@1 | 78 | #define DISPMODE_SD 0x00000002 /* Scan double */
|
nkeynes@1 | 79 | #define DISPMODE_COL 0x0000000C /* Colour mode */
|
nkeynes@1 | 80 | #define DISPMODE_CD 0x08000000 /* Clock double */
|
nkeynes@1 | 81 |
|
nkeynes@1 | 82 | #define MODE_RGB15 0x00000000
|
nkeynes@1 | 83 | #define MODE_RGB16 0x00000040
|
nkeynes@1 | 84 | #define MODE_RGB24 0x00000080
|
nkeynes@1 | 85 | #define MODE_RGB32 0x000000C0
|
nkeynes@1 | 86 |
|
nkeynes@1 | 87 | #define DISPSIZE_MODULO 0x3FF00000 /* line skip +1 (32-bit words)*/
|
nkeynes@1 | 88 | #define DISPSIZE_LPF 0x000FFC00 /* lines per field */
|
nkeynes@1 | 89 | #define DISPSIZE_PPL 0x000003FF /* pixel words (32 bit) per line */
|
nkeynes@1 | 90 |
|
nkeynes@1 | 91 | #define VIDCFG_VP 0x00000001 /* V-sync polarity */
|
nkeynes@1 | 92 | #define VIDCFG_HP 0x00000002 /* H-sync polarity */
|
nkeynes@1 | 93 | #define VIDCFG_I 0x00000010 /* Interlace enable */
|
nkeynes@1 | 94 | #define VIDCFG_BS 0x000000C0 /* Broadcast standard */
|
nkeynes@1 | 95 | #define VIDCFG_VO 0x00000100 /* Video output enable */
|
nkeynes@1 | 96 |
|
nkeynes@1 | 97 | #define BS_NTSC 0x00000000
|
nkeynes@1 | 98 | #define BS_PAL 0x00000040
|
nkeynes@1 | 99 | #define BS_PALM 0x00000080 /* ? */
|
nkeynes@1 | 100 | #define BS_PALN 0x000000C0 /* ? */
|
nkeynes@1 | 101 |
|
nkeynes@1 | 102 | void pvr2_next_frame( void );
|
nkeynes@19 | 103 | void pvr2_set_base_address( uint32_t );
|
nkeynes@56 | 104 |
|
nkeynes@56 | 105 | /**
|
nkeynes@56 | 106 | * Process the data in the supplied buffer as an array of TA command lists.
|
nkeynes@56 | 107 | * Any excess bytes are held pending until a complete list is sent
|
nkeynes@56 | 108 | */
|
nkeynes@56 | 109 | void pvr2ta_write( char *buf, uint32_t length );
|