filename | src/sh4/sh4mmio.h |
changeset | 929:fd8cb0c82f5f |
prev | 859:b941c703ccd6 |
next | 939:6f2302afeb89 |
author | nkeynes |
date | Sat Dec 27 02:59:35 2008 +0000 (15 years ago) |
branch | lxdream-mem |
permissions | -rw-r--r-- |
last change | Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode, which tracks the field of the same name in sh4r - actually a little faster this way. Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR flag yet). Also fixed the failure to check the flags in the common case (code address returned by previous block) which took away the performance benefits, but oh well. |
file | annotate | diff | log | raw |
nkeynes@30 | 1 | /** |
nkeynes@561 | 2 | * $Id$ |
nkeynes@826 | 3 | * |
nkeynes@30 | 4 | * MMIO region and supporting function declarations. Private to the sh4 |
nkeynes@30 | 5 | * module. |
nkeynes@30 | 6 | * |
nkeynes@30 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@30 | 8 | * |
nkeynes@30 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@30 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@30 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@30 | 12 | * (at your option) any later version. |
nkeynes@30 | 13 | * |
nkeynes@30 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@30 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@30 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@30 | 17 | * GNU General Public License for more details. |
nkeynes@30 | 18 | */ |
nkeynes@30 | 19 | |
nkeynes@550 | 20 | #include "lxdream.h" |
nkeynes@1 | 21 | #include "mmio.h" |
nkeynes@1 | 22 | |
nkeynes@1 | 23 | #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \ |
nkeynes@1 | 24 | (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE)) |
nkeynes@1 | 25 | |
nkeynes@736 | 26 | #ifdef __cplusplus |
nkeynes@736 | 27 | extern "C" { |
nkeynes@736 | 28 | #endif |
nkeynes@736 | 29 | |
nkeynes@1 | 30 | #ifdef MMIO_IMPL |
nkeynes@1 | 31 | #define SH4MMIO_IMPL |
nkeynes@1 | 32 | #else |
nkeynes@1 | 33 | #define SH4MMIO_IFACE |
nkeynes@1 | 34 | #endif |
nkeynes@1 | 35 | /* SH7750 onchip mmio devices */ |
nkeynes@1 | 36 | |
nkeynes@1 | 37 | MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" ) |
nkeynes@1 | 38 | LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" ) |
nkeynes@1 | 39 | LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" ) |
nkeynes@1 | 40 | LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" ) |
nkeynes@1 | 41 | LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" ) |
nkeynes@1 | 42 | LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" ) |
nkeynes@550 | 43 | BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */ |
nkeynes@550 | 44 | BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */ |
nkeynes@1 | 45 | LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" ) |
nkeynes@1 | 46 | LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" ) |
nkeynes@1 | 47 | LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" ) |
nkeynes@1 | 48 | LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" ) |
nkeynes@826 | 49 | LONG_PORT( 0x02C, MMUUNK1, PORT_MRW, 0, "Unknown MMU/general register" ) |
nkeynes@818 | 50 | LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */ |
nkeynes@1 | 51 | LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" ) |
nkeynes@1 | 52 | LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" ) |
nkeynes@1 | 53 | LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" ) |
nkeynes@819 | 54 | WORD_PORT( 0x084, PMCR1, PORT_MRW, 0, "Performance counter control 1" ) |
nkeynes@819 | 55 | WORD_PORT( 0x088, PMCR2, PORT_MRW, 0, "Performance counter control 2" ) |
nkeynes@819 | 56 | MMIO_REGION_END |
nkeynes@819 | 57 | |
nkeynes@819 | 58 | /* Performance counter values (undocumented) */ |
nkeynes@819 | 59 | MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" ) |
nkeynes@826 | 60 | LONG_PORT( 0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" ) |
nkeynes@826 | 61 | LONG_PORT( 0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" ) |
nkeynes@826 | 62 | LONG_PORT( 0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" ) |
nkeynes@826 | 63 | LONG_PORT( 0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" ) |
nkeynes@1 | 64 | MMIO_REGION_END |
nkeynes@1 | 65 | |
nkeynes@1 | 66 | /* User Break Controller (Page 717 [757] of sh7750h manual) */ |
nkeynes@1 | 67 | MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" ) |
nkeynes@1 | 68 | LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" ) |
nkeynes@1 | 69 | BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" ) |
nkeynes@1 | 70 | WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" ) |
nkeynes@1 | 71 | LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" ) |
nkeynes@1 | 72 | BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" ) |
nkeynes@1 | 73 | WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" ) |
nkeynes@1 | 74 | LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" ) |
nkeynes@1 | 75 | LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" ) |
nkeynes@1 | 76 | WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" ) |
nkeynes@1 | 77 | MMIO_REGION_END |
nkeynes@1 | 78 | /* Bus State Controller (Page 293 [333] of sh7750h manual) |
nkeynes@1 | 79 | * I/O Ports */ |
nkeynes@1 | 80 | MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" ) |
nkeynes@1 | 81 | LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" ) |
nkeynes@1 | 82 | WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" ) |
nkeynes@1 | 83 | LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" ) |
nkeynes@1 | 84 | LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" ) |
nkeynes@1 | 85 | LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" ) |
nkeynes@1 | 86 | LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" ) |
nkeynes@1 | 87 | WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" ) |
nkeynes@1 | 88 | WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" ) |
nkeynes@1 | 89 | WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" ) |
nkeynes@1 | 90 | WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" ) |
nkeynes@1 | 91 | WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" ) |
nkeynes@1 | 92 | LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" ) |
nkeynes@1 | 93 | WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" ) |
nkeynes@1 | 94 | LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" ) |
nkeynes@1 | 95 | WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" ) |
nkeynes@1 | 96 | WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" ) |
nkeynes@1 | 97 | MMIO_REGION_END |
nkeynes@1 | 98 | |
nkeynes@1 | 99 | /* DMA Controller (Page 457 [497] of sh7750h manual) */ |
nkeynes@1 | 100 | MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" ) |
nkeynes@1 | 101 | LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" ) |
nkeynes@1 | 102 | LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" ) |
nkeynes@1 | 103 | LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" ) |
nkeynes@1 | 104 | LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" ) |
nkeynes@1 | 105 | LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" ) |
nkeynes@1 | 106 | LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" ) |
nkeynes@1 | 107 | LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" ) |
nkeynes@1 | 108 | LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" ) |
nkeynes@1 | 109 | LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" ) |
nkeynes@1 | 110 | LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" ) |
nkeynes@1 | 111 | LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" ) |
nkeynes@1 | 112 | LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" ) |
nkeynes@1 | 113 | LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" ) |
nkeynes@1 | 114 | LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" ) |
nkeynes@1 | 115 | LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" ) |
nkeynes@1 | 116 | LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" ) |
nkeynes@1 | 117 | LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" ) |
nkeynes@1 | 118 | MMIO_REGION_END |
nkeynes@1 | 119 | |
nkeynes@859 | 120 | #define FRQCR_CKOEN 0x0800 |
nkeynes@859 | 121 | #define FRQCR_PLL1EN 0x0400 |
nkeynes@859 | 122 | #define FRQCR_PLL2EN 0x0200 |
nkeynes@859 | 123 | #define FRQCR_IFC_MASK 0x01C0 |
nkeynes@859 | 124 | #define FRQCR_BFC_MASK 0x0038 |
nkeynes@859 | 125 | #define FRQCR_PFC_MASK 0x0007 |
nkeynes@859 | 126 | |
nkeynes@1 | 127 | /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */ |
nkeynes@1 | 128 | MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" ) |
nkeynes@859 | 129 | WORD_PORT( 0x000, FRQCR, PORT_MRW, 0x0E0A, "Frequency control" ) |
nkeynes@1 | 130 | BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" ) |
nkeynes@1 | 131 | BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" ) |
nkeynes@1 | 132 | BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" ) |
nkeynes@1 | 133 | BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" ) |
nkeynes@1 | 134 | MMIO_REGION_END |
nkeynes@1 | 135 | |
nkeynes@1 | 136 | /* Real time clock (Page 253 [293] of sh7750h manual) */ |
nkeynes@1 | 137 | MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" ) |
nkeynes@1 | 138 | BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" ) |
nkeynes@1 | 139 | BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" ) |
nkeynes@1 | 140 | /* ... */ |
nkeynes@1 | 141 | MMIO_REGION_END |
nkeynes@1 | 142 | |
nkeynes@1 | 143 | /* Interrupt controller (Page 699 [739] of sh7750h manual) */ |
nkeynes@1 | 144 | MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" ) |
nkeynes@1 | 145 | WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" ) |
nkeynes@1 | 146 | WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" ) |
nkeynes@1 | 147 | WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" ) |
nkeynes@1 | 148 | WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" ) |
nkeynes@1 | 149 | WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" ) |
nkeynes@1 | 150 | MMIO_REGION_END |
nkeynes@1 | 151 | |
nkeynes@1 | 152 | /* Timer unit (Page 277 [317] of sh7750h manual) */ |
nkeynes@1 | 153 | MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" ) |
nkeynes@1 | 154 | BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" ) |
nkeynes@1 | 155 | BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" ) |
nkeynes@1 | 156 | LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" ) |
nkeynes@1 | 157 | LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" ) |
nkeynes@1 | 158 | WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" ) |
nkeynes@1 | 159 | LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" ) |
nkeynes@1 | 160 | LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" ) |
nkeynes@1 | 161 | WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" ) |
nkeynes@1 | 162 | LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" ) |
nkeynes@1 | 163 | LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" ) |
nkeynes@1 | 164 | WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" ) |
nkeynes@1 | 165 | LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" ) |
nkeynes@1 | 166 | MMIO_REGION_END |
nkeynes@1 | 167 | |
nkeynes@1 | 168 | /* Serial channel (page 541 [581] of sh7750h manual) */ |
nkeynes@1 | 169 | MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" ) |
nkeynes@1 | 170 | BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" ) |
nkeynes@1 | 171 | BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" ) |
nkeynes@1 | 172 | BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" ) |
nkeynes@1 | 173 | BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" ) |
nkeynes@1 | 174 | BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" ) |
nkeynes@1 | 175 | BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" ) |
nkeynes@1 | 176 | BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" ) |
nkeynes@1 | 177 | MMIO_REGION_END |
nkeynes@1 | 178 | |
nkeynes@1 | 179 | MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" ) |
nkeynes@1 | 180 | WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" ) |
nkeynes@19 | 181 | BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" ) |
nkeynes@19 | 182 | WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" ) |
nkeynes@19 | 183 | BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" ) |
nkeynes@826 | 184 | WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)" ) |
nkeynes@19 | 185 | BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" ) |
nkeynes@19 | 186 | WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" ) |
nkeynes@19 | 187 | WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" ) |
nkeynes@19 | 188 | WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" ) |
nkeynes@19 | 189 | WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" ) |
nkeynes@1 | 190 | MMIO_REGION_END |
nkeynes@1 | 191 | |
nkeynes@1 | 192 | MMIO_REGION_LIST_BEGIN( sh4mmio ) |
nkeynes@1 | 193 | MMIO_REGION( MMU ) |
nkeynes@1 | 194 | MMIO_REGION( UBC ) |
nkeynes@1 | 195 | MMIO_REGION( BSC ) |
nkeynes@1 | 196 | MMIO_REGION( DMAC ) |
nkeynes@1 | 197 | MMIO_REGION( CPG ) |
nkeynes@1 | 198 | MMIO_REGION( RTC ) |
nkeynes@1 | 199 | MMIO_REGION( INTC ) |
nkeynes@1 | 200 | MMIO_REGION( TMU ) |
nkeynes@1 | 201 | MMIO_REGION( SCI ) |
nkeynes@1 | 202 | MMIO_REGION( SCIF ) |
nkeynes@819 | 203 | MMIO_REGION( PMM ) |
nkeynes@1 | 204 | MMIO_REGION_LIST_END |
nkeynes@1 | 205 | |
nkeynes@10 | 206 | /* mmucr register bits */ |
nkeynes@10 | 207 | #define MMUCR_AT 0x00000001 /* Address Translation enabled */ |
nkeynes@10 | 208 | #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */ |
nkeynes@10 | 209 | #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */ |
nkeynes@10 | 210 | #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */ |
nkeynes@10 | 211 | #define MMUCR_URC 0x0000FC00 /* UTLB access counter */ |
nkeynes@10 | 212 | #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */ |
nkeynes@10 | 213 | #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */ |
nkeynes@10 | 214 | #define MMUCR_MASK 0xFCFCFF05 |
nkeynes@10 | 215 | #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */ |
nkeynes@10 | 216 | |
nkeynes@10 | 217 | #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT) |
nkeynes@10 | 218 | |
nkeynes@10 | 219 | /* ccr register bits */ |
nkeynes@10 | 220 | #define CCR_IIX 0x00008000 /* IC index enable */ |
nkeynes@10 | 221 | #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */ |
nkeynes@10 | 222 | #define CCR_ICE 0x00000100 /* IC enable */ |
nkeynes@10 | 223 | #define CCR_OIX 0x00000080 /* OC index enable */ |
nkeynes@10 | 224 | #define CCR_ORA 0x00000020 /* OC RAM enable */ |
nkeynes@10 | 225 | #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */ |
nkeynes@10 | 226 | #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */ |
nkeynes@10 | 227 | #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */ |
nkeynes@10 | 228 | #define CCR_OCE 0x00000001 /* OC enable */ |
nkeynes@10 | 229 | #define CCR_MASK 0x000089AF |
nkeynes@10 | 230 | #define CCR_RMASK 0x000081A7 /* Read mask */ |
nkeynes@10 | 231 | |
nkeynes@817 | 232 | #define MEM_OC_INDEX0 (CCR_ORA|CCR_OCE) |
nkeynes@817 | 233 | #define MEM_OC_INDEX1 (CCR_ORA|CCR_OIX|CCR_OCE) |
nkeynes@10 | 234 | |
nkeynes@819 | 235 | #define PMCR_CLKF 0x0100 |
nkeynes@819 | 236 | #define PMCR_PMCLR 0x2000 |
nkeynes@819 | 237 | #define PMCR_PMST 0x4000 |
nkeynes@819 | 238 | #define PMCR_PMEN 0x8000 |
nkeynes@841 | 239 | #define PMCR_RUNNING (PMCR_PMST|PMCR_PMEN) |
nkeynes@819 | 240 | |
nkeynes@550 | 241 | /* MMU functions */ |
nkeynes@10 | 242 | void mmu_init(void); |
nkeynes@10 | 243 | void mmu_set_cache_mode( int ); |
nkeynes@550 | 244 | void mmu_ldtlb(void); |
nkeynes@10 | 245 | |
nkeynes@929 | 246 | int32_t FASTCALL mmu_icache_addr_read( sh4addr_t addr ); |
nkeynes@929 | 247 | int32_t FASTCALL mmu_icache_data_read( sh4addr_t addr ); |
nkeynes@929 | 248 | int32_t FASTCALL mmu_itlb_addr_read( sh4addr_t addr ); |
nkeynes@929 | 249 | int32_t FASTCALL mmu_itlb_data_read( sh4addr_t addr ); |
nkeynes@929 | 250 | int32_t FASTCALL mmu_ocache_addr_read( sh4addr_t addr ); |
nkeynes@929 | 251 | int32_t FASTCALL mmu_ocache_data_read( sh4addr_t addr ); |
nkeynes@929 | 252 | int32_t FASTCALL mmu_utlb_addr_read( sh4addr_t addr ); |
nkeynes@929 | 253 | int32_t FASTCALL mmu_utlb_data_read( sh4addr_t addr ); |
nkeynes@929 | 254 | void FASTCALL mmu_icache_addr_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 255 | void FASTCALL mmu_icache_data_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 256 | void FASTCALL mmu_itlb_addr_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 257 | void FASTCALL mmu_itlb_data_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 258 | void FASTCALL mmu_ocache_addr_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 259 | void FASTCALL mmu_ocache_data_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 260 | void FASTCALL mmu_utlb_addr_write( sh4addr_t addr, uint32_t val ); |
nkeynes@929 | 261 | void FASTCALL mmu_utlb_data_write( sh4addr_t addr, uint32_t val ); |
nkeynes@736 | 262 | |
nkeynes@736 | 263 | |
nkeynes@736 | 264 | #ifdef __cplusplus |
nkeynes@736 | 265 | } |
nkeynes@1 | 266 | #endif |
nkeynes@736 | 267 | |
nkeynes@736 | 268 | #endif |
.