1.1 --- a/src/sh4/sh4mmio.h	Sun Dec 11 05:15:36 2005 +0000
     1.2 +++ b/src/sh4/sh4mmio.h	Fri Dec 23 11:44:55 2005 +0000
     1.3 @@ -135,6 +135,15 @@
     1.4  
     1.5  MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
     1.6      WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
     1.7 +    BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
     1.8 +    WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
     1.9 +    BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
    1.10 +    WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)") 
    1.11 +    BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
    1.12 +    WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
    1.13 +    WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
    1.14 +    WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
    1.15 +    WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
    1.16  MMIO_REGION_END
    1.17  
    1.18  MMIO_REGION_LIST_BEGIN( sh4mmio )