1.1 --- a/src/sh4/sh4x86.c	Tue Jan 22 11:30:37 2008 +0000
     1.2 +++ b/src/sh4/sh4x86.c	Wed Apr 16 10:12:12 2008 +0000
     1.3 @@ -761,6 +761,7 @@
     1.4                              case 0x5:
     1.5                                  { /* STS FPUL, Rn */
     1.6                                  uint32_t Rn = ((ir>>8)&0xF); 
     1.7 +                                check_fpuen();
     1.8                                  load_spreg( R_EAX, R_FPUL );
     1.9                                  store_reg( R_EAX, Rn );
    1.10                                  }
    1.11 @@ -768,6 +769,7 @@
    1.12                              case 0x6:
    1.13                                  { /* STS FPSCR, Rn */
    1.14                                  uint32_t Rn = ((ir>>8)&0xF); 
    1.15 +                                check_fpuen();
    1.16                                  load_spreg( R_EAX, R_FPSCR );
    1.17                                  store_reg( R_EAX, Rn );
    1.18                                  }
    1.19 @@ -1441,6 +1443,7 @@
    1.20                              case 0x5:
    1.21                                  { /* STS.L FPUL, @-Rn */
    1.22                                  uint32_t Rn = ((ir>>8)&0xF); 
    1.23 +                                check_fpuen();
    1.24                                  load_reg( R_EAX, Rn );
    1.25                                  check_walign32( R_EAX );
    1.26                                  ADD_imm8s_r32( -4, R_EAX );
    1.27 @@ -1454,6 +1457,7 @@
    1.28                              case 0x6:
    1.29                                  { /* STS.L FPSCR, @-Rn */
    1.30                                  uint32_t Rn = ((ir>>8)&0xF); 
    1.31 +                                check_fpuen();
    1.32                                  load_reg( R_EAX, Rn );
    1.33                                  check_walign32( R_EAX );
    1.34                                  ADD_imm8s_r32( -4, R_EAX );
    1.35 @@ -1702,6 +1706,7 @@
    1.36                              case 0x5:
    1.37                                  { /* LDS.L @Rm+, FPUL */
    1.38                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.39 +                                check_fpuen();
    1.40                                  load_reg( R_EAX, Rm );
    1.41                                  check_ralign32( R_EAX );
    1.42                                  MMU_TRANSLATE_READ( R_EAX );
    1.43 @@ -1714,6 +1719,7 @@
    1.44                              case 0x6:
    1.45                                  { /* LDS.L @Rm+, FPSCR */
    1.46                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.47 +                                check_fpuen();
    1.48                                  load_reg( R_EAX, Rm );
    1.49                                  check_ralign32( R_EAX );
    1.50                                  MMU_TRANSLATE_READ( R_EAX );
    1.51 @@ -1939,6 +1945,7 @@
    1.52                              case 0x5:
    1.53                                  { /* LDS Rm, FPUL */
    1.54                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.55 +                                check_fpuen();
    1.56                                  load_reg( R_EAX, Rm );
    1.57                                  store_spreg( R_EAX, R_FPUL );
    1.58                                  }
    1.59 @@ -1946,6 +1953,7 @@
    1.60                              case 0x6:
    1.61                                  { /* LDS Rm, FPSCR */
    1.62                                  uint32_t Rm = ((ir>>8)&0xF); 
    1.63 +                                check_fpuen();
    1.64                                  load_reg( R_EAX, Rm );
    1.65                                  store_spreg( R_EAX, R_FPSCR );
    1.66                                  update_fr_bank( R_EAX );