lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 124:ceb38f08619a |
| prev | 123:2ad156e10657 |
| next | 157:fbe03268ad8a |
| author | nkeynes |
| date | Wed Mar 22 14:29:02 2006 +0000 (18 years ago) |
| permissions | -rw-r--r-- |
| last change | Rename IDE DMA registers appropriately Remove forced irq hack Add correct irq handling for IDE Miscellaneous WIP for the GD-rom drive |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.c,v 1.26 2006-03-22 14:27:40 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define MAX_INT 0x7FFFFFFF
31 #define MIN_INT 0x80000000
32 #define MAX_INTF 2147483647.0
33 #define MIN_INTF -2147483648.0
35 /* CPU-generated exception code/vector pairs */
36 #define EXC_POWER_RESET 0x000 /* vector special */
37 #define EXC_MANUAL_RESET 0x020
38 #define EXC_SLOT_ILLEGAL 0x1A0
39 #define EXC_ILLEGAL 0x180
40 #define EXV_ILLEGAL 0x100
41 #define EXC_TRAP 0x160
42 #define EXV_TRAP 0x100
43 #define EXC_FPDISABLE 0x800
44 #define EXV_FPDISABLE 0x100
46 /********************** SH4 Module Definition ****************************/
48 void sh4_init( void );
49 void sh4_reset( void );
50 uint32_t sh4_run_slice( uint32_t );
51 void sh4_start( void );
52 void sh4_stop( void );
53 void sh4_save_state( FILE *f );
54 int sh4_load_state( FILE *f );
56 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
57 NULL, sh4_run_slice, sh4_stop,
58 sh4_save_state, sh4_load_state };
60 struct sh4_registers sh4r;
62 void sh4_init(void)
63 {
64 register_io_regions( mmio_list_sh4mmio );
65 mmu_init();
66 sh4_reset();
67 }
69 void sh4_reset(void)
70 {
71 /* zero everything out, for the sake of having a consistent state. */
72 memset( &sh4r, 0, sizeof(sh4r) );
74 /* Resume running if we were halted */
75 sh4r.sh4_state = SH4_STATE_RUNNING;
77 sh4r.pc = 0xA0000000;
78 sh4r.new_pc= 0xA0000002;
79 sh4r.vbr = 0x00000000;
80 sh4r.fpscr = 0x00040001;
81 sh4r.sr = 0x700000F0;
83 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
84 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
86 /* Peripheral modules */
87 intc_reset();
88 SCIF_reset();
89 }
91 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
92 static int sh4_breakpoint_count = 0;
94 void sh4_set_breakpoint( uint32_t pc, int type )
95 {
96 sh4_breakpoints[sh4_breakpoint_count].address = pc;
97 sh4_breakpoints[sh4_breakpoint_count].type = type;
98 sh4_breakpoint_count++;
99 }
101 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
102 {
103 int i;
105 for( i=0; i<sh4_breakpoint_count; i++ ) {
106 if( sh4_breakpoints[i].address == pc &&
107 sh4_breakpoints[i].type == type ) {
108 while( ++i < sh4_breakpoint_count ) {
109 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
110 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
111 }
112 sh4_breakpoint_count--;
113 return TRUE;
114 }
115 }
116 return FALSE;
117 }
119 int sh4_get_breakpoint( uint32_t pc )
120 {
121 int i;
122 for( i=0; i<sh4_breakpoint_count; i++ ) {
123 if( sh4_breakpoints[i].address == pc )
124 return sh4_breakpoints[i].type;
125 }
126 return 0;
127 }
129 uint32_t sh4_run_slice( uint32_t nanosecs )
130 {
131 int target = sh4r.icount + nanosecs / sh4_cpu_period;
132 int start = sh4r.icount;
133 int i;
135 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
136 if( sh4r.int_pending != 0 )
137 sh4r.sh4_state = SH4_STATE_RUNNING;;
138 }
140 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
141 if( !sh4_execute_instruction() )
142 break;
143 #ifdef ENABLE_DEBUG_MODE
144 for( i=0; i<sh4_breakpoint_count; i++ ) {
145 if( sh4_breakpoints[i].address == sh4r.pc ) {
146 break;
147 }
148 }
149 if( i != sh4_breakpoint_count ) {
150 dreamcast_stop();
151 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
152 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
153 break;
154 }
155 #endif
156 }
158 /* If we aborted early, but the cpu is still technically running,
159 * we're doing a hard abort - cut the timeslice back to what we
160 * actually executed
161 */
162 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
163 nanosecs = sh4r.slice_cycle;
164 }
165 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
166 TMU_run_slice( nanosecs );
167 SCIF_run_slice( nanosecs );
168 }
169 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
170 return nanosecs;
171 }
173 void sh4_stop(void)
174 {
176 }
178 void sh4_save_state( FILE *f )
179 {
180 fwrite( &sh4r, sizeof(sh4r), 1, f );
181 TMU_save_state( f );
182 SCIF_save_state( f );
183 }
185 int sh4_load_state( FILE * f )
186 {
187 fread( &sh4r, sizeof(sh4r), 1, f );
188 TMU_load_state( f );
189 return SCIF_load_state( f );
190 }
192 /********************** SH4 emulation core ****************************/
194 void sh4_set_pc( int pc )
195 {
196 sh4r.pc = pc;
197 sh4r.new_pc = pc+2;
198 }
200 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
201 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
203 #define RAISE( x, v ) do{ \
204 if( sh4r.vbr == 0 ) { \
205 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
206 dreamcast_stop(); return FALSE; \
207 } else { \
208 sh4r.spc = sh4r.pc + 2; \
209 sh4r.ssr = sh4_read_sr(); \
210 sh4r.sgr = sh4r.r[15]; \
211 MMIO_WRITE(MMU,EXPEVT,x); \
212 sh4r.pc = sh4r.vbr + v; \
213 sh4r.new_pc = sh4r.pc + 2; \
214 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
215 } \
216 return TRUE; } while(0)
218 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
219 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
220 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
221 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
222 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
223 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
225 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
227 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
229 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
231 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
232 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
233 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
234 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
235 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
237 static void sh4_switch_banks( )
238 {
239 uint32_t tmp[8];
241 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
242 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
243 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
244 }
246 static void sh4_load_sr( uint32_t newval )
247 {
248 if( (newval ^ sh4r.sr) & SR_RB )
249 sh4_switch_banks();
250 sh4r.sr = newval;
251 sh4r.t = (newval&SR_T) ? 1 : 0;
252 sh4r.s = (newval&SR_S) ? 1 : 0;
253 sh4r.m = (newval&SR_M) ? 1 : 0;
254 sh4r.q = (newval&SR_Q) ? 1 : 0;
255 intc_mask_changed();
256 }
258 static void sh4_write_float( uint32_t addr, int reg )
259 {
260 if( IS_FPU_DOUBLESIZE() ) {
261 if( reg & 1 ) {
262 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
263 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
264 } else {
265 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
266 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
267 }
268 } else {
269 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
270 }
271 }
273 static void sh4_read_float( uint32_t addr, int reg )
274 {
275 if( IS_FPU_DOUBLESIZE() ) {
276 if( reg & 1 ) {
277 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
278 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
279 } else {
280 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
281 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
282 }
283 } else {
284 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
285 }
286 }
288 static uint32_t sh4_read_sr( void )
289 {
290 /* synchronize sh4r.sr with the various bitflags */
291 sh4r.sr &= SR_MQSTMASK;
292 if( sh4r.t ) sh4r.sr |= SR_T;
293 if( sh4r.s ) sh4r.sr |= SR_S;
294 if( sh4r.m ) sh4r.sr |= SR_M;
295 if( sh4r.q ) sh4r.sr |= SR_Q;
296 return sh4r.sr;
297 }
298 /* function for external use */
299 void sh4_raise_exception( int code, int vector )
300 {
301 RAISE(code, vector);
302 }
304 static void sh4_accept_interrupt( void )
305 {
306 uint32_t code = intc_accept_interrupt();
307 sh4r.ssr = sh4_read_sr();
308 sh4r.spc = sh4r.pc;
309 sh4r.sgr = sh4r.r[15];
310 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
311 MMIO_WRITE( MMU, INTEVT, code );
312 sh4r.pc = sh4r.vbr + 0x600;
313 sh4r.new_pc = sh4r.pc + 2;
314 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
315 }
317 gboolean sh4_execute_instruction( void )
318 {
319 uint32_t pc;
320 unsigned short ir;
321 uint32_t tmp;
322 uint64_t tmpl;
323 float ftmp;
324 double dtmp;
326 #define R0 sh4r.r[0]
327 #define FR0 FR(0)
328 #define DR0 DR(0)
329 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
330 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
331 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
332 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
333 #define DISP8(ir) (ir&0x00FF)
334 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
335 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
336 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
337 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
338 #define FRNn(ir) ((ir&0x0F00)>>8)
339 #define FRMn(ir) ((ir&0x00F0)>>4)
340 #define DRNn(ir) ((ir&0x0E00)>>9)
341 #define DRMn(ir) ((ir&0x00E0)>>5)
342 #define FVN(ir) ((ir&0x0C00)>>8)
343 #define FVM(ir) ((ir&0x0300)>>6)
344 #define FRN(ir) FR(FRNn(ir))
345 #define FRM(ir) FR(FRMn(ir))
346 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
347 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
348 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
349 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
350 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
351 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
352 #define FPULf *((float *)&sh4r.fpul)
353 #define FPULi (sh4r.fpul)
355 if( SH4_INT_PENDING() )
356 sh4_accept_interrupt();
358 pc = sh4r.pc;
359 if( pc > 0xFFFFFF00 ) {
360 /* SYSCALL Magic */
361 syscall_invoke( pc );
362 sh4r.in_delay_slot = 0;
363 pc = sh4r.pc = sh4r.pr;
364 sh4r.new_pc = sh4r.pc + 2;
365 }
366 ir = MEM_READ_WORD(pc);
367 sh4r.icount++;
369 switch( (ir&0xF000)>>12 ) {
370 case 0: /* 0000nnnnmmmmxxxx */
371 switch( ir&0x000F ) {
372 case 2:
373 switch( (ir&0x00F0)>>4 ) {
374 case 0: /* STC SR, Rn */
375 CHECKPRIV();
376 RN(ir) = sh4_read_sr();
377 break;
378 case 1: /* STC GBR, Rn */
379 RN(ir) = sh4r.gbr;
380 break;
381 case 2: /* STC VBR, Rn */
382 CHECKPRIV();
383 RN(ir) = sh4r.vbr;
384 break;
385 case 3: /* STC SSR, Rn */
386 CHECKPRIV();
387 RN(ir) = sh4r.ssr;
388 break;
389 case 4: /* STC SPC, Rn */
390 CHECKPRIV();
391 RN(ir) = sh4r.spc;
392 break;
393 case 8: case 9: case 10: case 11: case 12: case 13:
394 case 14: case 15:/* STC Rm_bank, Rn */
395 CHECKPRIV();
396 RN(ir) = RN_BANK(ir);
397 break;
398 default: UNDEF(ir);
399 }
400 break;
401 case 3:
402 switch( (ir&0x00F0)>>4 ) {
403 case 0: /* BSRF Rn */
404 CHECKDEST( pc + 4 + RN(ir) );
405 CHECKSLOTILLEGAL();
406 sh4r.in_delay_slot = 1;
407 sh4r.pr = sh4r.pc + 4;
408 sh4r.pc = sh4r.new_pc;
409 sh4r.new_pc = pc + 4 + RN(ir);
410 return TRUE;
411 case 2: /* BRAF Rn */
412 CHECKDEST( pc + 4 + RN(ir) );
413 CHECKSLOTILLEGAL();
414 sh4r.in_delay_slot = 1;
415 sh4r.pc = sh4r.new_pc;
416 sh4r.new_pc = pc + 4 + RN(ir);
417 return TRUE;
418 case 8: /* PREF [Rn] */
419 tmp = RN(ir);
420 if( (tmp & 0xFC000000) == 0xE0000000 ) {
421 /* Store queue operation */
422 int queue = (tmp&0x20)>>2;
423 int32_t *src = &sh4r.store_queue[queue];
424 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
425 uint32_t target = tmp&0x03FFFFE0 | hi;
426 mem_copy_to_sh4( target, src, 32 );
427 //if( (target &0xFF000000) != 0x04000000 )
428 // WARN( "Executed SQ%c => %08X",
429 // (queue == 0 ? '0' : '1'), target );
430 }
431 break;
432 case 9: /* OCBI [Rn] */
433 case 10:/* OCBP [Rn] */
434 case 11:/* OCBWB [Rn] */
435 /* anything? */
436 break;
437 case 12:/* MOVCA.L R0, [Rn] */
438 UNIMP(ir);
439 default: UNDEF(ir);
440 }
441 break;
442 case 4: /* MOV.B Rm, [R0 + Rn] */
443 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
444 break;
445 case 5: /* MOV.W Rm, [R0 + Rn] */
446 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
447 break;
448 case 6: /* MOV.L Rm, [R0 + Rn] */
449 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
450 break;
451 case 7: /* MUL.L Rm, Rn */
452 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
453 (RM(ir) * RN(ir));
454 break;
455 case 8:
456 switch( (ir&0x0FF0)>>4 ) {
457 case 0: /* CLRT */
458 sh4r.t = 0;
459 break;
460 case 1: /* SETT */
461 sh4r.t = 1;
462 break;
463 case 2: /* CLRMAC */
464 sh4r.mac = 0;
465 break;
466 case 3: /* LDTLB */
467 break;
468 case 4: /* CLRS */
469 sh4r.s = 0;
470 break;
471 case 5: /* SETS */
472 sh4r.s = 1;
473 break;
474 default: UNDEF(ir);
475 }
476 break;
477 case 9:
478 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
479 RN(ir) = sh4r.t;
480 else if( ir == 0x0019 ) /* DIV0U */
481 sh4r.m = sh4r.q = sh4r.t = 0;
482 else if( ir == 0x0009 )
483 /* NOP */;
484 else UNDEF(ir);
485 break;
486 case 10:
487 switch( (ir&0x00F0) >> 4 ) {
488 case 0: /* STS MACH, Rn */
489 RN(ir) = sh4r.mac >> 32;
490 break;
491 case 1: /* STS MACL, Rn */
492 RN(ir) = (uint32_t)sh4r.mac;
493 break;
494 case 2: /* STS PR, Rn */
495 RN(ir) = sh4r.pr;
496 break;
497 case 3: /* STC SGR, Rn */
498 CHECKPRIV();
499 RN(ir) = sh4r.sgr;
500 break;
501 case 5:/* STS FPUL, Rn */
502 RN(ir) = sh4r.fpul;
503 break;
504 case 6: /* STS FPSCR, Rn */
505 RN(ir) = sh4r.fpscr;
506 break;
507 case 15:/* STC DBR, Rn */
508 CHECKPRIV();
509 RN(ir) = sh4r.dbr;
510 break;
511 default: UNDEF(ir);
512 }
513 break;
514 case 11:
515 switch( (ir&0x0FF0)>>4 ) {
516 case 0: /* RTS */
517 CHECKDEST( sh4r.pr );
518 CHECKSLOTILLEGAL();
519 sh4r.in_delay_slot = 1;
520 sh4r.pc = sh4r.new_pc;
521 sh4r.new_pc = sh4r.pr;
522 return TRUE;
523 case 1: /* SLEEP */
524 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
525 sh4r.sh4_state = SH4_STATE_STANDBY;
526 } else {
527 sh4r.sh4_state = SH4_STATE_SLEEP;
528 }
529 return FALSE; /* Halt CPU */
530 case 2: /* RTE */
531 CHECKPRIV();
532 CHECKDEST( sh4r.spc );
533 CHECKSLOTILLEGAL();
534 sh4r.in_delay_slot = 1;
535 sh4r.pc = sh4r.new_pc;
536 sh4r.new_pc = sh4r.spc;
537 sh4_load_sr( sh4r.ssr );
538 return TRUE;
539 default:UNDEF(ir);
540 }
541 break;
542 case 12:/* MOV.B [R0+R%d], R%d */
543 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
544 break;
545 case 13:/* MOV.W [R0+R%d], R%d */
546 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
547 break;
548 case 14:/* MOV.L [R0+R%d], R%d */
549 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
550 break;
551 case 15:/* MAC.L [Rm++], [Rn++] */
552 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
553 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
554 if( sh4r.s ) {
555 /* 48-bit Saturation. Yuch */
556 tmpl += SIGNEXT48(sh4r.mac);
557 if( tmpl < 0xFFFF800000000000LL )
558 tmpl = 0xFFFF800000000000LL;
559 else if( tmpl > 0x00007FFFFFFFFFFFLL )
560 tmpl = 0x00007FFFFFFFFFFFLL;
561 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
562 (tmpl&0x0000FFFFFFFFFFFFLL);
563 } else sh4r.mac = tmpl;
565 RM(ir) += 4;
566 RN(ir) += 4;
568 break;
569 default: UNDEF(ir);
570 }
571 break;
572 case 1: /* 0001nnnnmmmmdddd */
573 /* MOV.L Rm, [Rn + disp4*4] */
574 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
575 break;
576 case 2: /* 0010nnnnmmmmxxxx */
577 switch( ir&0x000F ) {
578 case 0: /* MOV.B Rm, [Rn] */
579 MEM_WRITE_BYTE( RN(ir), RM(ir) );
580 break;
581 case 1: /* MOV.W Rm, [Rn] */
582 MEM_WRITE_WORD( RN(ir), RM(ir) );
583 break;
584 case 2: /* MOV.L Rm, [Rn] */
585 MEM_WRITE_LONG( RN(ir), RM(ir) );
586 break;
587 case 3: UNDEF(ir);
588 break;
589 case 4: /* MOV.B Rm, [--Rn] */
590 RN(ir) --;
591 MEM_WRITE_BYTE( RN(ir), RM(ir) );
592 break;
593 case 5: /* MOV.W Rm, [--Rn] */
594 RN(ir) -= 2;
595 MEM_WRITE_WORD( RN(ir), RM(ir) );
596 break;
597 case 6: /* MOV.L Rm, [--Rn] */
598 RN(ir) -= 4;
599 MEM_WRITE_LONG( RN(ir), RM(ir) );
600 break;
601 case 7: /* DIV0S Rm, Rn */
602 sh4r.q = RN(ir)>>31;
603 sh4r.m = RM(ir)>>31;
604 sh4r.t = sh4r.q ^ sh4r.m;
605 break;
606 case 8: /* TST Rm, Rn */
607 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
608 break;
609 case 9: /* AND Rm, Rn */
610 RN(ir) &= RM(ir);
611 break;
612 case 10:/* XOR Rm, Rn */
613 RN(ir) ^= RM(ir);
614 break;
615 case 11:/* OR Rm, Rn */
616 RN(ir) |= RM(ir);
617 break;
618 case 12:/* CMP/STR Rm, Rn */
619 /* set T = 1 if any byte in RM & RN is the same */
620 tmp = RM(ir) ^ RN(ir);
621 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
622 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
623 break;
624 case 13:/* XTRCT Rm, Rn */
625 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
626 break;
627 case 14:/* MULU.W Rm, Rn */
628 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
629 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
630 break;
631 case 15:/* MULS.W Rm, Rn */
632 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
633 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
634 break;
635 }
636 break;
637 case 3: /* 0011nnnnmmmmxxxx */
638 switch( ir&0x000F ) {
639 case 0: /* CMP/EQ Rm, Rn */
640 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
641 break;
642 case 2: /* CMP/HS Rm, Rn */
643 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
644 break;
645 case 3: /* CMP/GE Rm, Rn */
646 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
647 break;
648 case 4: { /* DIV1 Rm, Rn */
649 /* This is just from the sh4p manual with some
650 * simplifications (someone want to check it's correct? :)
651 * Why they couldn't just provide a real DIV instruction...
652 * Please oh please let the translator batch these things
653 * up into a single DIV... */
654 uint32_t tmp0, tmp1, tmp2, dir;
656 dir = sh4r.q ^ sh4r.m;
657 sh4r.q = (RN(ir) >> 31);
658 tmp2 = RM(ir);
659 RN(ir) = (RN(ir) << 1) | sh4r.t;
660 tmp0 = RN(ir);
661 if( dir ) {
662 RN(ir) += tmp2;
663 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
664 } else {
665 RN(ir) -= tmp2;
666 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
667 }
668 sh4r.q ^= sh4r.m ^ tmp1;
669 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
670 break; }
671 case 5: /* DMULU.L Rm, Rn */
672 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
673 break;
674 case 6: /* CMP/HI Rm, Rn */
675 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
676 break;
677 case 7: /* CMP/GT Rm, Rn */
678 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
679 break;
680 case 8: /* SUB Rm, Rn */
681 RN(ir) -= RM(ir);
682 break;
683 case 10:/* SUBC Rm, Rn */
684 tmp = RN(ir);
685 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
686 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
687 break;
688 case 11:/* SUBV Rm, Rn */
689 UNIMP(ir);
690 break;
691 case 12:/* ADD Rm, Rn */
692 RN(ir) += RM(ir);
693 break;
694 case 13:/* DMULS.L Rm, Rn */
695 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
696 break;
697 case 14:/* ADDC Rm, Rn */
698 tmp = RN(ir);
699 RN(ir) += RM(ir) + sh4r.t;
700 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
701 break;
702 case 15:/* ADDV Rm, Rn */
703 UNIMP(ir);
704 break;
705 default: UNDEF(ir);
706 }
707 break;
708 case 4: /* 0100nnnnxxxxxxxx */
709 switch( ir&0x00FF ) {
710 case 0x00: /* SHLL Rn */
711 sh4r.t = RN(ir) >> 31;
712 RN(ir) <<= 1;
713 break;
714 case 0x01: /* SHLR Rn */
715 sh4r.t = RN(ir) & 0x00000001;
716 RN(ir) >>= 1;
717 break;
718 case 0x02: /* STS.L MACH, [--Rn] */
719 RN(ir) -= 4;
720 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
721 break;
722 case 0x03: /* STC.L SR, [--Rn] */
723 CHECKPRIV();
724 RN(ir) -= 4;
725 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
726 break;
727 case 0x04: /* ROTL Rn */
728 sh4r.t = RN(ir) >> 31;
729 RN(ir) <<= 1;
730 RN(ir) |= sh4r.t;
731 break;
732 case 0x05: /* ROTR Rn */
733 sh4r.t = RN(ir) & 0x00000001;
734 RN(ir) >>= 1;
735 RN(ir) |= (sh4r.t << 31);
736 break;
737 case 0x06: /* LDS.L [Rn++], MACH */
738 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
739 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
740 RN(ir) += 4;
741 break;
742 case 0x07: /* LDC.L [Rn++], SR */
743 CHECKPRIV();
744 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
745 RN(ir) +=4;
746 break;
747 case 0x08: /* SHLL2 Rn */
748 RN(ir) <<= 2;
749 break;
750 case 0x09: /* SHLR2 Rn */
751 RN(ir) >>= 2;
752 break;
753 case 0x0A: /* LDS Rn, MACH */
754 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
755 (((uint64_t)RN(ir))<<32);
756 break;
757 case 0x0B: /* JSR [Rn] */
758 CHECKDEST( RN(ir) );
759 CHECKSLOTILLEGAL();
760 sh4r.in_delay_slot = 1;
761 sh4r.pc = sh4r.new_pc;
762 sh4r.new_pc = RN(ir);
763 sh4r.pr = pc + 4;
764 return TRUE;
765 case 0x0E: /* LDC Rn, SR */
766 CHECKPRIV();
767 sh4_load_sr( RN(ir) );
768 break;
769 case 0x10: /* DT Rn */
770 RN(ir) --;
771 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
772 break;
773 case 0x11: /* CMP/PZ Rn */
774 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
775 break;
776 case 0x12: /* STS.L MACL, [--Rn] */
777 RN(ir) -= 4;
778 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
779 break;
780 case 0x13: /* STC.L GBR, [--Rn] */
781 RN(ir) -= 4;
782 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
783 break;
784 case 0x15: /* CMP/PL Rn */
785 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
786 break;
787 case 0x16: /* LDS.L [Rn++], MACL */
788 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
789 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
790 RN(ir) += 4;
791 break;
792 case 0x17: /* LDC.L [Rn++], GBR */
793 sh4r.gbr = MEM_READ_LONG(RN(ir));
794 RN(ir) +=4;
795 break;
796 case 0x18: /* SHLL8 Rn */
797 RN(ir) <<= 8;
798 break;
799 case 0x19: /* SHLR8 Rn */
800 RN(ir) >>= 8;
801 break;
802 case 0x1A: /* LDS Rn, MACL */
803 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
804 (uint64_t)((uint32_t)(RN(ir)));
805 break;
806 case 0x1B: /* TAS.B [Rn] */
807 tmp = MEM_READ_BYTE( RN(ir) );
808 sh4r.t = ( tmp == 0 ? 1 : 0 );
809 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
810 break;
811 case 0x1E: /* LDC Rn, GBR */
812 sh4r.gbr = RN(ir);
813 break;
814 case 0x20: /* SHAL Rn */
815 sh4r.t = RN(ir) >> 31;
816 RN(ir) <<= 1;
817 break;
818 case 0x21: /* SHAR Rn */
819 sh4r.t = RN(ir) & 0x00000001;
820 RN(ir) = ((int32_t)RN(ir)) >> 1;
821 break;
822 case 0x22: /* STS.L PR, [--Rn] */
823 RN(ir) -= 4;
824 MEM_WRITE_LONG( RN(ir), sh4r.pr );
825 break;
826 case 0x23: /* STC.L VBR, [--Rn] */
827 CHECKPRIV();
828 RN(ir) -= 4;
829 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
830 break;
831 case 0x24: /* ROTCL Rn */
832 tmp = RN(ir) >> 31;
833 RN(ir) <<= 1;
834 RN(ir) |= sh4r.t;
835 sh4r.t = tmp;
836 break;
837 case 0x25: /* ROTCR Rn */
838 tmp = RN(ir) & 0x00000001;
839 RN(ir) >>= 1;
840 RN(ir) |= (sh4r.t << 31 );
841 sh4r.t = tmp;
842 break;
843 case 0x26: /* LDS.L [Rn++], PR */
844 sh4r.pr = MEM_READ_LONG( RN(ir) );
845 RN(ir) += 4;
846 break;
847 case 0x27: /* LDC.L [Rn++], VBR */
848 CHECKPRIV();
849 sh4r.vbr = MEM_READ_LONG(RN(ir));
850 RN(ir) +=4;
851 break;
852 case 0x28: /* SHLL16 Rn */
853 RN(ir) <<= 16;
854 break;
855 case 0x29: /* SHLR16 Rn */
856 RN(ir) >>= 16;
857 break;
858 case 0x2A: /* LDS Rn, PR */
859 sh4r.pr = RN(ir);
860 break;
861 case 0x2B: /* JMP [Rn] */
862 CHECKDEST( RN(ir) );
863 CHECKSLOTILLEGAL();
864 sh4r.in_delay_slot = 1;
865 sh4r.pc = sh4r.new_pc;
866 sh4r.new_pc = RN(ir);
867 return TRUE;
868 case 0x2E: /* LDC Rn, VBR */
869 CHECKPRIV();
870 sh4r.vbr = RN(ir);
871 break;
872 case 0x32: /* STC.L SGR, [--Rn] */
873 CHECKPRIV();
874 RN(ir) -= 4;
875 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
876 break;
877 case 0x33: /* STC.L SSR, [--Rn] */
878 CHECKPRIV();
879 RN(ir) -= 4;
880 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
881 break;
882 case 0x37: /* LDC.L [Rn++], SSR */
883 CHECKPRIV();
884 sh4r.ssr = MEM_READ_LONG(RN(ir));
885 RN(ir) +=4;
886 break;
887 case 0x3E: /* LDC Rn, SSR */
888 CHECKPRIV();
889 sh4r.ssr = RN(ir);
890 break;
891 case 0x43: /* STC.L SPC, [--Rn] */
892 CHECKPRIV();
893 RN(ir) -= 4;
894 MEM_WRITE_LONG( RN(ir), sh4r.spc );
895 break;
896 case 0x47: /* LDC.L [Rn++], SPC */
897 CHECKPRIV();
898 sh4r.spc = MEM_READ_LONG(RN(ir));
899 RN(ir) +=4;
900 break;
901 case 0x4E: /* LDC Rn, SPC */
902 CHECKPRIV();
903 sh4r.spc = RN(ir);
904 break;
905 case 0x52: /* STS.L FPUL, [--Rn] */
906 RN(ir) -= 4;
907 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
908 break;
909 case 0x56: /* LDS.L [Rn++], FPUL */
910 sh4r.fpul = MEM_READ_LONG(RN(ir));
911 RN(ir) +=4;
912 break;
913 case 0x5A: /* LDS Rn, FPUL */
914 sh4r.fpul = RN(ir);
915 break;
916 case 0x62: /* STS.L FPSCR, [--Rn] */
917 RN(ir) -= 4;
918 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
919 break;
920 case 0x66: /* LDS.L [Rn++], FPSCR */
921 sh4r.fpscr = MEM_READ_LONG(RN(ir));
922 RN(ir) +=4;
923 break;
924 case 0x6A: /* LDS Rn, FPSCR */
925 sh4r.fpscr = RN(ir);
926 break;
927 case 0xF2: /* STC.L DBR, [--Rn] */
928 CHECKPRIV();
929 RN(ir) -= 4;
930 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
931 break;
932 case 0xF6: /* LDC.L [Rn++], DBR */
933 CHECKPRIV();
934 sh4r.dbr = MEM_READ_LONG(RN(ir));
935 RN(ir) +=4;
936 break;
937 case 0xFA: /* LDC Rn, DBR */
938 CHECKPRIV();
939 sh4r.dbr = RN(ir);
940 break;
941 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
942 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
943 CHECKPRIV();
944 RN(ir) -= 4;
945 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
946 break;
947 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
948 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
949 CHECKPRIV();
950 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
951 RN(ir) += 4;
952 break;
953 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
954 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
955 CHECKPRIV();
956 RN_BANK(ir) = RM(ir);
957 break;
958 default:
959 if( (ir&0x000F) == 0x0F ) {
960 /* MAC.W [Rm++], [Rn++] */
961 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
962 SIGNEXT16(MEM_READ_WORD(RN(ir)));
963 if( sh4r.s ) {
964 /* FIXME */
965 UNIMP(ir);
966 } else sh4r.mac += SIGNEXT32(tmp);
967 RM(ir) += 2;
968 RN(ir) += 2;
969 } else if( (ir&0x000F) == 0x0C ) {
970 /* SHAD Rm, Rn */
971 tmp = RM(ir);
972 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
973 else if( (tmp & 0x1F) == 0 )
974 RN(ir) = ((int32_t)RN(ir)) >> 31;
975 else
976 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
977 } else if( (ir&0x000F) == 0x0D ) {
978 /* SHLD Rm, Rn */
979 tmp = RM(ir);
980 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
981 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
982 else RN(ir) >>= (((~tmp) & 0x1F)+1);
983 } else UNDEF(ir);
984 }
985 break;
986 case 5: /* 0101nnnnmmmmdddd */
987 /* MOV.L [Rm + disp4*4], Rn */
988 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
989 break;
990 case 6: /* 0110xxxxxxxxxxxx */
991 switch( ir&0x000f ) {
992 case 0: /* MOV.B [Rm], Rn */
993 RN(ir) = MEM_READ_BYTE( RM(ir) );
994 break;
995 case 1: /* MOV.W [Rm], Rn */
996 RN(ir) = MEM_READ_WORD( RM(ir) );
997 break;
998 case 2: /* MOV.L [Rm], Rn */
999 RN(ir) = MEM_READ_LONG( RM(ir) );
1000 break;
1001 case 3: /* MOV Rm, Rn */
1002 RN(ir) = RM(ir);
1003 break;
1004 case 4: /* MOV.B [Rm++], Rn */
1005 RN(ir) = MEM_READ_BYTE( RM(ir) );
1006 RM(ir) ++;
1007 break;
1008 case 5: /* MOV.W [Rm++], Rn */
1009 RN(ir) = MEM_READ_WORD( RM(ir) );
1010 RM(ir) += 2;
1011 break;
1012 case 6: /* MOV.L [Rm++], Rn */
1013 RN(ir) = MEM_READ_LONG( RM(ir) );
1014 RM(ir) += 4;
1015 break;
1016 case 7: /* NOT Rm, Rn */
1017 RN(ir) = ~RM(ir);
1018 break;
1019 case 8: /* SWAP.B Rm, Rn */
1020 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1021 ((RM(ir)&0x000000FF)<<8);
1022 break;
1023 case 9: /* SWAP.W Rm, Rn */
1024 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1025 break;
1026 case 10:/* NEGC Rm, Rn */
1027 tmp = 0 - RM(ir);
1028 RN(ir) = tmp - sh4r.t;
1029 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1030 break;
1031 case 11:/* NEG Rm, Rn */
1032 RN(ir) = 0 - RM(ir);
1033 break;
1034 case 12:/* EXTU.B Rm, Rn */
1035 RN(ir) = RM(ir)&0x000000FF;
1036 break;
1037 case 13:/* EXTU.W Rm, Rn */
1038 RN(ir) = RM(ir)&0x0000FFFF;
1039 break;
1040 case 14:/* EXTS.B Rm, Rn */
1041 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1042 break;
1043 case 15:/* EXTS.W Rm, Rn */
1044 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1045 break;
1046 }
1047 break;
1048 case 7: /* 0111nnnniiiiiiii */
1049 /* ADD imm8, Rn */
1050 RN(ir) += IMM8(ir);
1051 break;
1052 case 8: /* 1000xxxxxxxxxxxx */
1053 switch( (ir&0x0F00) >> 8 ) {
1054 case 0: /* MOV.B R0, [Rm + disp4] */
1055 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1056 break;
1057 case 1: /* MOV.W R0, [Rm + disp4*2] */
1058 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
1059 break;
1060 case 4: /* MOV.B [Rm + disp4], R0 */
1061 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1062 break;
1063 case 5: /* MOV.W [Rm + disp4*2], R0 */
1064 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
1065 break;
1066 case 8: /* CMP/EQ imm, R0 */
1067 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1068 break;
1069 case 9: /* BT disp8 */
1070 CHECKSLOTILLEGAL()
1071 if( sh4r.t ) {
1072 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1073 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1074 sh4r.new_pc = sh4r.pc + 2;
1075 return TRUE;
1076 }
1077 break;
1078 case 11:/* BF disp8 */
1079 CHECKSLOTILLEGAL()
1080 if( !sh4r.t ) {
1081 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1082 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1083 sh4r.new_pc = sh4r.pc + 2;
1084 return TRUE;
1085 }
1086 break;
1087 case 13:/* BT/S disp8 */
1088 CHECKSLOTILLEGAL()
1089 if( sh4r.t ) {
1090 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1091 sh4r.in_delay_slot = 1;
1092 sh4r.pc = sh4r.new_pc;
1093 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1094 sh4r.in_delay_slot = 1;
1095 return TRUE;
1096 }
1097 break;
1098 case 15:/* BF/S disp8 */
1099 CHECKSLOTILLEGAL()
1100 if( !sh4r.t ) {
1101 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1102 sh4r.in_delay_slot = 1;
1103 sh4r.pc = sh4r.new_pc;
1104 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1105 return TRUE;
1106 }
1107 break;
1108 default: UNDEF(ir);
1109 }
1110 break;
1111 case 9: /* 1001xxxxxxxxxxxx */
1112 /* MOV.W [disp8*2 + pc + 4], Rn */
1113 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
1114 break;
1115 case 10:/* 1010dddddddddddd */
1116 /* BRA disp12 */
1117 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1118 CHECKSLOTILLEGAL()
1119 sh4r.in_delay_slot = 1;
1120 sh4r.pc = sh4r.new_pc;
1121 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1122 return TRUE;
1123 case 11:/* 1011dddddddddddd */
1124 /* BSR disp12 */
1125 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1126 CHECKSLOTILLEGAL()
1127 sh4r.in_delay_slot = 1;
1128 sh4r.pr = pc + 4;
1129 sh4r.pc = sh4r.new_pc;
1130 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1131 return TRUE;
1132 case 12:/* 1100xxxxdddddddd */
1133 switch( (ir&0x0F00)>>8 ) {
1134 case 0: /* MOV.B R0, [GBR + disp8] */
1135 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1136 break;
1137 case 1: /* MOV.W R0, [GBR + disp8*2] */
1138 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1139 break;
1140 case 2: /*MOV.L R0, [GBR + disp8*4] */
1141 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1142 break;
1143 case 3: /* TRAPA imm8 */
1144 CHECKSLOTILLEGAL()
1145 sh4r.in_delay_slot = 1;
1146 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1147 RAISE( EXC_TRAP, EXV_TRAP );
1148 break;
1149 case 4: /* MOV.B [GBR + disp8], R0 */
1150 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1151 break;
1152 case 5: /* MOV.W [GBR + disp8*2], R0 */
1153 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1154 break;
1155 case 6: /* MOV.L [GBR + disp8*4], R0 */
1156 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1157 break;
1158 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1159 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1160 break;
1161 case 8: /* TST imm8, R0 */
1162 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1163 break;
1164 case 9: /* AND imm8, R0 */
1165 R0 &= UIMM8(ir);
1166 break;
1167 case 10:/* XOR imm8, R0 */
1168 R0 ^= UIMM8(ir);
1169 break;
1170 case 11:/* OR imm8, R0 */
1171 R0 |= UIMM8(ir);
1172 break;
1173 case 12:/* TST.B imm8, [R0+GBR] */
1174 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1175 break;
1176 case 13:/* AND.B imm8, [R0+GBR] */
1177 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1178 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1179 break;
1180 case 14:/* XOR.B imm8, [R0+GBR] */
1181 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1182 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1183 break;
1184 case 15:/* OR.B imm8, [R0+GBR] */
1185 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1186 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1187 break;
1188 }
1189 break;
1190 case 13:/* 1101nnnndddddddd */
1191 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1192 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1193 break;
1194 case 14:/* 1110nnnniiiiiiii */
1195 /* MOV imm8, Rn */
1196 RN(ir) = IMM8(ir);
1197 break;
1198 case 15:/* 1111xxxxxxxxxxxx */
1199 CHECKFPUEN();
1200 if( IS_FPU_DOUBLEPREC() ) {
1201 switch( ir&0x000F ) {
1202 case 0: /* FADD FRm, FRn */
1203 DRN(ir) += DRM(ir);
1204 break;
1205 case 1: /* FSUB FRm, FRn */
1206 DRN(ir) -= DRM(ir);
1207 break;
1208 case 2: /* FMUL FRm, FRn */
1209 DRN(ir) = DRN(ir) * DRM(ir);
1210 break;
1211 case 3: /* FDIV FRm, FRn */
1212 DRN(ir) = DRN(ir) / DRM(ir);
1213 break;
1214 case 4: /* FCMP/EQ FRm, FRn */
1215 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1216 break;
1217 case 5: /* FCMP/GT FRm, FRn */
1218 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1219 break;
1220 case 6: /* FMOV.S [Rm+R0], FRn */
1221 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1222 break;
1223 case 7: /* FMOV.S FRm, [Rn+R0] */
1224 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1225 break;
1226 case 8: /* FMOV.S [Rm], FRn */
1227 MEM_FP_READ( RM(ir), FRNn(ir) );
1228 break;
1229 case 9: /* FMOV.S [Rm++], FRn */
1230 MEM_FP_READ( RM(ir), FRNn(ir) );
1231 RM(ir) += FP_WIDTH;
1232 break;
1233 case 10:/* FMOV.S FRm, [Rn] */
1234 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1235 break;
1236 case 11:/* FMOV.S FRm, [--Rn] */
1237 RN(ir) -= FP_WIDTH;
1238 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1239 break;
1240 case 12:/* FMOV FRm, FRn */
1241 if( IS_FPU_DOUBLESIZE() )
1242 DRN(ir) = DRM(ir);
1243 else
1244 FRN(ir) = FRM(ir);
1245 break;
1246 case 13:
1247 switch( (ir&0x00F0) >> 4 ) {
1248 case 0: /* FSTS FPUL, FRn */
1249 FRN(ir) = FPULf;
1250 break;
1251 case 1: /* FLDS FRn,FPUL */
1252 FPULf = FRN(ir);
1253 break;
1254 case 2: /* FLOAT FPUL, FRn */
1255 DRN(ir) = (float)FPULi;
1256 break;
1257 case 3: /* FTRC FRn, FPUL */
1258 dtmp = DRN(ir);
1259 if( dtmp >= MAX_INTF )
1260 FPULi = MAX_INT;
1261 else if( dtmp <= MIN_INTF )
1262 FPULi = MIN_INT;
1263 else
1264 FPULi = (int32_t)dtmp;
1265 break;
1266 case 4: /* FNEG FRn */
1267 DRN(ir) = -DRN(ir);
1268 break;
1269 case 5: /* FABS FRn */
1270 DRN(ir) = fabs(DRN(ir));
1271 break;
1272 case 6: /* FSQRT FRn */
1273 DRN(ir) = sqrt(DRN(ir));
1274 break;
1275 case 7: /* FSRRA FRn */
1276 DRN(ir) = 1.0/sqrt(DRN(ir));
1277 break;
1278 case 8: /* FLDI0 FRn */
1279 DRN(ir) = 0.0;
1280 break;
1281 case 9: /* FLDI1 FRn */
1282 DRN(ir) = 1.0;
1283 break;
1284 case 10: /* FCNVSD FPUL, DRn */
1285 DRN(ir) = (double)FPULf;
1286 break;
1287 case 11: /* FCNVDS DRn, FPUL */
1288 FPULf = (float)DRN(ir);
1289 break;
1290 case 14:/* FIPR FVm, FVn */
1291 UNDEF(ir);
1292 break;
1293 case 15:
1294 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1295 break;
1296 }
1297 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1298 float angle = (((float)(short)(FPULi>>16)) +
1299 ((float)(FPULi&16)/65536.0)) *
1300 2 * M_PI;
1301 int reg = DRNn(ir);
1302 DR(reg) = sinf(angle);
1303 DR(reg+1) = cosf(angle);
1304 break;
1305 }
1306 else if( ir == 0xFBFD ) {
1307 /* FRCHG */
1308 sh4r.fpscr ^= FPSCR_FR;
1309 break;
1310 }
1311 else if( ir == 0xF3FD ) {
1312 /* FSCHG */
1313 sh4r.fpscr ^= FPSCR_SZ;
1314 break;
1315 }
1316 default: UNDEF(ir);
1317 }
1318 break;
1319 case 14:/* FMAC FR0, FRm, FRn */
1320 DRN(ir) += DRM(ir)*DR0;
1321 break;
1322 default: UNDEF(ir);
1323 }
1324 } else { /* Single precision */
1325 switch( ir&0x000F ) {
1326 case 0: /* FADD FRm, FRn */
1327 FRN(ir) += FRM(ir);
1328 break;
1329 case 1: /* FSUB FRm, FRn */
1330 FRN(ir) -= FRM(ir);
1331 break;
1332 case 2: /* FMUL FRm, FRn */
1333 FRN(ir) = FRN(ir) * FRM(ir);
1334 break;
1335 case 3: /* FDIV FRm, FRn */
1336 FRN(ir) = FRN(ir) / FRM(ir);
1337 break;
1338 case 4: /* FCMP/EQ FRm, FRn */
1339 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1340 break;
1341 case 5: /* FCMP/GT FRm, FRn */
1342 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1343 break;
1344 case 6: /* FMOV.S [Rm+R0], FRn */
1345 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1346 break;
1347 case 7: /* FMOV.S FRm, [Rn+R0] */
1348 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1349 break;
1350 case 8: /* FMOV.S [Rm], FRn */
1351 MEM_FP_READ( RM(ir), FRNn(ir) );
1352 break;
1353 case 9: /* FMOV.S [Rm++], FRn */
1354 MEM_FP_READ( RM(ir), FRNn(ir) );
1355 RM(ir) += FP_WIDTH;
1356 break;
1357 case 10:/* FMOV.S FRm, [Rn] */
1358 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1359 break;
1360 case 11:/* FMOV.S FRm, [--Rn] */
1361 RN(ir) -= FP_WIDTH;
1362 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1363 break;
1364 case 12:/* FMOV FRm, FRn */
1365 if( IS_FPU_DOUBLESIZE() )
1366 DRN(ir) = DRM(ir);
1367 else
1368 FRN(ir) = FRM(ir);
1369 break;
1370 case 13:
1371 switch( (ir&0x00F0) >> 4 ) {
1372 case 0: /* FSTS FPUL, FRn */
1373 FRN(ir) = FPULf;
1374 break;
1375 case 1: /* FLDS FRn,FPUL */
1376 FPULf = FRN(ir);
1377 break;
1378 case 2: /* FLOAT FPUL, FRn */
1379 FRN(ir) = (float)FPULi;
1380 break;
1381 case 3: /* FTRC FRn, FPUL */
1382 ftmp = FRN(ir);
1383 if( ftmp >= MAX_INTF )
1384 FPULi = MAX_INT;
1385 else if( ftmp <= MIN_INTF )
1386 FPULi = MIN_INT;
1387 else
1388 FPULi = (int32_t)ftmp;
1389 break;
1390 case 4: /* FNEG FRn */
1391 FRN(ir) = -FRN(ir);
1392 break;
1393 case 5: /* FABS FRn */
1394 FRN(ir) = fabsf(FRN(ir));
1395 break;
1396 case 6: /* FSQRT FRn */
1397 FRN(ir) = sqrtf(FRN(ir));
1398 break;
1399 case 7: /* FSRRA FRn */
1400 FRN(ir) = 1.0/sqrtf(FRN(ir));
1401 break;
1402 case 8: /* FLDI0 FRn */
1403 FRN(ir) = 0.0;
1404 break;
1405 case 9: /* FLDI1 FRn */
1406 FRN(ir) = 1.0;
1407 break;
1408 case 10: /* FCNVSD FPUL, DRn */
1409 UNDEF(ir);
1410 break;
1411 case 11: /* FCNVDS DRn, FPUL */
1412 UNDEF(ir);
1413 break;
1414 case 14:/* FIPR FVm, FVn */
1415 /* FIXME: This is not going to be entirely accurate
1416 * as the SH4 instruction is less precise. Also
1417 * need to check for 0s and infinities.
1418 */
1419 {
1420 int tmp2 = FVN(ir);
1421 tmp = FVM(ir);
1422 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1423 FR(tmp+1)*FR(tmp2+1) +
1424 FR(tmp+2)*FR(tmp2+2) +
1425 FR(tmp+3)*FR(tmp2+3);
1426 break;
1427 }
1428 case 15:
1429 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1430 tmp = FVN(ir);
1431 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1432 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1433 XF(8)*fv[2] + XF(12)*fv[3];
1434 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1435 XF(9)*fv[2] + XF(13)*fv[3];
1436 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1437 XF(10)*fv[2] + XF(14)*fv[3];
1438 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1439 XF(11)*fv[2] + XF(15)*fv[3];
1440 break;
1441 }
1442 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1443 float angle = (((float)(short)(FPULi>>16)) +
1444 (((float)(FPULi&0xFFFF))/65536.0)) *
1445 2 * M_PI;
1446 int reg = FRNn(ir);
1447 FR(reg) = sinf(angle);
1448 FR(reg+1) = cosf(angle);
1449 break;
1450 }
1451 else if( ir == 0xFBFD ) {
1452 /* FRCHG */
1453 sh4r.fpscr ^= FPSCR_FR;
1454 break;
1455 }
1456 else if( ir == 0xF3FD ) {
1457 /* FSCHG */
1458 sh4r.fpscr ^= FPSCR_SZ;
1459 break;
1460 }
1461 default: UNDEF(ir);
1462 }
1463 break;
1464 case 14:/* FMAC FR0, FRm, FRn */
1465 FRN(ir) += FRM(ir)*FR0;
1466 break;
1467 default: UNDEF(ir);
1468 }
1469 }
1470 break;
1471 }
1472 sh4r.pc = sh4r.new_pc;
1473 sh4r.new_pc += 2;
1474 sh4r.in_delay_slot = 0;
1475 }
.