lxdream.org :: lxdream/src/asic.c r2:42349f6ea216

tree revision 12:7748fcf320b9

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     1 #include <assert.h>

     2 #include "dream.h"

     3 #include "mem.h"

     4 #include "sh4/intc.h"

     5 #include "asic.h"

     6 #include "dreamcast.h"

     7 #include "maple.h"

     8 #include "ide.h"

     9 #define MMIO_IMPL

    10 #include "asic.h"

    11 /*

    12  * Open questions:

    13  *   1) Does changing the mask after event occurance result in the

    14  *      interrupt being delivered immediately?

    15  *   2) If the pending register is not cleared after an interrupt, does

    16  *      the interrupt line remain high? (ie does the IRQ reoccur?)

    17  * TODO: Logic diagram of ASIC event/interrupt logic.

    18  *

    19  * ... don't even get me started on the "EXTDMA" page, about which, apparently,

    20  * practically nothing is publicly known...

    21  */

    23 void asic_init( void )

    24 {

    25     register_io_region( &mmio_region_ASIC );

    26     register_io_region( &mmio_region_EXTDMA );

    27     mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */

    28     asic_event( EVENT_GDROM_CMD );

    29 }

    31 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )

    32 {

    33     switch( reg ) {

    34         case PIRQ0:

    35         case PIRQ1:

    36         case PIRQ2:

    37             /* Clear any interrupts */

    38             MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );

    39             break;

    40         case MAPLE_STATE:

    41             MMIO_WRITE( ASIC, reg, val );

    42             if( val & 1 ) {

    43                 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;

    44 		WARN( "Maple request initiated at %08X, halting", maple_addr );

    45                 maple_handle_buffer( maple_addr );

    46                 MMIO_WRITE( ASIC, reg, 0 );

    47 //                dreamcast_stop();

    48             }

    49             break;

    50         default:

    51             MMIO_WRITE( ASIC, reg, val );

    52             WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",

    53                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );

    54     }

    55 }

    57 int32_t mmio_region_ASIC_read( uint32_t reg )

    58 {

    59     int32_t val;

    60     switch( reg ) {

    61         /*

    62         case 0x89C:

    63             sh4_stop();

    64             return 0x000000B;

    65         */

    66         case PIRQ0:

    67         case PIRQ1:

    68         case PIRQ2:

    69             val = MMIO_READ(ASIC, reg);

    70 //            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",

    71 //                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );

    72             return val;

    73         case G2STATUS:

    74             return 0; /* find out later if there's any cases we actually need to care about */

    75         default:

    76             val = MMIO_READ(ASIC, reg);

    77             WARN( "Read from ASIC (%03X => %08X) [%s: %s]",

    78                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );

    79             return val;

    80     }

    82 }

    84 void asic_event( int event )

    85 {

    86     int offset = ((event&0x60)>>3);

    87     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));

    89     if( result & MMIO_READ(ASIC, IRQA0 + offset) )

    90         intc_raise_interrupt( INT_IRQ13 );

    91     if( result & MMIO_READ(ASIC, IRQB0 + offset) )

    92         intc_raise_interrupt( INT_IRQ11 );

    93     if( result & MMIO_READ(ASIC, IRQC0 + offset) )

    94         intc_raise_interrupt( INT_IRQ9 );

    95 }

    99 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )

   100 {

   101     switch( reg ) {

   102         case IDEALTSTATUS: /* Device control */

   103             ide_write_control( val );

   104             break;

   105         case IDEDATA:

   106             ide_write_data_pio( val );

   107             break;

   108         case IDEFEAT:

   109             if( ide_can_write_regs() )

   110                 idereg.feature = (uint8_t)val;

   111             break;

   112         case IDECOUNT:

   113             if( ide_can_write_regs() )

   114                 idereg.count = (uint8_t)val;

   115             break;

   116         case IDELBA0:

   117             if( ide_can_write_regs() )

   118                 idereg.lba0 = (uint8_t)val;

   119             break;

   120         case IDELBA1:

   121             if( ide_can_write_regs() )

   122                 idereg.lba1 = (uint8_t)val;

   123             break;

   124         case IDELBA2:

   125             if( ide_can_write_regs() )

   126                 idereg.lba2 = (uint8_t)val;

   127             break;

   128         case IDEDEV:

   129             if( ide_can_write_regs() )

   130                 idereg.device = (uint8_t)val;

   131             break;

   132         case IDECMD:

   133             if( ide_can_write_regs() ) {

   134                 ide_clear_interrupt();

   135                 ide_write_command( (uint8_t)val );

   136             }

   137             break;

   139         default:

   140             MMIO_WRITE( EXTDMA, reg, val );

   141     }

   142 }

   144 MMIO_REGION_READ_FN( EXTDMA, reg )

   145 {

   146     switch( reg ) {

   147         case IDEALTSTATUS: return idereg.status;

   148         case IDEDATA: return ide_read_data_pio( );

   149         case IDEFEAT: return idereg.error;

   150         case IDECOUNT:return idereg.count;

   151         case IDELBA0: return idereg.disc;

   152         case IDELBA1: return idereg.lba1;

   153         case IDELBA2: return idereg.lba2;

   154         case IDEDEV: return idereg.device;

   155         case IDECMD:

   156             ide_clear_interrupt();

   157             return idereg.status;

   158         default:

   159             return MMIO_READ( EXTDMA, reg );

   160     }

   161 }