2 * $Id: sh4core.in,v 1.3 2007-09-08 03:12:21 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 #define EXV_EXCEPTION 0x100 /* General exception vector */
38 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
39 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
41 /********************** SH4 Module Definition ****************************/
43 void sh4_init( void );
44 void sh4_reset( void );
45 uint32_t sh4_run_slice( uint32_t );
46 void sh4_start( void );
47 void sh4_stop( void );
48 void sh4_save_state( FILE *f );
49 int sh4_load_state( FILE *f );
50 void sh4_accept_interrupt( void );
52 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
53 NULL, sh4_run_slice, sh4_stop,
54 sh4_save_state, sh4_load_state };
56 struct sh4_registers sh4r;
60 register_io_regions( mmio_list_sh4mmio );
67 /* zero everything out, for the sake of having a consistent state. */
68 memset( &sh4r, 0, sizeof(sh4r) );
70 /* Resume running if we were halted */
71 sh4r.sh4_state = SH4_STATE_RUNNING;
74 sh4r.new_pc= 0xA0000002;
75 sh4r.vbr = 0x00000000;
76 sh4r.fpscr = 0x00040001;
79 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
80 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
82 /* Peripheral modules */
90 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
91 static int sh4_breakpoint_count = 0;
92 static uint16_t *sh4_icache = NULL;
93 static uint32_t sh4_icache_addr = 0;
95 void sh4_set_breakpoint( uint32_t pc, int type )
97 sh4_breakpoints[sh4_breakpoint_count].address = pc;
98 sh4_breakpoints[sh4_breakpoint_count].type = type;
99 sh4_breakpoint_count++;
102 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
106 for( i=0; i<sh4_breakpoint_count; i++ ) {
107 if( sh4_breakpoints[i].address == pc &&
108 sh4_breakpoints[i].type == type ) {
109 while( ++i < sh4_breakpoint_count ) {
110 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
111 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
113 sh4_breakpoint_count--;
120 int sh4_get_breakpoint( uint32_t pc )
123 for( i=0; i<sh4_breakpoint_count; i++ ) {
124 if( sh4_breakpoints[i].address == pc )
125 return sh4_breakpoints[i].type;
130 uint32_t sh4_run_slice( uint32_t nanosecs )
133 sh4r.slice_cycle = 0;
135 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
136 if( sh4r.event_pending < nanosecs ) {
137 sh4r.sh4_state = SH4_STATE_RUNNING;
138 sh4r.slice_cycle = sh4r.event_pending;
142 if( sh4_breakpoint_count == 0 ) {
143 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
144 if( SH4_EVENT_PENDING() ) {
145 if( sh4r.event_types & PENDING_EVENT ) {
148 /* Eventq execute may (quite likely) deliver an immediate IRQ */
149 if( sh4r.event_types & PENDING_IRQ ) {
150 sh4_accept_interrupt();
153 if( !sh4_execute_instruction() ) {
158 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
159 if( SH4_EVENT_PENDING() ) {
160 if( sh4r.event_types & PENDING_EVENT ) {
163 /* Eventq execute may (quite likely) deliver an immediate IRQ */
164 if( sh4r.event_types & PENDING_IRQ ) {
165 sh4_accept_interrupt();
169 if( !sh4_execute_instruction() )
171 #ifdef ENABLE_DEBUG_MODE
172 for( i=0; i<sh4_breakpoint_count; i++ ) {
173 if( sh4_breakpoints[i].address == sh4r.pc ) {
177 if( i != sh4_breakpoint_count ) {
179 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
180 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
187 /* If we aborted early, but the cpu is still technically running,
188 * we're doing a hard abort - cut the timeslice back to what we
191 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
192 nanosecs = sh4r.slice_cycle;
194 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
195 TMU_run_slice( nanosecs );
196 SCIF_run_slice( nanosecs );
206 void sh4_save_state( FILE *f )
208 fwrite( &sh4r, sizeof(sh4r), 1, f );
210 INTC_save_state( f );
212 SCIF_save_state( f );
215 int sh4_load_state( FILE * f )
217 fread( &sh4r, sizeof(sh4r), 1, f );
219 INTC_load_state( f );
221 return SCIF_load_state( f );
224 /********************** SH4 emulation core ****************************/
226 void sh4_set_pc( int pc )
232 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
233 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
235 #if(SH4_CALLTRACE == 1)
236 #define MAX_CALLSTACK 32
237 static struct call_stack {
239 sh4addr_t target_addr;
240 sh4addr_t stack_pointer;
241 } call_stack[MAX_CALLSTACK];
243 static int call_stack_depth = 0;
244 int sh4_call_trace_on = 0;
246 static inline trace_call( sh4addr_t source, sh4addr_t dest )
248 if( call_stack_depth < MAX_CALLSTACK ) {
249 call_stack[call_stack_depth].call_addr = source;
250 call_stack[call_stack_depth].target_addr = dest;
251 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
256 static inline trace_return( sh4addr_t source, sh4addr_t dest )
258 if( call_stack_depth > 0 ) {
263 void fprint_stack_trace( FILE *f )
265 int i = call_stack_depth -1;
266 if( i >= MAX_CALLSTACK )
267 i = MAX_CALLSTACK - 1;
268 for( ; i >= 0; i-- ) {
269 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
270 (call_stack_depth - i), call_stack[i].call_addr,
271 call_stack[i].target_addr, call_stack[i].stack_pointer );
275 #define TRACE_CALL( source, dest ) trace_call(source, dest)
276 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
278 #define TRACE_CALL( dest, rts )
279 #define TRACE_RETURN( source, dest )
282 #define RAISE( x, v ) do{ \
283 if( sh4r.vbr == 0 ) { \
284 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
285 dreamcast_stop(); return FALSE; \
287 sh4r.spc = sh4r.pc; \
288 sh4r.ssr = sh4_read_sr(); \
289 sh4r.sgr = sh4r.r[15]; \
290 MMIO_WRITE(MMU,EXPEVT,x); \
291 sh4r.pc = sh4r.vbr + v; \
292 sh4r.new_pc = sh4r.pc + 2; \
293 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
294 if( sh4r.in_delay_slot ) { \
295 sh4r.in_delay_slot = 0; \
299 return TRUE; } while(0)
301 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
302 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
303 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
304 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
305 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
306 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
308 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
310 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
311 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
313 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
314 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
315 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
316 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
317 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
319 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
320 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
321 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
323 static void sh4_switch_banks( )
327 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
328 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
329 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
332 static void sh4_load_sr( uint32_t newval )
334 if( (newval ^ sh4r.sr) & SR_RB )
337 sh4r.t = (newval&SR_T) ? 1 : 0;
338 sh4r.s = (newval&SR_S) ? 1 : 0;
339 sh4r.m = (newval&SR_M) ? 1 : 0;
340 sh4r.q = (newval&SR_Q) ? 1 : 0;
344 static void sh4_write_float( uint32_t addr, int reg )
346 if( IS_FPU_DOUBLESIZE() ) {
348 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
349 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
351 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
352 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
355 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
359 static void sh4_read_float( uint32_t addr, int reg )
361 if( IS_FPU_DOUBLESIZE() ) {
363 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
364 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
366 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
367 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
370 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
374 static uint32_t sh4_read_sr( void )
376 /* synchronize sh4r.sr with the various bitflags */
377 sh4r.sr &= SR_MQSTMASK;
378 if( sh4r.t ) sh4r.sr |= SR_T;
379 if( sh4r.s ) sh4r.sr |= SR_S;
380 if( sh4r.m ) sh4r.sr |= SR_M;
381 if( sh4r.q ) sh4r.sr |= SR_Q;
386 * Raise a general CPU exception for the specified exception code.
387 * (NOT for TRAPA or TLB exceptions)
389 gboolean sh4_raise_exception( int code )
391 RAISE( code, EXV_EXCEPTION );
394 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
395 if( sh4r.in_delay_slot ) {
396 return sh4_raise_exception(slot_code);
398 return sh4_raise_exception(normal_code);
402 gboolean sh4_raise_tlb_exception( int code )
404 RAISE( code, EXV_TLBMISS );
407 void sh4_accept_interrupt( void )
409 uint32_t code = intc_accept_interrupt();
410 sh4r.ssr = sh4_read_sr();
412 sh4r.sgr = sh4r.r[15];
413 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
414 MMIO_WRITE( MMU, INTEVT, code );
415 sh4r.pc = sh4r.vbr + 0x600;
416 sh4r.new_pc = sh4r.pc + 2;
417 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
420 gboolean sh4_execute_instruction( void )
430 if( pc > 0xFFFFFF00 ) {
432 syscall_invoke( pc );
433 sh4r.in_delay_slot = 0;
434 pc = sh4r.pc = sh4r.pr;
435 sh4r.new_pc = sh4r.pc + 2;
439 /* Read instruction */
440 uint32_t pageaddr = pc >> 12;
441 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
442 ir = sh4_icache[(pc&0xFFF)>>1];
444 sh4_icache = (uint16_t *)mem_get_page(pc);
445 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
446 /* If someone's actually been so daft as to try to execute out of an IO
447 * region, fallback on the full-blown memory read
450 ir = MEM_READ_WORD(pc);
452 sh4_icache_addr = pageaddr;
453 ir = sh4_icache[(pc&0xFFF)>>1];
457 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
458 AND #imm, R0 {: R0 &= imm; :}
459 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
460 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
461 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
462 OR #imm, R0 {: R0 |= imm; :}
463 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
465 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
466 sh4r.t = ( tmp == 0 ? 1 : 0 );
467 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
469 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
470 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
471 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
472 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
473 XOR #imm, R0 {: R0 ^= imm; :}
474 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
475 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
478 sh4r.t = sh4r.r[Rn] >> 31;
480 sh4r.r[Rn] |= sh4r.t;
483 sh4r.t = sh4r.r[Rn] & 0x00000001;
485 sh4r.r[Rn] |= (sh4r.t << 31);
488 tmp = sh4r.r[Rn] >> 31;
490 sh4r.r[Rn] |= sh4r.t;
494 tmp = sh4r.r[Rn] & 0x00000001;
496 sh4r.r[Rn] |= (sh4r.t << 31 );
501 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
502 else if( (tmp & 0x1F) == 0 )
503 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
505 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
509 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
510 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
511 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
514 sh4r.t = sh4r.r[Rn] >> 31;
518 sh4r.t = sh4r.r[Rn] & 0x00000001;
519 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
521 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
522 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
523 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
524 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
525 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
526 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
527 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
528 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
530 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
531 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
532 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
533 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
534 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
535 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
537 CLRT {: sh4r.t = 0; :}
538 SETT {: sh4r.t = 1; :}
539 CLRMAC {: sh4r.mac = 0; :}
540 LDTLB {: /* TODO */ :}
541 CLRS {: sh4r.s = 0; :}
542 SETS {: sh4r.s = 1; :}
543 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
548 if( (tmp & 0xFC000000) == 0xE0000000 ) {
549 sh4_flush_store_queue(tmp);
558 MEM_WRITE_LONG( tmp, R0 );
560 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
561 MOV.W Rm, @(R0, Rn) {:
562 CHECKWALIGN16( R0 + sh4r.r[Rn] );
563 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
565 MOV.L Rm, @(R0, Rn) {:
566 CHECKWALIGN32( R0 + sh4r.r[Rn] );
567 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
569 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
570 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
571 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
573 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
574 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
576 MOV.L Rm, @(disp, Rn) {:
577 tmp = sh4r.r[Rn] + disp;
578 CHECKWALIGN32( tmp );
579 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
581 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
582 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
583 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
584 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
585 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
586 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
587 MOV.L @(disp, Rm), Rn {:
588 tmp = sh4r.r[Rm] + disp;
589 CHECKRALIGN32( tmp );
590 sh4r.r[Rn] = MEM_READ_LONG( tmp );
592 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
593 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
594 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
595 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
596 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
597 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
598 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
599 MOV.L @(disp, PC), Rn {:
601 tmp = (pc&0xFFFFFFFC) + disp + 4;
602 sh4r.r[Rn] = MEM_READ_LONG( tmp );
604 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
605 MOV.W R0, @(disp, GBR) {:
606 tmp = sh4r.gbr + disp;
607 CHECKWALIGN16( tmp );
608 MEM_WRITE_WORD( tmp, R0 );
610 MOV.L R0, @(disp, GBR) {:
611 tmp = sh4r.gbr + disp;
612 CHECKWALIGN32( tmp );
613 MEM_WRITE_LONG( tmp, R0 );
615 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
616 MOV.W @(disp, GBR), R0 {:
617 tmp = sh4r.gbr + disp;
618 CHECKRALIGN16( tmp );
619 R0 = MEM_READ_WORD( tmp );
621 MOV.L @(disp, GBR), R0 {:
622 tmp = sh4r.gbr + disp;
623 CHECKRALIGN32( tmp );
624 R0 = MEM_READ_LONG( tmp );
626 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
627 MOV.W R0, @(disp, Rn) {:
628 tmp = sh4r.r[Rn] + disp;
629 CHECKWALIGN16( tmp );
630 MEM_WRITE_WORD( tmp, R0 );
632 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
633 MOV.W @(disp, Rm), R0 {:
634 tmp = sh4r.r[Rm] + disp;
635 CHECKRALIGN16( tmp );
636 R0 = MEM_READ_WORD( tmp );
638 MOV.W @(disp, PC), Rn {:
641 sh4r.r[Rn] = MEM_READ_WORD( tmp );
643 MOVA @(disp, PC), R0 {:
645 R0 = (pc&0xFFFFFFFC) + disp + 4;
647 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
649 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
650 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
651 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
652 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
653 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
654 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
655 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
656 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
658 /* set T = 1 if any byte in RM & RN is the same */
659 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
660 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
661 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
664 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
665 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
668 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
669 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
672 tmp = sh4r.r[Rn] + sh4r.r[Rm];
673 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
676 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
678 sh4r.q = sh4r.r[Rn]>>31;
679 sh4r.m = sh4r.r[Rm]>>31;
680 sh4r.t = sh4r.q ^ sh4r.m;
683 /* This is just from the sh4p manual with some
684 * simplifications (someone want to check it's correct? :)
685 * Why they couldn't just provide a real DIV instruction...
687 uint32_t tmp0, tmp1, tmp2, dir;
689 dir = sh4r.q ^ sh4r.m;
690 sh4r.q = (sh4r.r[Rn] >> 31);
692 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
696 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
699 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
701 sh4r.q ^= sh4r.m ^ tmp1;
702 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
704 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
705 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
708 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
711 CHECKRALIGN16( sh4r.r[Rn] );
712 CHECKRALIGN16( sh4r.r[Rm] );
713 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
715 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
718 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
719 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
720 sh4r.mac = 0x000000017FFFFFFFLL;
721 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
722 sh4r.mac = 0x0000000180000000LL;
724 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
725 ((uint32_t)(sh4r.mac + stmp));
728 sh4r.mac += SIGNEXT32(stmp);
732 CHECKRALIGN32( sh4r.r[Rm] );
733 CHECKRALIGN32( sh4r.r[Rn] );
734 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
736 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
739 /* 48-bit Saturation. Yuch */
740 if( tmpl < (int64_t)0xFFFF800000000000LL )
741 tmpl = 0xFFFF800000000000LL;
742 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
743 tmpl = 0x00007FFFFFFFFFFFLL;
747 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
748 (sh4r.r[Rm] * sh4r.r[Rn]); :}
750 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
751 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
754 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
755 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
758 tmp = 0 - sh4r.r[Rm];
759 sh4r.r[Rn] = tmp - sh4r.t;
760 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
762 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
763 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
766 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
767 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
772 CHECKDEST( pc + 4 + sh4r.r[Rn] );
773 sh4r.in_delay_slot = 1;
774 sh4r.pc = sh4r.new_pc;
775 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
780 CHECKDEST( pc + 4 + sh4r.r[Rn] );
781 sh4r.in_delay_slot = 1;
782 sh4r.pr = sh4r.pc + 4;
783 sh4r.pc = sh4r.new_pc;
784 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
785 TRACE_CALL( pc, sh4r.new_pc );
791 CHECKDEST( sh4r.pc + disp + 4 )
793 sh4r.new_pc = sh4r.pc + 2;
800 CHECKDEST( sh4r.pc + disp + 4 )
802 sh4r.new_pc = sh4r.pc + 2;
809 CHECKDEST( sh4r.pc + disp + 4 )
810 sh4r.in_delay_slot = 1;
811 sh4r.pc = sh4r.new_pc;
812 sh4r.new_pc = pc + disp + 4;
813 sh4r.in_delay_slot = 1;
820 CHECKDEST( sh4r.pc + disp + 4 )
821 sh4r.in_delay_slot = 1;
822 sh4r.pc = sh4r.new_pc;
823 sh4r.new_pc = pc + disp + 4;
829 CHECKDEST( sh4r.pc + disp + 4 );
830 sh4r.in_delay_slot = 1;
831 sh4r.pc = sh4r.new_pc;
832 sh4r.new_pc = pc + 4 + disp;
836 CHECKDEST( sh4r.pc + disp + 4 );
838 sh4r.in_delay_slot = 1;
840 sh4r.pc = sh4r.new_pc;
841 sh4r.new_pc = pc + 4 + disp;
842 TRACE_CALL( pc, sh4r.new_pc );
847 MMIO_WRITE( MMU, TRA, imm<<2 );
849 sh4_raise_exception( EXC_TRAP );
853 CHECKDEST( sh4r.pr );
854 sh4r.in_delay_slot = 1;
855 sh4r.pc = sh4r.new_pc;
856 sh4r.new_pc = sh4r.pr;
857 TRACE_RETURN( pc, sh4r.new_pc );
861 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
862 sh4r.sh4_state = SH4_STATE_STANDBY;
864 sh4r.sh4_state = SH4_STATE_SLEEP;
866 return FALSE; /* Halt CPU */
870 CHECKDEST( sh4r.spc );
872 sh4r.in_delay_slot = 1;
873 sh4r.pc = sh4r.new_pc;
874 sh4r.new_pc = sh4r.spc;
875 sh4_load_sr( sh4r.ssr );
879 CHECKDEST( sh4r.r[Rn] );
881 sh4r.in_delay_slot = 1;
882 sh4r.pc = sh4r.new_pc;
883 sh4r.new_pc = sh4r.r[Rn];
887 CHECKDEST( sh4r.r[Rn] );
889 sh4r.in_delay_slot = 1;
890 sh4r.pc = sh4r.new_pc;
891 sh4r.new_pc = sh4r.r[Rn];
893 TRACE_CALL( pc, sh4r.new_pc );
896 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
899 CHECKWALIGN32( sh4r.r[Rn] );
900 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
905 CHECKWALIGN32( sh4r.r[Rn] );
906 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
909 CHECKRALIGN32( sh4r.r[Rm] );
910 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
911 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
917 CHECKWALIGN32( sh4r.r[Rm] );
918 sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) );
922 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
923 (((uint64_t)sh4r.r[Rm])<<32);
928 sh4_load_sr( sh4r.r[Rm] );
932 sh4r.sgr = sh4r.r[Rm];
936 CHECKRALIGN32( sh4r.r[Rm] );
937 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
940 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
943 CHECKWALIGN32( sh4r.r[Rn] );
944 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
948 CHECKWALIGN32( sh4r.r[Rn] );
949 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
952 CHECKRALIGN32( sh4r.r[Rm] );
953 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
954 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
958 CHECKRALIGN32( sh4r.r[Rm] );
959 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
963 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
964 (uint64_t)((uint32_t)(sh4r.r[Rm]));
966 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
967 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
970 CHECKWALIGN32( sh4r.r[Rn] );
971 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
976 CHECKWALIGN32( sh4r.r[Rn] );
977 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
980 CHECKRALIGN32( sh4r.r[Rm] );
981 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
986 CHECKRALIGN32( sh4r.r[Rm] );
987 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
990 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
993 sh4r.vbr = sh4r.r[Rm];
997 sh4r.r[Rn] = sh4r.sgr;
1002 CHECKWALIGN32( sh4r.r[Rn] );
1003 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
1008 CHECKWALIGN32( sh4r.r[Rn] );
1009 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
1013 CHECKRALIGN32( sh4r.r[Rm] );
1014 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
1019 sh4r.ssr = sh4r.r[Rm];
1024 CHECKWALIGN32( sh4r.r[Rn] );
1025 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
1029 CHECKRALIGN32( sh4r.r[Rm] );
1030 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
1035 sh4r.spc = sh4r.r[Rm];
1037 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
1040 CHECKWALIGN32( sh4r.r[Rn] );
1041 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
1044 CHECKRALIGN32( sh4r.r[Rm] );
1045 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
1048 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
1049 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
1050 STS.L FPSCR, @-Rn {:
1052 CHECKWALIGN32( sh4r.r[Rn] );
1053 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
1055 LDS.L @Rm+, FPSCR {:
1056 CHECKRALIGN32( sh4r.r[Rm] );
1057 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
1060 LDS Rm, FPSCR {: sh4r.fpscr = sh4r.r[Rm]; :}
1061 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
1065 CHECKWALIGN32( sh4r.r[Rn] );
1066 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
1070 CHECKRALIGN32( sh4r.r[Rm] );
1071 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
1076 sh4r.dbr = sh4r.r[Rm];
1078 STC.L Rm_BANK, @-Rn {:
1081 CHECKWALIGN32( sh4r.r[Rn] );
1082 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
1084 LDC.L @Rm+, Rn_BANK {:
1086 CHECKRALIGN32( sh4r.r[Rm] );
1087 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
1092 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1096 sh4r.r[Rn] = sh4_read_sr();
1100 sh4r.r[Rn] = sh4r.gbr;
1104 sh4r.r[Rn] = sh4r.vbr;
1108 sh4r.r[Rn] = sh4r.ssr;
1112 sh4r.r[Rn] = sh4r.spc;
1116 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
1121 if( IS_FPU_DOUBLEPREC() ) {
1129 if( IS_FPU_DOUBLEPREC() ) {
1138 if( IS_FPU_DOUBLEPREC() ) {
1147 if( IS_FPU_DOUBLEPREC() ) {
1156 if( IS_FPU_DOUBLEPREC() ) {
1157 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1159 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1165 if( IS_FPU_DOUBLEPREC() ) {
1166 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1168 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1172 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
1173 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
1174 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
1175 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
1176 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1177 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
1179 if( IS_FPU_DOUBLESIZE() )
1184 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
1185 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
1188 if( IS_FPU_DOUBLEPREC() )
1189 DR(FRn) = (float)FPULi;
1191 FR(FRn) = (float)FPULi;
1195 if( IS_FPU_DOUBLEPREC() ) {
1197 if( dtmp >= MAX_INTF )
1199 else if( dtmp <= MIN_INTF )
1202 FPULi = (int32_t)dtmp;
1205 if( ftmp >= MAX_INTF )
1207 else if( ftmp <= MIN_INTF )
1210 FPULi = (int32_t)ftmp;
1215 if( IS_FPU_DOUBLEPREC() ) {
1223 if( IS_FPU_DOUBLEPREC() ) {
1224 DR(FRn) = fabs(DR(FRn));
1226 FR(FRn) = fabsf(FR(FRn));
1231 if( IS_FPU_DOUBLEPREC() ) {
1232 DR(FRn) = sqrt(DR(FRn));
1234 FR(FRn) = sqrtf(FR(FRn));
1239 if( IS_FPU_DOUBLEPREC() ) {
1247 if( IS_FPU_DOUBLEPREC() ) {
1253 FMAC FR0, FRm, FRn {:
1255 if( IS_FPU_DOUBLEPREC() ) {
1256 DR(FRn) += DR(FRm)*DR(0);
1258 FR(FRn) += FR(FRm)*FR(0);
1261 FRCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR; :}
1262 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1265 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1266 DR(FRn) = (double)FPULf;
1271 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1272 FPULf = (float)DR(FRm);
1278 if( !IS_FPU_DOUBLEPREC() ) {
1279 FR(FRn) = 1.0/sqrtf(FR(FRn));
1284 if( !IS_FPU_DOUBLEPREC() ) {
1287 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1288 FR(tmp+1)*FR(tmp2+1) +
1289 FR(tmp+2)*FR(tmp2+2) +
1290 FR(tmp+3)*FR(tmp2+3);
1295 if( !IS_FPU_DOUBLEPREC() ) {
1296 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1297 FR(FRn) = sinf(angle);
1298 FR((FRn)+1) = cosf(angle);
1303 if( !IS_FPU_DOUBLEPREC() ) {
1305 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1306 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1307 XF(8)*fv[2] + XF(12)*fv[3];
1308 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1309 XF(9)*fv[2] + XF(13)*fv[3];
1310 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1311 XF(10)*fv[2] + XF(14)*fv[3];
1312 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1313 XF(11)*fv[2] + XF(15)*fv[3];
1320 sh4r.pc = sh4r.new_pc;
1322 sh4r.in_delay_slot = 0;
.