2 * $Id: sh4core.c,v 1.34 2006-12-12 09:20:25 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXV_ILLEGAL 0x100
45 #define EXC_TRAP 0x160
46 #define EXV_TRAP 0x100
47 #define EXC_FPDISABLE 0x800
48 #define EXV_FPDISABLE 0x100
50 /********************** SH4 Module Definition ****************************/
52 void sh4_init( void );
53 void sh4_reset( void );
54 uint32_t sh4_run_slice( uint32_t );
55 void sh4_start( void );
56 void sh4_stop( void );
57 void sh4_save_state( FILE *f );
58 int sh4_load_state( FILE *f );
60 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
61 NULL, sh4_run_slice, sh4_stop,
62 sh4_save_state, sh4_load_state };
64 struct sh4_registers sh4r;
68 register_io_regions( mmio_list_sh4mmio );
75 /* zero everything out, for the sake of having a consistent state. */
76 memset( &sh4r, 0, sizeof(sh4r) );
78 /* Resume running if we were halted */
79 sh4r.sh4_state = SH4_STATE_RUNNING;
82 sh4r.new_pc= 0xA0000002;
83 sh4r.vbr = 0x00000000;
84 sh4r.fpscr = 0x00040001;
87 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
88 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
90 /* Peripheral modules */
96 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
97 static int sh4_breakpoint_count = 0;
98 static uint16_t *sh4_icache = NULL;
99 static uint32_t sh4_icache_addr = 0;
101 void sh4_set_breakpoint( uint32_t pc, int type )
103 sh4_breakpoints[sh4_breakpoint_count].address = pc;
104 sh4_breakpoints[sh4_breakpoint_count].type = type;
105 sh4_breakpoint_count++;
108 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
112 for( i=0; i<sh4_breakpoint_count; i++ ) {
113 if( sh4_breakpoints[i].address == pc &&
114 sh4_breakpoints[i].type == type ) {
115 while( ++i < sh4_breakpoint_count ) {
116 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
117 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
119 sh4_breakpoint_count--;
126 int sh4_get_breakpoint( uint32_t pc )
129 for( i=0; i<sh4_breakpoint_count; i++ ) {
130 if( sh4_breakpoints[i].address == pc )
131 return sh4_breakpoints[i].type;
136 uint32_t sh4_run_slice( uint32_t nanosecs )
138 int target = sh4r.icount + nanosecs / sh4_cpu_period;
139 int start = sh4r.icount;
142 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
143 if( sh4r.int_pending != 0 )
144 sh4r.sh4_state = SH4_STATE_RUNNING;;
147 if( sh4_breakpoint_count == 0 ) {
148 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
149 if( !sh4_execute_instruction() ) {
155 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
156 if( !sh4_execute_instruction() )
158 #ifdef ENABLE_DEBUG_MODE
159 for( i=0; i<sh4_breakpoint_count; i++ ) {
160 if( sh4_breakpoints[i].address == sh4r.pc ) {
164 if( i != sh4_breakpoint_count ) {
166 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
167 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
174 /* If we aborted early, but the cpu is still technically running,
175 * we're doing a hard abort - cut the timeslice back to what we
178 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
179 nanosecs = sh4r.slice_cycle;
181 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
182 TMU_run_slice( nanosecs );
183 SCIF_run_slice( nanosecs );
185 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
194 void sh4_save_state( FILE *f )
196 fwrite( &sh4r, sizeof(sh4r), 1, f );
197 INTC_save_state( f );
199 SCIF_save_state( f );
202 int sh4_load_state( FILE * f )
204 fread( &sh4r, sizeof(sh4r), 1, f );
205 INTC_load_state( f );
207 return SCIF_load_state( f );
210 /********************** SH4 emulation core ****************************/
212 void sh4_set_pc( int pc )
218 #define UNDEF(ir) if( sh4r.in_delay_slot ) { RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 ); } else { RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 ); }
219 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
221 #if(SH4_CALLTRACE == 1)
222 #define MAX_CALLSTACK 32
223 static struct call_stack {
225 sh4addr_t target_addr;
226 sh4addr_t stack_pointer;
227 } call_stack[MAX_CALLSTACK];
229 static int call_stack_depth = 0;
230 int sh4_call_trace_on = 0;
232 static inline trace_call( sh4addr_t source, sh4addr_t dest )
234 if( call_stack_depth < MAX_CALLSTACK ) {
235 call_stack[call_stack_depth].call_addr = source;
236 call_stack[call_stack_depth].target_addr = dest;
237 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
242 static inline trace_return( sh4addr_t source, sh4addr_t dest )
244 if( call_stack_depth > 0 ) {
249 void fprint_stack_trace( FILE *f )
251 int i = call_stack_depth -1;
252 if( i >= MAX_CALLSTACK )
253 i = MAX_CALLSTACK - 1;
254 for( ; i >= 0; i-- ) {
255 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
256 (call_stack_depth - i), call_stack[i].call_addr,
257 call_stack[i].target_addr, call_stack[i].stack_pointer );
261 #define TRACE_CALL( source, dest ) trace_call(source, dest)
262 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
264 #define TRACE_CALL( dest, rts )
265 #define TRACE_RETURN( source, dest )
268 #define RAISE( x, v, pcadj ) do{ \
269 if( sh4r.vbr == 0 ) { \
270 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
271 dreamcast_stop(); return FALSE; \
273 sh4r.spc = sh4r.pc + pcadj; \
274 sh4r.ssr = sh4_read_sr(); \
275 sh4r.sgr = sh4r.r[15]; \
276 MMIO_WRITE(MMU,EXPEVT,x); \
277 sh4r.pc = sh4r.vbr + v; \
278 sh4r.new_pc = sh4r.pc + 2; \
279 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
280 sh4r.in_delay_slot = 0; \
282 return TRUE; } while(0)
283 #define RAISE_SLOTILLEGAL() RAISE( EXC_SLOT_ILLEGAL, EXV_ILLEGAL, -2 )
284 #define RAISE_ILLEGAL() RAISE( EXC_ILLEGAL, EXV_ILLEGAL, 0 )
286 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
287 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
288 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
289 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
290 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
291 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
293 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
295 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
297 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
299 #define CHECK( x, c, v ) if( !x ) RAISE( c, v, 0 )
300 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) { if( sh4r.in_delay_slot ) { RAISE_SLOTILLEGAL(); } else { RAISE_ILLEGAL(); } }
301 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
302 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
303 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
304 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
306 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
307 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
308 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL, -2); }
310 static void sh4_switch_banks( )
314 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
315 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
316 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
319 static void sh4_load_sr( uint32_t newval )
321 if( (newval ^ sh4r.sr) & SR_RB )
324 sh4r.t = (newval&SR_T) ? 1 : 0;
325 sh4r.s = (newval&SR_S) ? 1 : 0;
326 sh4r.m = (newval&SR_M) ? 1 : 0;
327 sh4r.q = (newval&SR_Q) ? 1 : 0;
331 static void sh4_write_float( uint32_t addr, int reg )
333 if( IS_FPU_DOUBLESIZE() ) {
335 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
336 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
338 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
339 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
342 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
346 static void sh4_read_float( uint32_t addr, int reg )
348 if( IS_FPU_DOUBLESIZE() ) {
350 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
351 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
353 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
354 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
357 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
361 static uint32_t sh4_read_sr( void )
363 /* synchronize sh4r.sr with the various bitflags */
364 sh4r.sr &= SR_MQSTMASK;
365 if( sh4r.t ) sh4r.sr |= SR_T;
366 if( sh4r.s ) sh4r.sr |= SR_S;
367 if( sh4r.m ) sh4r.sr |= SR_M;
368 if( sh4r.q ) sh4r.sr |= SR_Q;
371 /* function for external use */
372 void sh4_raise_exception( int code, int vector )
374 RAISE(code, vector, 0);
377 static void sh4_accept_interrupt( void )
379 uint32_t code = intc_accept_interrupt();
380 sh4r.ssr = sh4_read_sr();
382 sh4r.sgr = sh4r.r[15];
383 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
384 MMIO_WRITE( MMU, INTEVT, code );
385 sh4r.pc = sh4r.vbr + 0x600;
386 sh4r.new_pc = sh4r.pc + 2;
387 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
390 gboolean sh4_execute_instruction( void )
402 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
403 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
404 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
405 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
406 #define DISP8(ir) (ir&0x00FF)
407 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
408 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
409 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
410 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
411 #define FRNn(ir) ((ir&0x0F00)>>8)
412 #define FRMn(ir) ((ir&0x00F0)>>4)
413 #define DRNn(ir) ((ir&0x0E00)>>9)
414 #define DRMn(ir) ((ir&0x00E0)>>5)
415 #define FVN(ir) ((ir&0x0C00)>>8)
416 #define FVM(ir) ((ir&0x0300)>>6)
417 #define FRN(ir) FR(FRNn(ir))
418 #define FRM(ir) FR(FRMn(ir))
419 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
420 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
421 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
422 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
423 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
424 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
425 #define FPULf *((float *)&sh4r.fpul)
426 #define FPULi (sh4r.fpul)
428 if( SH4_INT_PENDING() )
429 sh4_accept_interrupt();
432 if( pc > 0xFFFFFF00 ) {
434 syscall_invoke( pc );
435 sh4r.in_delay_slot = 0;
436 pc = sh4r.pc = sh4r.pr;
437 sh4r.new_pc = sh4r.pc + 2;
441 /* Read instruction */
442 uint32_t pageaddr = pc >> 12;
443 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
444 ir = sh4_icache[(pc&0xFFF)>>1];
446 sh4_icache = (uint16_t *)mem_get_page(pc);
447 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
448 /* If someone's actually been so daft as to try to execute out of an IO
449 * region, fallback on the full-blown memory read
452 ir = MEM_READ_WORD(pc);
454 sh4_icache_addr = pageaddr;
455 ir = sh4_icache[(pc&0xFFF)>>1];
460 switch( (ir&0xF000)>>12 ) {
461 case 0: /* 0000nnnnmmmmxxxx */
462 switch( ir&0x000F ) {
464 switch( (ir&0x00F0)>>4 ) {
465 case 0: /* STC SR, Rn */
467 RN(ir) = sh4_read_sr();
469 case 1: /* STC GBR, Rn */
472 case 2: /* STC VBR, Rn */
476 case 3: /* STC SSR, Rn */
480 case 4: /* STC SPC, Rn */
484 case 8: case 9: case 10: case 11: case 12: case 13:
485 case 14: case 15:/* STC Rm_bank, Rn */
487 RN(ir) = RN_BANK(ir);
493 switch( (ir&0x00F0)>>4 ) {
494 case 0: /* BSRF Rn */
496 CHECKDEST( pc + 4 + RN(ir) );
497 sh4r.in_delay_slot = 1;
498 sh4r.pr = sh4r.pc + 4;
499 sh4r.pc = sh4r.new_pc;
500 sh4r.new_pc = pc + 4 + RN(ir);
501 TRACE_CALL( pc, sh4r.new_pc );
503 case 2: /* BRAF Rn */
505 CHECKDEST( pc + 4 + RN(ir) );
506 sh4r.in_delay_slot = 1;
507 sh4r.pc = sh4r.new_pc;
508 sh4r.new_pc = pc + 4 + RN(ir);
510 case 8: /* PREF [Rn] */
512 if( (tmp & 0xFC000000) == 0xE0000000 ) {
513 /* Store queue operation */
514 int queue = (tmp&0x20)>>2;
515 int32_t *src = &sh4r.store_queue[queue];
516 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
517 uint32_t target = tmp&0x03FFFFE0 | hi;
518 mem_copy_to_sh4( target, src, 32 );
521 case 9: /* OCBI [Rn] */
522 case 10:/* OCBP [Rn] */
523 case 11:/* OCBWB [Rn] */
526 case 12:/* MOVCA.L R0, [Rn] */
529 MEM_WRITE_LONG( tmp, R0 );
534 case 4: /* MOV.B Rm, [R0 + Rn] */
535 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
537 case 5: /* MOV.W Rm, [R0 + Rn] */
538 CHECKWALIGN16( R0 + RN(ir) );
539 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
541 case 6: /* MOV.L Rm, [R0 + Rn] */
542 CHECKWALIGN32( R0 + RN(ir) );
543 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
545 case 7: /* MUL.L Rm, Rn */
546 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
550 switch( (ir&0x0FF0)>>4 ) {
572 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
574 else if( ir == 0x0019 ) /* DIV0U */
575 sh4r.m = sh4r.q = sh4r.t = 0;
576 else if( ir == 0x0009 )
581 switch( (ir&0x00F0) >> 4 ) {
582 case 0: /* STS MACH, Rn */
583 RN(ir) = sh4r.mac >> 32;
585 case 1: /* STS MACL, Rn */
586 RN(ir) = (uint32_t)sh4r.mac;
588 case 2: /* STS PR, Rn */
591 case 3: /* STC SGR, Rn */
595 case 5:/* STS FPUL, Rn */
598 case 6: /* STS FPSCR, Rn */
601 case 15:/* STC DBR, Rn */
609 switch( (ir&0x0FF0)>>4 ) {
612 CHECKDEST( sh4r.pr );
613 sh4r.in_delay_slot = 1;
614 sh4r.pc = sh4r.new_pc;
615 sh4r.new_pc = sh4r.pr;
616 TRACE_RETURN( pc, sh4r.new_pc );
619 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
620 sh4r.sh4_state = SH4_STATE_STANDBY;
622 sh4r.sh4_state = SH4_STATE_SLEEP;
624 return FALSE; /* Halt CPU */
627 CHECKDEST( sh4r.spc );
629 sh4r.in_delay_slot = 1;
630 sh4r.pc = sh4r.new_pc;
631 sh4r.new_pc = sh4r.spc;
632 sh4_load_sr( sh4r.ssr );
637 case 12:/* MOV.B [R0+R%d], R%d */
638 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
640 case 13:/* MOV.W [R0+R%d], R%d */
641 CHECKRALIGN16( R0 + RM(ir) );
642 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
644 case 14:/* MOV.L [R0+R%d], R%d */
645 CHECKRALIGN32( R0 + RM(ir) );
646 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
648 case 15:/* MAC.L [Rm++], [Rn++] */
649 CHECKRALIGN32( RM(ir) );
650 CHECKRALIGN32( RN(ir) );
651 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
652 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
654 /* 48-bit Saturation. Yuch */
655 tmpl += SIGNEXT48(sh4r.mac);
656 if( tmpl < 0xFFFF800000000000LL )
657 tmpl = 0xFFFF800000000000LL;
658 else if( tmpl > 0x00007FFFFFFFFFFFLL )
659 tmpl = 0x00007FFFFFFFFFFFLL;
660 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
661 (tmpl&0x0000FFFFFFFFFFFFLL);
662 } else sh4r.mac = tmpl;
671 case 1: /* 0001nnnnmmmmdddd */
672 /* MOV.L Rm, [Rn + disp4*4] */
673 tmp = RN(ir) + (DISP4(ir)<<2);
674 CHECKWALIGN32( tmp );
675 MEM_WRITE_LONG( tmp, RM(ir) );
677 case 2: /* 0010nnnnmmmmxxxx */
678 switch( ir&0x000F ) {
679 case 0: /* MOV.B Rm, [Rn] */
680 MEM_WRITE_BYTE( RN(ir), RM(ir) );
682 case 1: /* MOV.W Rm, [Rn] */
683 CHECKWALIGN16( RN(ir) );
684 MEM_WRITE_WORD( RN(ir), RM(ir) );
686 case 2: /* MOV.L Rm, [Rn] */
687 CHECKWALIGN32( RN(ir) );
688 MEM_WRITE_LONG( RN(ir), RM(ir) );
692 case 4: /* MOV.B Rm, [--Rn] */
694 MEM_WRITE_BYTE( RN(ir), RM(ir) );
696 case 5: /* MOV.W Rm, [--Rn] */
698 CHECKWALIGN16( RN(ir) );
699 MEM_WRITE_WORD( RN(ir), RM(ir) );
701 case 6: /* MOV.L Rm, [--Rn] */
703 CHECKWALIGN32( RN(ir) );
704 MEM_WRITE_LONG( RN(ir), RM(ir) );
706 case 7: /* DIV0S Rm, Rn */
709 sh4r.t = sh4r.q ^ sh4r.m;
711 case 8: /* TST Rm, Rn */
712 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
714 case 9: /* AND Rm, Rn */
717 case 10:/* XOR Rm, Rn */
720 case 11:/* OR Rm, Rn */
723 case 12:/* CMP/STR Rm, Rn */
724 /* set T = 1 if any byte in RM & RN is the same */
725 tmp = RM(ir) ^ RN(ir);
726 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
727 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
729 case 13:/* XTRCT Rm, Rn */
730 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
732 case 14:/* MULU.W Rm, Rn */
733 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
734 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
736 case 15:/* MULS.W Rm, Rn */
737 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
738 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
742 case 3: /* 0011nnnnmmmmxxxx */
743 switch( ir&0x000F ) {
744 case 0: /* CMP/EQ Rm, Rn */
745 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
747 case 2: /* CMP/HS Rm, Rn */
748 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
750 case 3: /* CMP/GE Rm, Rn */
751 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
753 case 4: { /* DIV1 Rm, Rn */
754 /* This is just from the sh4p manual with some
755 * simplifications (someone want to check it's correct? :)
756 * Why they couldn't just provide a real DIV instruction...
757 * Please oh please let the translator batch these things
758 * up into a single DIV... */
759 uint32_t tmp0, tmp1, tmp2, dir;
761 dir = sh4r.q ^ sh4r.m;
762 sh4r.q = (RN(ir) >> 31);
764 RN(ir) = (RN(ir) << 1) | sh4r.t;
768 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
771 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
773 sh4r.q ^= sh4r.m ^ tmp1;
774 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
776 case 5: /* DMULU.L Rm, Rn */
777 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
779 case 6: /* CMP/HI Rm, Rn */
780 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
782 case 7: /* CMP/GT Rm, Rn */
783 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
785 case 8: /* SUB Rm, Rn */
788 case 10:/* SUBC Rm, Rn */
790 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
791 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
793 case 11:/* SUBV Rm, Rn */
796 case 12:/* ADD Rm, Rn */
799 case 13:/* DMULS.L Rm, Rn */
800 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
802 case 14:/* ADDC Rm, Rn */
804 RN(ir) += RM(ir) + sh4r.t;
805 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
807 case 15:/* ADDV Rm, Rn */
808 tmp = RN(ir) + RM(ir);
809 sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
815 case 4: /* 0100nnnnxxxxxxxx */
816 switch( ir&0x00FF ) {
817 case 0x00: /* SHLL Rn */
818 sh4r.t = RN(ir) >> 31;
821 case 0x01: /* SHLR Rn */
822 sh4r.t = RN(ir) & 0x00000001;
825 case 0x02: /* STS.L MACH, [--Rn] */
827 CHECKWALIGN32( RN(ir) );
828 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
830 case 0x03: /* STC.L SR, [--Rn] */
833 CHECKWALIGN32( RN(ir) );
834 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
836 case 0x04: /* ROTL Rn */
837 sh4r.t = RN(ir) >> 31;
841 case 0x05: /* ROTR Rn */
842 sh4r.t = RN(ir) & 0x00000001;
844 RN(ir) |= (sh4r.t << 31);
846 case 0x06: /* LDS.L [Rn++], MACH */
847 CHECKRALIGN32( RN(ir) );
848 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
849 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
852 case 0x07: /* LDC.L [Rn++], SR */
855 CHECKWALIGN32( RN(ir) );
856 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
859 case 0x08: /* SHLL2 Rn */
862 case 0x09: /* SHLR2 Rn */
865 case 0x0A: /* LDS Rn, MACH */
866 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
867 (((uint64_t)RN(ir))<<32);
869 case 0x0B: /* JSR [Rn] */
872 sh4r.in_delay_slot = 1;
873 sh4r.pc = sh4r.new_pc;
874 sh4r.new_pc = RN(ir);
876 TRACE_CALL( pc, sh4r.new_pc );
878 case 0x0E: /* LDC Rn, SR */
881 sh4_load_sr( RN(ir) );
883 case 0x10: /* DT Rn */
885 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
887 case 0x11: /* CMP/PZ Rn */
888 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
890 case 0x12: /* STS.L MACL, [--Rn] */
892 CHECKWALIGN32( RN(ir) );
893 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
895 case 0x13: /* STC.L GBR, [--Rn] */
897 CHECKWALIGN32( RN(ir) );
898 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
900 case 0x15: /* CMP/PL Rn */
901 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
903 case 0x16: /* LDS.L [Rn++], MACL */
904 CHECKRALIGN32( RN(ir) );
905 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
906 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
909 case 0x17: /* LDC.L [Rn++], GBR */
910 CHECKRALIGN32( RN(ir) );
911 sh4r.gbr = MEM_READ_LONG(RN(ir));
914 case 0x18: /* SHLL8 Rn */
917 case 0x19: /* SHLR8 Rn */
920 case 0x1A: /* LDS Rn, MACL */
921 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
922 (uint64_t)((uint32_t)(RN(ir)));
924 case 0x1B: /* TAS.B [Rn] */
925 tmp = MEM_READ_BYTE( RN(ir) );
926 sh4r.t = ( tmp == 0 ? 1 : 0 );
927 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
929 case 0x1E: /* LDC Rn, GBR */
932 case 0x20: /* SHAL Rn */
933 sh4r.t = RN(ir) >> 31;
936 case 0x21: /* SHAR Rn */
937 sh4r.t = RN(ir) & 0x00000001;
938 RN(ir) = ((int32_t)RN(ir)) >> 1;
940 case 0x22: /* STS.L PR, [--Rn] */
942 CHECKWALIGN32( RN(ir) );
943 MEM_WRITE_LONG( RN(ir), sh4r.pr );
945 case 0x23: /* STC.L VBR, [--Rn] */
948 CHECKWALIGN32( RN(ir) );
949 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
951 case 0x24: /* ROTCL Rn */
957 case 0x25: /* ROTCR Rn */
958 tmp = RN(ir) & 0x00000001;
960 RN(ir) |= (sh4r.t << 31 );
963 case 0x26: /* LDS.L [Rn++], PR */
964 CHECKRALIGN32( RN(ir) );
965 sh4r.pr = MEM_READ_LONG( RN(ir) );
968 case 0x27: /* LDC.L [Rn++], VBR */
970 CHECKRALIGN32( RN(ir) );
971 sh4r.vbr = MEM_READ_LONG(RN(ir));
974 case 0x28: /* SHLL16 Rn */
977 case 0x29: /* SHLR16 Rn */
980 case 0x2A: /* LDS Rn, PR */
983 case 0x2B: /* JMP [Rn] */
986 sh4r.in_delay_slot = 1;
987 sh4r.pc = sh4r.new_pc;
988 sh4r.new_pc = RN(ir);
990 case 0x2E: /* LDC Rn, VBR */
994 case 0x32: /* STC.L SGR, [--Rn] */
997 CHECKWALIGN32( RN(ir) );
998 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
1000 case 0x33: /* STC.L SSR, [--Rn] */
1003 CHECKWALIGN32( RN(ir) );
1004 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
1006 case 0x37: /* LDC.L [Rn++], SSR */
1008 CHECKRALIGN32( RN(ir) );
1009 sh4r.ssr = MEM_READ_LONG(RN(ir));
1012 case 0x3E: /* LDC Rn, SSR */
1016 case 0x43: /* STC.L SPC, [--Rn] */
1019 CHECKWALIGN32( RN(ir) );
1020 MEM_WRITE_LONG( RN(ir), sh4r.spc );
1022 case 0x47: /* LDC.L [Rn++], SPC */
1024 CHECKRALIGN32( RN(ir) );
1025 sh4r.spc = MEM_READ_LONG(RN(ir));
1028 case 0x4E: /* LDC Rn, SPC */
1032 case 0x52: /* STS.L FPUL, [--Rn] */
1034 CHECKWALIGN32( RN(ir) );
1035 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
1037 case 0x56: /* LDS.L [Rn++], FPUL */
1038 CHECKRALIGN32( RN(ir) );
1039 sh4r.fpul = MEM_READ_LONG(RN(ir));
1042 case 0x5A: /* LDS Rn, FPUL */
1045 case 0x62: /* STS.L FPSCR, [--Rn] */
1047 CHECKWALIGN32( RN(ir) );
1048 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
1050 case 0x66: /* LDS.L [Rn++], FPSCR */
1051 CHECKRALIGN32( RN(ir) );
1052 sh4r.fpscr = MEM_READ_LONG(RN(ir));
1055 case 0x6A: /* LDS Rn, FPSCR */
1056 sh4r.fpscr = RN(ir);
1058 case 0xF2: /* STC.L DBR, [--Rn] */
1061 CHECKWALIGN32( RN(ir) );
1062 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
1064 case 0xF6: /* LDC.L [Rn++], DBR */
1066 CHECKRALIGN32( RN(ir) );
1067 sh4r.dbr = MEM_READ_LONG(RN(ir));
1070 case 0xFA: /* LDC Rn, DBR */
1074 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
1075 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
1078 CHECKWALIGN32( RN(ir) );
1079 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1081 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1082 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1084 CHECKRALIGN32( RN(ir) );
1085 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1088 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1089 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1091 RN_BANK(ir) = RM(ir);
1094 if( (ir&0x000F) == 0x0F ) {
1095 /* MAC.W [Rm++], [Rn++] */
1096 CHECKRALIGN16( RN(ir) );
1097 CHECKRALIGN16( RM(ir) );
1098 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1099 SIGNEXT16(MEM_READ_WORD(RN(ir)));
1103 } else sh4r.mac += SIGNEXT32(tmp);
1106 } else if( (ir&0x000F) == 0x0C ) {
1109 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1110 else if( (tmp & 0x1F) == 0 )
1111 RN(ir) = ((int32_t)RN(ir)) >> 31;
1113 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
1114 } else if( (ir&0x000F) == 0x0D ) {
1117 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1118 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1119 else RN(ir) >>= (((~tmp) & 0x1F)+1);
1123 case 5: /* 0101nnnnmmmmdddd */
1124 /* MOV.L [Rm + disp4*4], Rn */
1125 tmp = RM(ir) + (DISP4(ir)<<2);
1126 CHECKRALIGN32( tmp );
1127 RN(ir) = MEM_READ_LONG( tmp );
1129 case 6: /* 0110xxxxxxxxxxxx */
1130 switch( ir&0x000f ) {
1131 case 0: /* MOV.B [Rm], Rn */
1132 RN(ir) = MEM_READ_BYTE( RM(ir) );
1134 case 1: /* MOV.W [Rm], Rn */
1135 CHECKRALIGN16( RM(ir) );
1136 RN(ir) = MEM_READ_WORD( RM(ir) );
1138 case 2: /* MOV.L [Rm], Rn */
1139 CHECKRALIGN32( RM(ir) );
1140 RN(ir) = MEM_READ_LONG( RM(ir) );
1142 case 3: /* MOV Rm, Rn */
1145 case 4: /* MOV.B [Rm++], Rn */
1146 RN(ir) = MEM_READ_BYTE( RM(ir) );
1149 case 5: /* MOV.W [Rm++], Rn */
1150 CHECKRALIGN16( RM(ir) );
1151 RN(ir) = MEM_READ_WORD( RM(ir) );
1154 case 6: /* MOV.L [Rm++], Rn */
1155 CHECKRALIGN32( RM(ir) );
1156 RN(ir) = MEM_READ_LONG( RM(ir) );
1159 case 7: /* NOT Rm, Rn */
1162 case 8: /* SWAP.B Rm, Rn */
1163 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1164 ((RM(ir)&0x000000FF)<<8);
1166 case 9: /* SWAP.W Rm, Rn */
1167 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1169 case 10:/* NEGC Rm, Rn */
1171 RN(ir) = tmp - sh4r.t;
1172 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1174 case 11:/* NEG Rm, Rn */
1175 RN(ir) = 0 - RM(ir);
1177 case 12:/* EXTU.B Rm, Rn */
1178 RN(ir) = RM(ir)&0x000000FF;
1180 case 13:/* EXTU.W Rm, Rn */
1181 RN(ir) = RM(ir)&0x0000FFFF;
1183 case 14:/* EXTS.B Rm, Rn */
1184 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1186 case 15:/* EXTS.W Rm, Rn */
1187 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1191 case 7: /* 0111nnnniiiiiiii */
1195 case 8: /* 1000xxxxxxxxxxxx */
1196 switch( (ir&0x0F00) >> 8 ) {
1197 case 0: /* MOV.B R0, [Rm + disp4] */
1198 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1200 case 1: /* MOV.W R0, [Rm + disp4*2] */
1201 tmp = RM(ir) + (DISP4(ir)<<1);
1202 CHECKWALIGN16( tmp );
1203 MEM_WRITE_WORD( tmp, R0 );
1205 case 4: /* MOV.B [Rm + disp4], R0 */
1206 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1208 case 5: /* MOV.W [Rm + disp4*2], R0 */
1209 tmp = RM(ir) + (DISP4(ir)<<1);
1210 CHECKRALIGN16( tmp );
1211 R0 = MEM_READ_WORD( tmp );
1213 case 8: /* CMP/EQ imm, R0 */
1214 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1216 case 9: /* BT disp8 */
1219 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1220 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1221 sh4r.new_pc = sh4r.pc + 2;
1225 case 11:/* BF disp8 */
1228 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1229 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1230 sh4r.new_pc = sh4r.pc + 2;
1234 case 13:/* BT/S disp8 */
1237 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1238 sh4r.in_delay_slot = 1;
1239 sh4r.pc = sh4r.new_pc;
1240 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1241 sh4r.in_delay_slot = 1;
1245 case 15:/* BF/S disp8 */
1248 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1249 sh4r.in_delay_slot = 1;
1250 sh4r.pc = sh4r.new_pc;
1251 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1258 case 9: /* 1001xxxxxxxxxxxx */
1259 /* MOV.W [disp8*2 + pc + 4], Rn */
1261 tmp = pc + 4 + (DISP8(ir)<<1);
1262 RN(ir) = MEM_READ_WORD( tmp );
1264 case 10:/* 1010dddddddddddd */
1267 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1268 sh4r.in_delay_slot = 1;
1269 sh4r.pc = sh4r.new_pc;
1270 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1272 case 11:/* 1011dddddddddddd */
1274 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1276 sh4r.in_delay_slot = 1;
1278 sh4r.pc = sh4r.new_pc;
1279 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1280 TRACE_CALL( pc, sh4r.new_pc );
1282 case 12:/* 1100xxxxdddddddd */
1283 switch( (ir&0x0F00)>>8 ) {
1284 case 0: /* MOV.B R0, [GBR + disp8] */
1285 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1287 case 1: /* MOV.W R0, [GBR + disp8*2] */
1288 tmp = sh4r.gbr + (DISP8(ir)<<1);
1289 CHECKWALIGN16( tmp );
1290 MEM_WRITE_WORD( tmp, R0 );
1292 case 2: /*MOV.L R0, [GBR + disp8*4] */
1293 tmp = sh4r.gbr + (DISP8(ir)<<2);
1294 CHECKWALIGN32( tmp );
1295 MEM_WRITE_LONG( tmp, R0 );
1297 case 3: /* TRAPA imm8 */
1299 sh4r.in_delay_slot = 1;
1300 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1301 RAISE( EXC_TRAP, EXV_TRAP, 2 );
1303 case 4: /* MOV.B [GBR + disp8], R0 */
1304 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1306 case 5: /* MOV.W [GBR + disp8*2], R0 */
1307 tmp = sh4r.gbr + (DISP8(ir)<<1);
1308 CHECKRALIGN16( tmp );
1309 R0 = MEM_READ_WORD( tmp );
1311 case 6: /* MOV.L [GBR + disp8*4], R0 */
1312 tmp = sh4r.gbr + (DISP8(ir)<<2);
1313 CHECKRALIGN32( tmp );
1314 R0 = MEM_READ_LONG( tmp );
1316 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1318 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1320 case 8: /* TST imm8, R0 */
1321 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1323 case 9: /* AND imm8, R0 */
1326 case 10:/* XOR imm8, R0 */
1329 case 11:/* OR imm8, R0 */
1332 case 12:/* TST.B imm8, [R0+GBR] */
1333 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1335 case 13:/* AND.B imm8, [R0+GBR] */
1336 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1337 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1339 case 14:/* XOR.B imm8, [R0+GBR] */
1340 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1341 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1343 case 15:/* OR.B imm8, [R0+GBR] */
1344 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1345 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1349 case 13:/* 1101nnnndddddddd */
1350 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1352 tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1353 RN(ir) = MEM_READ_LONG( tmp );
1355 case 14:/* 1110nnnniiiiiiii */
1359 case 15:/* 1111xxxxxxxxxxxx */
1361 if( IS_FPU_DOUBLEPREC() ) {
1362 switch( ir&0x000F ) {
1363 case 0: /* FADD FRm, FRn */
1366 case 1: /* FSUB FRm, FRn */
1369 case 2: /* FMUL FRm, FRn */
1370 DRN(ir) = DRN(ir) * DRM(ir);
1372 case 3: /* FDIV FRm, FRn */
1373 DRN(ir) = DRN(ir) / DRM(ir);
1375 case 4: /* FCMP/EQ FRm, FRn */
1376 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1378 case 5: /* FCMP/GT FRm, FRn */
1379 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1381 case 6: /* FMOV.S [Rm+R0], FRn */
1382 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1384 case 7: /* FMOV.S FRm, [Rn+R0] */
1385 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1387 case 8: /* FMOV.S [Rm], FRn */
1388 MEM_FP_READ( RM(ir), FRNn(ir) );
1390 case 9: /* FMOV.S [Rm++], FRn */
1391 MEM_FP_READ( RM(ir), FRNn(ir) );
1394 case 10:/* FMOV.S FRm, [Rn] */
1395 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1397 case 11:/* FMOV.S FRm, [--Rn] */
1399 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1401 case 12:/* FMOV FRm, FRn */
1402 if( IS_FPU_DOUBLESIZE() )
1408 switch( (ir&0x00F0) >> 4 ) {
1409 case 0: /* FSTS FPUL, FRn */
1412 case 1: /* FLDS FRn,FPUL */
1415 case 2: /* FLOAT FPUL, FRn */
1416 DRN(ir) = (float)FPULi;
1418 case 3: /* FTRC FRn, FPUL */
1420 if( dtmp >= MAX_INTF )
1422 else if( dtmp <= MIN_INTF )
1425 FPULi = (int32_t)dtmp;
1427 case 4: /* FNEG FRn */
1430 case 5: /* FABS FRn */
1431 DRN(ir) = fabs(DRN(ir));
1433 case 6: /* FSQRT FRn */
1434 DRN(ir) = sqrt(DRN(ir));
1436 case 7: /* FSRRA FRn */
1437 /* NO-OP when PR=1 */
1439 case 8: /* FLDI0 FRn */
1442 case 9: /* FLDI1 FRn */
1445 case 10: /* FCNVSD FPUL, DRn */
1446 if( ! IS_FPU_DOUBLESIZE() )
1447 DRN(ir) = (double)FPULf;
1449 case 11: /* FCNVDS DRn, FPUL */
1450 if( ! IS_FPU_DOUBLESIZE() )
1451 FPULf = (float)DRN(ir);
1453 case 14:/* FIPR FVm, FVn */
1454 /* NO-OP when PR=1 */
1457 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1458 /* NO-OP when PR=1 */
1461 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1462 /* NO-OP when PR=1 */
1465 else if( ir == 0xFBFD ) {
1467 sh4r.fpscr ^= FPSCR_FR;
1470 else if( ir == 0xF3FD ) {
1472 sh4r.fpscr ^= FPSCR_SZ;
1478 case 14:/* FMAC FR0, FRm, FRn */
1479 DRN(ir) += DRM(ir)*DR0;
1483 } else { /* Single precision */
1484 switch( ir&0x000F ) {
1485 case 0: /* FADD FRm, FRn */
1488 case 1: /* FSUB FRm, FRn */
1491 case 2: /* FMUL FRm, FRn */
1492 FRN(ir) = FRN(ir) * FRM(ir);
1494 case 3: /* FDIV FRm, FRn */
1495 FRN(ir) = FRN(ir) / FRM(ir);
1497 case 4: /* FCMP/EQ FRm, FRn */
1498 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1500 case 5: /* FCMP/GT FRm, FRn */
1501 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1503 case 6: /* FMOV.S [Rm+R0], FRn */
1504 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1506 case 7: /* FMOV.S FRm, [Rn+R0] */
1507 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1509 case 8: /* FMOV.S [Rm], FRn */
1510 MEM_FP_READ( RM(ir), FRNn(ir) );
1512 case 9: /* FMOV.S [Rm++], FRn */
1513 MEM_FP_READ( RM(ir), FRNn(ir) );
1516 case 10:/* FMOV.S FRm, [Rn] */
1517 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1519 case 11:/* FMOV.S FRm, [--Rn] */
1521 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1523 case 12:/* FMOV FRm, FRn */
1524 if( IS_FPU_DOUBLESIZE() )
1530 switch( (ir&0x00F0) >> 4 ) {
1531 case 0: /* FSTS FPUL, FRn */
1534 case 1: /* FLDS FRn,FPUL */
1537 case 2: /* FLOAT FPUL, FRn */
1538 FRN(ir) = (float)FPULi;
1540 case 3: /* FTRC FRn, FPUL */
1542 if( ftmp >= MAX_INTF )
1544 else if( ftmp <= MIN_INTF )
1547 FPULi = (int32_t)ftmp;
1549 case 4: /* FNEG FRn */
1552 case 5: /* FABS FRn */
1553 FRN(ir) = fabsf(FRN(ir));
1555 case 6: /* FSQRT FRn */
1556 FRN(ir) = sqrtf(FRN(ir));
1558 case 7: /* FSRRA FRn */
1559 FRN(ir) = 1.0/sqrtf(FRN(ir));
1561 case 8: /* FLDI0 FRn */
1564 case 9: /* FLDI1 FRn */
1567 case 10: /* FCNVSD FPUL, DRn */
1569 case 11: /* FCNVDS DRn, FPUL */
1571 case 14:/* FIPR FVm, FVn */
1572 /* FIXME: This is not going to be entirely accurate
1573 * as the SH4 instruction is less precise. Also
1574 * need to check for 0s and infinities.
1579 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1580 FR(tmp+1)*FR(tmp2+1) +
1581 FR(tmp+2)*FR(tmp2+2) +
1582 FR(tmp+3)*FR(tmp2+3);
1586 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1588 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1589 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1590 XF(8)*fv[2] + XF(12)*fv[3];
1591 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1592 XF(9)*fv[2] + XF(13)*fv[3];
1593 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1594 XF(10)*fv[2] + XF(14)*fv[3];
1595 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1596 XF(11)*fv[2] + XF(15)*fv[3];
1599 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1600 float angle = (((float)(short)(FPULi>>16)) +
1601 (((float)(FPULi&0xFFFF))/65536.0)) *
1604 FR(reg) = sinf(angle);
1605 FR(reg+1) = cosf(angle);
1608 else if( ir == 0xFBFD ) {
1610 sh4r.fpscr ^= FPSCR_FR;
1613 else if( ir == 0xF3FD ) {
1615 sh4r.fpscr ^= FPSCR_SZ;
1621 case 14:/* FMAC FR0, FRm, FRn */
1622 FRN(ir) += FRM(ir)*FR0;
1629 sh4r.pc = sh4r.new_pc;
1631 sh4r.in_delay_slot = 0;
.