lxdream.org :: lxdream/src/sh4/sh4x86.c r361:be3de4ecd954

tree revision 361:be3de4ecd954

filename	src/sh4/sh4x86.c
changeset	361:be3de4ecd954
prev	359:c588dce7ebde
next	368:36fac4c42322
author	nkeynes
date	Tue Aug 28 08:46:14 2007 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Translator WIP: fill out and correct another batch of instructions

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     1 /**

     2  * $Id: sh4x86.c,v 1.2 2007-08-28 08:46:14 nkeynes Exp $

     3  *

     4  * SH4 => x86 translation. This version does no real optimization, it just

     5  * outputs straight-line x86 code - it mainly exists to provide a baseline

     6  * to test the optimizing versions against.

     7  *

     8  * Copyright (c) 2007 Nathan Keynes.

     9  *

    10  * This program is free software; you can redistribute it and/or modify

    11  * it under the terms of the GNU General Public License as published by

    12  * the Free Software Foundation; either version 2 of the License, or

    13  * (at your option) any later version.

    14  *

    15  * This program is distributed in the hope that it will be useful,

    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    18  * GNU General Public License for more details.

    19  */

    21 #include "sh4core.h"

    22 #include "sh4trans.h"

    23 #include "x86op.h"

    25 /**

    26  * Emit an instruction to load an SH4 reg into a real register

    27  */

    28 static inline void load_reg( int x86reg, int sh4reg )

    29 {

    30     /* mov [bp+n], reg */

    31     OP(0x8B);

    32     OP(0x45 + (x86reg<<3));

    33     OP(REG_OFFSET(r[sh4reg]));

    34 }

    36 static inline void load_spreg( int x86reg, int regoffset )

    37 {

    38     /* mov [bp+n], reg */

    39     OP(0x8B);

    40     OP(0x45 + (x86reg<<3));

    41     OP(regoffset);

    42 }

    44 /**

    45  * Emit an instruction to load an immediate value into a register

    46  */

    47 static inline void load_imm32( int x86reg, uint32_t value ) {

    48     /* mov #value, reg */

    49     OP(0xB8 + x86reg);

    50     OP32(value);

    51 }

    53 /**

    54  * Emit an instruction to store an SH4 reg (RN)

    55  */

    56 void static inline store_reg( int x86reg, int sh4reg ) {

    57     /* mov reg, [bp+n] */

    58     OP(0x89);

    59     OP(0x45 + (x86reg<<3));

    60     OP(REG_OFFSET(r[sh4reg]));

    61 }

    62 void static inline store_spreg( int x86reg, int regoffset ) {

    63     /* mov reg, [bp+n] */

    64     OP(0x89);

    65     OP(0x45 + (x86reg<<3));

    66     OP(regoffset);

    67 }

    69 /**

    70  * Note: clobbers EAX to make the indirect call - this isn't usually

    71  * a problem since the callee will usually clobber it anyway.

    72  */

    73 static inline void call_func0( void *ptr )

    74 {

    75     load_imm32(R_EAX, (uint32_t)ptr);

    76     OP(0xFF);

    77     MODRM_rm32_r32(R_EAX, 2);

    78 }

    80 static inline void call_func1( void *ptr, int arg1 )

    81 {

    82     PUSH_r32(arg1);

    83     call_func0(ptr);

    84     ADD_imm8s_r32( -4, R_ESP );

    85 }

    87 static inline void call_func2( void *ptr, int arg1, int arg2 )

    88 {

    89     PUSH_r32(arg2);

    90     PUSH_r32(arg1);

    91     call_func0(ptr);

    92     ADD_imm8s_r32( -4, R_ESP );

    93 }

    95 #define UNDEF()

    96 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }

    97 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)

    98 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)

    99 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)

   100 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)

   101 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)

   102 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)

   105 /**

   106  * Emit the 'start of block' assembly. Sets up the stack frame and save

   107  * SI/DI as required

   108  */

   109 void sh4_translate_begin_block() {

   110     /* push ebp */

   111     *xlat_output++ = 0x50 + R_EBP;

   113     /* mov &sh4r, ebp */

   114     load_imm32( R_EBP, (uint32_t)&sh4r );

   116     /* load carry from SR */

   117 }

   119 /**

   120  * Flush any open regs back to memory, restore SI/DI/, update PC, etc

   121  */

   122 void sh4_translate_end_block( sh4addr_t pc ) {

   123     /* pop ebp */

   124     *xlat_output++ = 0x58 + R_EBP;

   126     /* ret */

   127     *xlat_output++ = 0xC3;

   128 }

   130 /**

   131  * Translate a single instruction. Delayed branches are handled specially

   132  * by translating both branch and delayed instruction as a single unit (as

   133  *

   134  *

   135  * @return true if the instruction marks the end of a basic block

   136  * (eg a branch or

   137  */

   138 uint32_t sh4_x86_translate_instruction( uint32_t pc )

   139 {

   140     uint16_t ir = sh4_read_word( pc );

   142         switch( (ir&0xF000) >> 12 ) {

   143             case 0x0:

   144                 switch( ir&0xF ) {

   145                     case 0x2:

   146                         switch( (ir&0x80) >> 7 ) {

   147                             case 0x0:

   148                                 switch( (ir&0x70) >> 4 ) {

   149                                     case 0x0:

   150                                         { /* STC SR, Rn */

   151                                         uint32_t Rn = ((ir>>8)&0xF);

   152                                         /* TODO */

   153                                         }

   154                                         break;

   155                                     case 0x1:

   156                                         { /* STC GBR, Rn */

   157                                         uint32_t Rn = ((ir>>8)&0xF);

   158                                         load_spreg( R_EAX, R_GBR );

   159                                         store_reg( R_EAX, Rn );

   160                                         }

   161                                         break;

   162                                     case 0x2:

   163                                         { /* STC VBR, Rn */

   164                                         uint32_t Rn = ((ir>>8)&0xF);

   165                                         load_spreg( R_EAX, R_VBR );

   166                                         store_reg( R_EAX, Rn );

   167                                         }

   168                                         break;

   169                                     case 0x3:

   170                                         { /* STC SSR, Rn */

   171                                         uint32_t Rn = ((ir>>8)&0xF);

   172                                         load_spreg( R_EAX, R_SSR );

   173                                         store_reg( R_EAX, Rn );

   174                                         }

   175                                         break;

   176                                     case 0x4:

   177                                         { /* STC SPC, Rn */

   178                                         uint32_t Rn = ((ir>>8)&0xF);

   179                                         load_spreg( R_EAX, R_SPC );

   180                                         store_reg( R_EAX, Rn );

   181                                         }

   182                                         break;

   183                                     default:

   184                                         UNDEF();

   185                                         break;

   186                                 }

   187                                 break;

   188                             case 0x1:

   189                                 { /* STC Rm_BANK, Rn */

   190                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   191                                 /* TODO */

   192                                 }

   193                                 break;

   194                         }

   195                         break;

   196                     case 0x3:

   197                         switch( (ir&0xF0) >> 4 ) {

   198                             case 0x0:

   199                                 { /* BSRF Rn */

   200                                 uint32_t Rn = ((ir>>8)&0xF);

   201                                 }

   202                                 break;

   203                             case 0x2:

   204                                 { /* BRAF Rn */

   205                                 uint32_t Rn = ((ir>>8)&0xF);

   206                                 }

   207                                 break;

   208                             case 0x8:

   209                                 { /* PREF @Rn */

   210                                 uint32_t Rn = ((ir>>8)&0xF);

   211                                 }

   212                                 break;

   213                             case 0x9:

   214                                 { /* OCBI @Rn */

   215                                 uint32_t Rn = ((ir>>8)&0xF);

   216                                 }

   217                                 break;

   218                             case 0xA:

   219                                 { /* OCBP @Rn */

   220                                 uint32_t Rn = ((ir>>8)&0xF);

   221                                 }

   222                                 break;

   223                             case 0xB:

   224                                 { /* OCBWB @Rn */

   225                                 uint32_t Rn = ((ir>>8)&0xF);

   226                                 }

   227                                 break;

   228                             case 0xC:

   229                                 { /* MOVCA.L R0, @Rn */

   230                                 uint32_t Rn = ((ir>>8)&0xF);

   231                                 load_reg( R_EAX, 0 );

   232                                 load_reg( R_ECX, Rn );

   233                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   234                                 }

   235                                 break;

   236                             default:

   237                                 UNDEF();

   238                                 break;

   239                         }

   240                         break;

   241                     case 0x4:

   242                         { /* MOV.B Rm, @(R0, Rn) */

   243                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   244                         load_reg( R_EAX, 0 );

   245                         load_reg( R_ECX, Rn );

   246                         ADD_r32_r32( R_EAX, R_ECX );

   247                         load_reg( R_EAX, Rm );

   248                         MEM_WRITE_BYTE( R_ECX, R_EAX );

   249                         }

   250                         break;

   251                     case 0x5:

   252                         { /* MOV.W Rm, @(R0, Rn) */

   253                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   254                         load_reg( R_EAX, 0 );

   255                         load_reg( R_ECX, Rn );

   256                         ADD_r32_r32( R_EAX, R_ECX );

   257                         load_reg( R_EAX, Rm );

   258                         MEM_WRITE_WORD( R_ECX, R_EAX );

   259                         }

   260                         break;

   261                     case 0x6:

   262                         { /* MOV.L Rm, @(R0, Rn) */

   263                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   264                         load_reg( R_EAX, 0 );

   265                         load_reg( R_ECX, Rn );

   266                         ADD_r32_r32( R_EAX, R_ECX );

   267                         load_reg( R_EAX, Rm );

   268                         MEM_WRITE_LONG( R_ECX, R_EAX );

   269                         }

   270                         break;

   271                     case 0x7:

   272                         { /* MUL.L Rm, Rn */

   273                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   274                         load_reg( R_EAX, Rm );

   275                         load_reg( R_ECX, Rn );

   276                         MUL_r32( R_ECX );

   277                         store_spreg( R_EAX, R_MACL );

   278                         }

   279                         break;

   280                     case 0x8:

   281                         switch( (ir&0xFF0) >> 4 ) {

   282                             case 0x0:

   283                                 { /* CLRT */

   284                                 }

   285                                 break;

   286                             case 0x1:

   287                                 { /* SETT */

   288                                 }

   289                                 break;

   290                             case 0x2:

   291                                 { /* CLRMAC */

   292                                 }

   293                                 break;

   294                             case 0x3:

   295                                 { /* LDTLB */

   296                                 }

   297                                 break;

   298                             case 0x4:

   299                                 { /* CLRS */

   300                                 }

   301                                 break;

   302                             case 0x5:

   303                                 { /* SETS */

   304                                 }

   305                                 break;

   306                             default:

   307                                 UNDEF();

   308                                 break;

   309                         }

   310                         break;

   311                     case 0x9:

   312                         switch( (ir&0xF0) >> 4 ) {

   313                             case 0x0:

   314                                 { /* NOP */

   315                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */

   316                                 }

   317                                 break;

   318                             case 0x1:

   319                                 { /* DIV0U */

   320                                 XOR_r32_r32( R_EAX, R_EAX );

   321                                 store_spreg( R_EAX, R_Q );

   322                                 store_spreg( R_EAX, R_M );

   323                                 store_spreg( R_EAX, R_T );

   324                                 }

   325                                 break;

   326                             case 0x2:

   327                                 { /* MOVT Rn */

   328                                 uint32_t Rn = ((ir>>8)&0xF);

   329                                 load_spreg( R_EAX, R_T );

   330                                 store_reg( R_EAX, Rn );

   331                                 }

   332                                 break;

   333                             default:

   334                                 UNDEF();

   335                                 break;

   336                         }

   337                         break;

   338                     case 0xA:

   339                         switch( (ir&0xF0) >> 4 ) {

   340                             case 0x0:

   341                                 { /* STS MACH, Rn */

   342                                 uint32_t Rn = ((ir>>8)&0xF);

   343                                 load_spreg( R_EAX, R_MACH );

   344                                 store_reg( R_EAX, Rn );

   345                                 }

   346                                 break;

   347                             case 0x1:

   348                                 { /* STS MACL, Rn */

   349                                 uint32_t Rn = ((ir>>8)&0xF);

   350                                 load_spreg( R_EAX, R_MACL );

   351                                 store_reg( R_EAX, Rn );

   352                                 }

   353                                 break;

   354                             case 0x2:

   355                                 { /* STS PR, Rn */

   356                                 uint32_t Rn = ((ir>>8)&0xF);

   357                                 load_spreg( R_EAX, R_PR );

   358                                 store_reg( R_EAX, Rn );

   359                                 }

   360                                 break;

   361                             case 0x3:

   362                                 { /* STC SGR, Rn */

   363                                 uint32_t Rn = ((ir>>8)&0xF);

   364                                 load_spreg( R_EAX, R_SGR );

   365                                 store_reg( R_EAX, Rn );

   366                                 }

   367                                 break;

   368                             case 0x5:

   369                                 { /* STS FPUL, Rn */

   370                                 uint32_t Rn = ((ir>>8)&0xF);

   371                                 load_spreg( R_EAX, R_FPUL );

   372                                 store_reg( R_EAX, Rn );

   373                                 }

   374                                 break;

   375                             case 0x6:

   376                                 { /* STS FPSCR, Rn */

   377                                 uint32_t Rn = ((ir>>8)&0xF);

   378                                 load_spreg( R_EAX, R_FPSCR );

   379                                 store_reg( R_EAX, Rn );

   380                                 }

   381                                 break;

   382                             case 0xF:

   383                                 { /* STC DBR, Rn */

   384                                 uint32_t Rn = ((ir>>8)&0xF);

   385                                 load_spreg( R_EAX, R_DBR );

   386                                 store_reg( R_EAX, Rn );

   387                                 }

   388                                 break;

   389                             default:

   390                                 UNDEF();

   391                                 break;

   392                         }

   393                         break;

   394                     case 0xB:

   395                         switch( (ir&0xFF0) >> 4 ) {

   396                             case 0x0:

   397                                 { /* RTS */

   398                                 }

   399                                 break;

   400                             case 0x1:

   401                                 { /* SLEEP */

   402                                 }

   403                                 break;

   404                             case 0x2:

   405                                 { /* RTE */

   406                                 }

   407                                 break;

   408                             default:

   409                                 UNDEF();

   410                                 break;

   411                         }

   412                         break;

   413                     case 0xC:

   414                         { /* MOV.B @(R0, Rm), Rn */

   415                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   416                         load_reg( R_EAX, 0 );

   417                         load_reg( R_ECX, Rm );

   418                         ADD_r32_r32( R_EAX, R_ECX );

   419                         MEM_READ_BYTE( R_ECX, R_EAX );

   420                         store_reg( R_EAX, Rn );

   421                         }

   422                         break;

   423                     case 0xD:

   424                         { /* MOV.W @(R0, Rm), Rn */

   425                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   426                         load_reg( R_EAX, 0 );

   427                         load_reg( R_ECX, Rm );

   428                         ADD_r32_r32( R_EAX, R_ECX );

   429                         MEM_READ_WORD( R_ECX, R_EAX );

   430                         store_reg( R_EAX, Rn );

   431                         }

   432                         break;

   433                     case 0xE:

   434                         { /* MOV.L @(R0, Rm), Rn */

   435                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   436                         load_reg( R_EAX, 0 );

   437                         load_reg( R_ECX, Rm );

   438                         ADD_r32_r32( R_EAX, R_ECX );

   439                         MEM_READ_LONG( R_ECX, R_EAX );

   440                         store_reg( R_EAX, Rn );

   441                         }

   442                         break;

   443                     case 0xF:

   444                         { /* MAC.L @Rm+, @Rn+ */

   445                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   446                         }

   447                         break;

   448                     default:

   449                         UNDEF();

   450                         break;

   451                 }

   452                 break;

   453             case 0x1:

   454                 { /* MOV.L Rm, @(disp, Rn) */

   455                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   456                 load_reg( R_ECX, Rn );

   457                 load_reg( R_EAX, Rm );

   458                 ADD_imm32_r32( disp, R_ECX );

   459                 MEM_WRITE_LONG( R_ECX, R_EAX );

   460                 }

   461                 break;

   462             case 0x2:

   463                 switch( ir&0xF ) {

   464                     case 0x0:

   465                         { /* MOV.B Rm, @Rn */

   466                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   467                         load_reg( R_EAX, Rm );

   468                         load_reg( R_ECX, Rn );

   469                         MEM_WRITE_BYTE( R_ECX, R_EAX );

   470                         }

   471                         break;

   472                     case 0x1:

   473                         { /* MOV.W Rm, @Rn */

   474                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   475                         load_reg( R_ECX, Rn );

   476                         MEM_READ_WORD( R_ECX, R_EAX );

   477                         store_reg( R_EAX, Rn );

   478                         }

   479                         break;

   480                     case 0x2:

   481                         { /* MOV.L Rm, @Rn */

   482                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   483                         load_reg( R_EAX, Rm );

   484                         load_reg( R_ECX, Rn );

   485                         MEM_WRITE_LONG( R_ECX, R_EAX );

   486                         }

   487                         break;

   488                     case 0x4:

   489                         { /* MOV.B Rm, @-Rn */

   490                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   491                         load_reg( R_EAX, Rm );

   492                         load_reg( R_ECX, Rn );

   493                         ADD_imm8s_r32( -1, Rn );

   494                         store_reg( R_ECX, Rn );

   495                         MEM_WRITE_BYTE( R_ECX, R_EAX );

   496                         }

   497                         break;

   498                     case 0x5:

   499                         { /* MOV.W Rm, @-Rn */

   500                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   501                         load_reg( R_ECX, Rn );

   502                         load_reg( R_EAX, Rm );

   503                         ADD_imm8s_r32( -2, R_ECX );

   504                         MEM_WRITE_WORD( R_ECX, R_EAX );

   505                         }

   506                         break;

   507                     case 0x6:

   508                         { /* MOV.L Rm, @-Rn */

   509                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   510                         load_reg( R_EAX, Rm );

   511                         load_reg( R_ECX, Rn );

   512                         ADD_imm8s_r32( -4, R_ECX );

   513                         store_reg( R_ECX, Rn );

   514                         MEM_WRITE_LONG( R_ECX, R_EAX );

   515                         }

   516                         break;

   517                     case 0x7:

   518                         { /* DIV0S Rm, Rn */

   519                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   520                         load_reg( R_EAX, Rm );

   521                         load_reg( R_ECX, Rm );

   522                         SHR_imm8_r32( 31, R_EAX );

   523                         SHR_imm8_r32( 31, R_ECX );

   524                         store_spreg( R_EAX, R_M );

   525                         store_spreg( R_ECX, R_Q );

   526                         CMP_r32_r32( R_EAX, R_ECX );

   527                         SETE_t();

   528                         }

   529                         break;

   530                     case 0x8:

   531                         { /* TST Rm, Rn */

   532                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   533                         load_reg( R_EAX, Rm );

   534                         load_reg( R_ECX, Rn );

   535                         TEST_r32_r32( R_EAX, R_ECX );

   536                         SETE_t();

   537                         }

   538                         break;

   539                     case 0x9:

   540                         { /* AND Rm, Rn */

   541                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   542                         load_reg( R_EAX, Rm );

   543                         load_reg( R_ECX, Rn );

   544                         AND_r32_r32( R_EAX, R_ECX );

   545                         store_reg( R_ECX, Rn );

   546                         }

   547                         break;

   548                     case 0xA:

   549                         { /* XOR Rm, Rn */

   550                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   551                         load_reg( R_EAX, Rm );

   552                         load_reg( R_ECX, Rn );

   553                         XOR_r32_r32( R_EAX, R_ECX );

   554                         store_reg( R_ECX, Rn );

   555                         }

   556                         break;

   557                     case 0xB:

   558                         { /* OR Rm, Rn */

   559                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   560                         load_reg( R_EAX, Rm );

   561                         load_reg( R_ECX, Rn );

   562                         OR_r32_r32( R_EAX, R_ECX );

   563                         store_reg( R_ECX, Rn );

   564                         }

   565                         break;

   566                     case 0xC:

   567                         { /* CMP/STR Rm, Rn */

   568                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   569                         }

   570                         break;

   571                     case 0xD:

   572                         { /* XTRCT Rm, Rn */

   573                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   574                         load_reg( R_EAX, Rm );

   575                         MOV_r32_r32( R_EAX, R_ECX );

   576                         SHR_imm8_r32( 16, R_EAX );

   577                         SHL_imm8_r32( 16, R_ECX );

   578                         OR_r32_r32( R_EAX, R_ECX );

   579                         store_reg( R_ECX, Rn );

   580                         }

   581                         break;

   582                     case 0xE:

   583                         { /* MULU.W Rm, Rn */

   584                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   585                         }

   586                         break;

   587                     case 0xF:

   588                         { /* MULS.W Rm, Rn */

   589                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   590                         }

   591                         break;

   592                     default:

   593                         UNDEF();

   594                         break;

   595                 }

   596                 break;

   597             case 0x3:

   598                 switch( ir&0xF ) {

   599                     case 0x0:

   600                         { /* CMP/EQ Rm, Rn */

   601                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   602                         load_reg( R_EAX, Rm );

   603                         load_reg( R_ECX, Rn );

   604                         CMP_r32_r32( R_EAX, R_ECX );

   605                         SETE_t();

   606                         }

   607                         break;

   608                     case 0x2:

   609                         { /* CMP/HS Rm, Rn */

   610                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   611                         load_reg( R_EAX, Rm );

   612                         load_reg( R_ECX, Rn );

   613                         CMP_r32_r32( R_EAX, R_ECX );

   614                         SETAE_t();

   615                         }

   616                         break;

   617                     case 0x3:

   618                         { /* CMP/GE Rm, Rn */

   619                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   620                         load_reg( R_EAX, Rm );

   621                         load_reg( R_ECX, Rn );

   622                         CMP_r32_r32( R_EAX, R_ECX );

   623                         SETGE_t();

   624                         }

   625                         break;

   626                     case 0x4:

   627                         { /* DIV1 Rm, Rn */

   628                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   629                         }

   630                         break;

   631                     case 0x5:

   632                         { /* DMULU.L Rm, Rn */

   633                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   634                         load_reg( R_EAX, Rm );

   635                         load_reg( R_ECX, Rn );

   636                         MUL_r32(R_ECX);

   637                         store_spreg( R_EDX, R_MACH );

   638                         store_spreg( R_EAX, R_MACL );

   639                         }

   640                         break;

   641                     case 0x6:

   642                         { /* CMP/HI Rm, Rn */

   643                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   644                         load_reg( R_EAX, Rm );

   645                         load_reg( R_ECX, Rn );

   646                         CMP_r32_r32( R_EAX, R_ECX );

   647                         SETA_t();

   648                         }

   649                         break;

   650                     case 0x7:

   651                         { /* CMP/GT Rm, Rn */

   652                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   653                         load_reg( R_EAX, Rm );

   654                         load_reg( R_ECX, Rn );

   655                         CMP_r32_r32( R_EAX, R_ECX );

   656                         SETG_t();

   657                         }

   658                         break;

   659                     case 0x8:

   660                         { /* SUB Rm, Rn */

   661                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   662                         load_reg( R_EAX, Rm );

   663                         load_reg( R_ECX, Rn );

   664                         SUB_r32_r32( R_EAX, R_ECX );

   665                         store_reg( R_ECX, Rn );

   666                         }

   667                         break;

   668                     case 0xA:

   669                         { /* SUBC Rm, Rn */

   670                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   671                         load_reg( R_EAX, Rm );

   672                         load_reg( R_ECX, Rn );

   673                         LDC_t();

   674                         SBB_r32_r32( R_EAX, R_ECX );

   675                         store_reg( R_ECX, Rn );

   676                         }

   677                         break;

   678                     case 0xB:

   679                         { /* SUBV Rm, Rn */

   680                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   681                         load_reg( R_EAX, Rm );

   682                         load_reg( R_ECX, Rn );

   683                         SUB_r32_r32( R_EAX, R_ECX );

   684                         store_reg( R_ECX, Rn );

   685                         SETO_t();

   686                         }

   687                         break;

   688                     case 0xC:

   689                         { /* ADD Rm, Rn */

   690                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   691                         load_reg( R_EAX, Rm );

   692                         load_reg( R_ECX, Rn );

   693                         ADD_r32_r32( R_EAX, R_ECX );

   694                         store_reg( R_ECX, Rn );

   695                         }

   696                         break;

   697                     case 0xD:

   698                         { /* DMULS.L Rm, Rn */

   699                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   700                         load_reg( R_EAX, Rm );

   701                         load_reg( R_ECX, Rn );

   702                         IMUL_r32(R_ECX);

   703                         store_spreg( R_EDX, R_MACH );

   704                         store_spreg( R_EAX, R_MACL );

   705                         }

   706                         break;

   707                     case 0xE:

   708                         { /* ADDC Rm, Rn */

   709                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   710                         load_reg( R_EAX, Rm );

   711                         load_reg( R_ECX, Rn );

   712                         LDC_t();

   713                         ADC_r32_r32( R_EAX, R_ECX );

   714                         store_reg( R_ECX, Rn );

   715                         SETC_t();

   716                         }

   717                         break;

   718                     case 0xF:

   719                         { /* ADDV Rm, Rn */

   720                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   721                         load_reg( R_EAX, Rm );

   722                         load_reg( R_ECX, Rn );

   723                         ADD_r32_r32( R_EAX, R_ECX );

   724                         store_reg( R_ECX, Rn );

   725                         SETO_t();

   726                         }

   727                         break;

   728                     default:

   729                         UNDEF();

   730                         break;

   731                 }

   732                 break;

   733             case 0x4:

   734                 switch( ir&0xF ) {

   735                     case 0x0:

   736                         switch( (ir&0xF0) >> 4 ) {

   737                             case 0x0:

   738                                 { /* SHLL Rn */

   739                                 uint32_t Rn = ((ir>>8)&0xF);

   740                                 load_reg( R_EAX, Rn );

   741                                 SHL1_r32( R_EAX );

   742                                 store_reg( R_EAX, Rn );

   743                                 }

   744                                 break;

   745                             case 0x1:

   746                                 { /* DT Rn */

   747                                 uint32_t Rn = ((ir>>8)&0xF);

   748                                 load_reg( R_EAX, Rn );

   749                                 ADD_imm8s_r32( -1, Rn );

   750                                 store_reg( R_EAX, Rn );

   751                                 SETE_t();

   752                                 }

   753                                 break;

   754                             case 0x2:

   755                                 { /* SHAL Rn */

   756                                 uint32_t Rn = ((ir>>8)&0xF);

   757                                 load_reg( R_EAX, Rn );

   758                                 SHL1_r32( R_EAX );

   759                                 store_reg( R_EAX, Rn );

   760                                 }

   761                                 break;

   762                             default:

   763                                 UNDEF();

   764                                 break;

   765                         }

   766                         break;

   767                     case 0x1:

   768                         switch( (ir&0xF0) >> 4 ) {

   769                             case 0x0:

   770                                 { /* SHLR Rn */

   771                                 uint32_t Rn = ((ir>>8)&0xF);

   772                                 load_reg( R_EAX, Rn );

   773                                 SHR1_r32( R_EAX );

   774                                 store_reg( R_EAX, Rn );

   775                                 }

   776                                 break;

   777                             case 0x1:

   778                                 { /* CMP/PZ Rn */

   779                                 uint32_t Rn = ((ir>>8)&0xF);

   780                                 load_reg( R_EAX, Rn );

   781                                 CMP_imm8s_r32( 0, R_EAX );

   782                                 SETGE_t();

   783                                 }

   784                                 break;

   785                             case 0x2:

   786                                 { /* SHAR Rn */

   787                                 uint32_t Rn = ((ir>>8)&0xF);

   788                                 load_reg( R_EAX, Rn );

   789                                 SAR1_r32( R_EAX );

   790                                 store_reg( R_EAX, Rn );

   791                                 }

   792                                 break;

   793                             default:

   794                                 UNDEF();

   795                                 break;

   796                         }

   797                         break;

   798                     case 0x2:

   799                         switch( (ir&0xF0) >> 4 ) {

   800                             case 0x0:

   801                                 { /* STS.L MACH, @-Rn */

   802                                 uint32_t Rn = ((ir>>8)&0xF);

   803                                 load_reg( R_ECX, Rn );

   804                                 ADD_imm8s_r32( -4, Rn );

   805                                 store_reg( R_ECX, Rn );

   806                                 load_spreg( R_EAX, R_MACH );

   807                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   808                                 }

   809                                 break;

   810                             case 0x1:

   811                                 { /* STS.L MACL, @-Rn */

   812                                 uint32_t Rn = ((ir>>8)&0xF);

   813                                 load_reg( R_ECX, Rn );

   814                                 ADD_imm8s_r32( -4, Rn );

   815                                 store_reg( R_ECX, Rn );

   816                                 load_spreg( R_EAX, R_MACL );

   817                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   818                                 }

   819                                 break;

   820                             case 0x2:

   821                                 { /* STS.L PR, @-Rn */

   822                                 uint32_t Rn = ((ir>>8)&0xF);

   823                                 load_reg( R_ECX, Rn );

   824                                 ADD_imm8s_r32( -4, Rn );

   825                                 store_reg( R_ECX, Rn );

   826                                 load_spreg( R_EAX, R_PR );

   827                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   828                                 }

   829                                 break;

   830                             case 0x3:

   831                                 { /* STC.L SGR, @-Rn */

   832                                 uint32_t Rn = ((ir>>8)&0xF);

   833                                 load_reg( R_ECX, Rn );

   834                                 ADD_imm8s_r32( -4, Rn );

   835                                 store_reg( R_ECX, Rn );

   836                                 load_spreg( R_EAX, R_SGR );

   837                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   838                                 }

   839                                 break;

   840                             case 0x5:

   841                                 { /* STS.L FPUL, @-Rn */

   842                                 uint32_t Rn = ((ir>>8)&0xF);

   843                                 load_reg( R_ECX, Rn );

   844                                 ADD_imm8s_r32( -4, Rn );

   845                                 store_reg( R_ECX, Rn );

   846                                 load_spreg( R_EAX, R_FPUL );

   847                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   848                                 }

   849                                 break;

   850                             case 0x6:

   851                                 { /* STS.L FPSCR, @-Rn */

   852                                 uint32_t Rn = ((ir>>8)&0xF);

   853                                 load_reg( R_ECX, Rn );

   854                                 ADD_imm8s_r32( -4, Rn );

   855                                 store_reg( R_ECX, Rn );

   856                                 load_spreg( R_EAX, R_FPSCR );

   857                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   858                                 }

   859                                 break;

   860                             case 0xF:

   861                                 { /* STC.L DBR, @-Rn */

   862                                 uint32_t Rn = ((ir>>8)&0xF);

   863                                 load_reg( R_ECX, Rn );

   864                                 ADD_imm8s_r32( -4, Rn );

   865                                 store_reg( R_ECX, Rn );

   866                                 load_spreg( R_EAX, R_DBR );

   867                                 MEM_WRITE_LONG( R_ECX, R_EAX );

   868                                 }

   869                                 break;

   870                             default:

   871                                 UNDEF();

   872                                 break;

   873                         }

   874                         break;

   875                     case 0x3:

   876                         switch( (ir&0x80) >> 7 ) {

   877                             case 0x0:

   878                                 switch( (ir&0x70) >> 4 ) {

   879                                     case 0x0:

   880                                         { /* STC.L SR, @-Rn */

   881                                         uint32_t Rn = ((ir>>8)&0xF);

   882                                         /* TODO */

   883                                         }

   884                                         break;

   885                                     case 0x1:

   886                                         { /* STC.L GBR, @-Rn */

   887                                         uint32_t Rn = ((ir>>8)&0xF);

   888                                         load_reg( R_ECX, Rn );

   889                                         ADD_imm8s_r32( -4, Rn );

   890                                         store_reg( R_ECX, Rn );

   891                                         load_spreg( R_EAX, R_GBR );

   892                                         MEM_WRITE_LONG( R_ECX, R_EAX );

   893                                         }

   894                                         break;

   895                                     case 0x2:

   896                                         { /* STC.L VBR, @-Rn */

   897                                         uint32_t Rn = ((ir>>8)&0xF);

   898                                         load_reg( R_ECX, Rn );

   899                                         ADD_imm8s_r32( -4, Rn );

   900                                         store_reg( R_ECX, Rn );

   901                                         load_spreg( R_EAX, R_VBR );

   902                                         MEM_WRITE_LONG( R_ECX, R_EAX );

   903                                         }

   904                                         break;

   905                                     case 0x3:

   906                                         { /* STC.L SSR, @-Rn */

   907                                         uint32_t Rn = ((ir>>8)&0xF);

   908                                         load_reg( R_ECX, Rn );

   909                                         ADD_imm8s_r32( -4, Rn );

   910                                         store_reg( R_ECX, Rn );

   911                                         load_spreg( R_EAX, R_SSR );

   912                                         MEM_WRITE_LONG( R_ECX, R_EAX );

   913                                         }

   914                                         break;

   915                                     case 0x4:

   916                                         { /* STC.L SPC, @-Rn */

   917                                         uint32_t Rn = ((ir>>8)&0xF);

   918                                         load_reg( R_ECX, Rn );

   919                                         ADD_imm8s_r32( -4, Rn );

   920                                         store_reg( R_ECX, Rn );

   921                                         load_spreg( R_EAX, R_SPC );

   922                                         MEM_WRITE_LONG( R_ECX, R_EAX );

   923                                         }

   924                                         break;

   925                                     default:

   926                                         UNDEF();

   927                                         break;

   928                                 }

   929                                 break;

   930                             case 0x1:

   931                                 { /* STC.L Rm_BANK, @-Rn */

   932                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   933                                 }

   934                                 break;

   935                         }

   936                         break;

   937                     case 0x4:

   938                         switch( (ir&0xF0) >> 4 ) {

   939                             case 0x0:

   940                                 { /* ROTL Rn */

   941                                 uint32_t Rn = ((ir>>8)&0xF);

   942                                 load_reg( R_EAX, Rn );

   943                                 ROL1_r32( R_EAX );

   944                                 store_reg( R_EAX, Rn );

   945                                 SETC_t();

   946                                 }

   947                                 break;

   948                             case 0x2:

   949                                 { /* ROTCL Rn */

   950                                 uint32_t Rn = ((ir>>8)&0xF);

   951                                 load_reg( R_EAX, Rn );

   952                                 LDC_t();

   953                                 RCL1_r32( R_EAX );

   954                                 store_reg( R_EAX, Rn );

   955                                 SETC_t();

   956                                 }

   957                                 break;

   958                             default:

   959                                 UNDEF();

   960                                 break;

   961                         }

   962                         break;

   963                     case 0x5:

   964                         switch( (ir&0xF0) >> 4 ) {

   965                             case 0x0:

   966                                 { /* ROTR Rn */

   967                                 uint32_t Rn = ((ir>>8)&0xF);

   968                                 load_reg( R_EAX, Rn );

   969                                 ROR1_r32( R_EAX );

   970                                 store_reg( R_EAX, Rn );

   971                                 SETC_t();

   972                                 }

   973                                 break;

   974                             case 0x1:

   975                                 { /* CMP/PL Rn */

   976                                 uint32_t Rn = ((ir>>8)&0xF);

   977                                 load_reg( R_EAX, Rn );

   978                                 CMP_imm8s_r32( 0, R_EAX );

   979                                 SETG_t();

   980                                 }

   981                                 break;

   982                             case 0x2:

   983                                 { /* ROTCR Rn */

   984                                 uint32_t Rn = ((ir>>8)&0xF);

   985                                 load_reg( R_EAX, Rn );

   986                                 LDC_t();

   987                                 RCR1_r32( R_EAX );

   988                                 store_reg( R_EAX, Rn );

   989                                 SETC_t();

   990                                 }

   991                                 break;

   992                             default:

   993                                 UNDEF();

   994                                 break;

   995                         }

   996                         break;

   997                     case 0x6:

   998                         switch( (ir&0xF0) >> 4 ) {

   999                             case 0x0:

  1000                                 { /* LDS.L @Rm+, MACH */

  1001                                 uint32_t Rm = ((ir>>8)&0xF);

  1002                                 load_reg( R_EAX, Rm );

  1003                                 MOV_r32_r32( R_EAX, R_ECX );

  1004                                 ADD_imm8s_r32( 4, R_EAX );

  1005                                 store_reg( R_EAX, Rm );

  1006                                 MEM_READ_LONG( R_ECX, R_EAX );

  1007                                 store_spreg( R_EAX, R_MACH );

  1008                                 }

  1009                                 break;

  1010                             case 0x1:

  1011                                 { /* LDS.L @Rm+, MACL */

  1012                                 uint32_t Rm = ((ir>>8)&0xF);

  1013                                 load_reg( R_EAX, Rm );

  1014                                 MOV_r32_r32( R_EAX, R_ECX );

  1015                                 ADD_imm8s_r32( 4, R_EAX );

  1016                                 store_reg( R_EAX, Rm );

  1017                                 MEM_READ_LONG( R_ECX, R_EAX );

  1018                                 store_spreg( R_EAX, R_MACL );

  1019                                 }

  1020                                 break;

  1021                             case 0x2:

  1022                                 { /* LDS.L @Rm+, PR */

  1023                                 uint32_t Rm = ((ir>>8)&0xF);

  1024                                 load_reg( R_EAX, Rm );

  1025                                 MOV_r32_r32( R_EAX, R_ECX );

  1026                                 ADD_imm8s_r32( 4, R_EAX );

  1027                                 store_reg( R_EAX, Rm );

  1028                                 MEM_READ_LONG( R_ECX, R_EAX );

  1029                                 store_spreg( R_EAX, R_PR );

  1030                                 }

  1031                                 break;

  1032                             case 0x3:

  1033                                 { /* LDC.L @Rm+, SGR */

  1034                                 uint32_t Rm = ((ir>>8)&0xF);

  1035                                 load_reg( R_EAX, Rm );

  1036                                 MOV_r32_r32( R_EAX, R_ECX );

  1037                                 ADD_imm8s_r32( 4, R_EAX );

  1038                                 store_reg( R_EAX, Rm );

  1039                                 MEM_READ_LONG( R_ECX, R_EAX );

  1040                                 store_spreg( R_EAX, R_SGR );

  1041                                 }

  1042                                 break;

  1043                             case 0x5:

  1044                                 { /* LDS.L @Rm+, FPUL */

  1045                                 uint32_t Rm = ((ir>>8)&0xF);

  1046                                 load_reg( R_EAX, Rm );

  1047                                 MOV_r32_r32( R_EAX, R_ECX );

  1048                                 ADD_imm8s_r32( 4, R_EAX );

  1049                                 store_reg( R_EAX, Rm );

  1050                                 MEM_READ_LONG( R_ECX, R_EAX );

  1051                                 store_spreg( R_EAX, R_FPUL );

  1052                                 }

  1053                                 break;

  1054                             case 0x6:

  1055                                 { /* LDS.L @Rm+, FPSCR */

  1056                                 uint32_t Rm = ((ir>>8)&0xF);

  1057                                 load_reg( R_EAX, Rm );

  1058                                 MOV_r32_r32( R_EAX, R_ECX );

  1059                                 ADD_imm8s_r32( 4, R_EAX );

  1060                                 store_reg( R_EAX, Rm );

  1061                                 MEM_READ_LONG( R_ECX, R_EAX );

  1062                                 store_spreg( R_EAX, R_FPSCR );

  1063                                 }

  1064                                 break;

  1065                             case 0xF:

  1066                                 { /* LDC.L @Rm+, DBR */

  1067                                 uint32_t Rm = ((ir>>8)&0xF);

  1068                                 load_reg( R_EAX, Rm );

  1069                                 MOV_r32_r32( R_EAX, R_ECX );

  1070                                 ADD_imm8s_r32( 4, R_EAX );

  1071                                 store_reg( R_EAX, Rm );

  1072                                 MEM_READ_LONG( R_ECX, R_EAX );

  1073                                 store_spreg( R_EAX, R_DBR );

  1074                                 }

  1075                                 break;

  1076                             default:

  1077                                 UNDEF();

  1078                                 break;

  1079                         }

  1080                         break;

  1081                     case 0x7:

  1082                         switch( (ir&0x80) >> 7 ) {

  1083                             case 0x0:

  1084                                 switch( (ir&0x70) >> 4 ) {

  1085                                     case 0x0:

  1086                                         { /* LDC.L @Rm+, SR */

  1087                                         uint32_t Rm = ((ir>>8)&0xF);

  1088                                         }

  1089                                         break;

  1090                                     case 0x1:

  1091                                         { /* LDC.L @Rm+, GBR */

  1092                                         uint32_t Rm = ((ir>>8)&0xF);

  1093                                         load_reg( R_EAX, Rm );

  1094                                         MOV_r32_r32( R_EAX, R_ECX );

  1095                                         ADD_imm8s_r32( 4, R_EAX );

  1096                                         store_reg( R_EAX, Rm );

  1097                                         MEM_READ_LONG( R_ECX, R_EAX );

  1098                                         store_spreg( R_EAX, R_GBR );

  1099                                         }

  1100                                         break;

  1101                                     case 0x2:

  1102                                         { /* LDC.L @Rm+, VBR */

  1103                                         uint32_t Rm = ((ir>>8)&0xF);

  1104                                         load_reg( R_EAX, Rm );

  1105                                         MOV_r32_r32( R_EAX, R_ECX );

  1106                                         ADD_imm8s_r32( 4, R_EAX );

  1107                                         store_reg( R_EAX, Rm );

  1108                                         MEM_READ_LONG( R_ECX, R_EAX );

  1109                                         store_spreg( R_EAX, R_VBR );

  1110                                         }

  1111                                         break;

  1112                                     case 0x3:

  1113                                         { /* LDC.L @Rm+, SSR */

  1114                                         uint32_t Rm = ((ir>>8)&0xF);

  1115                                         load_reg( R_EAX, Rm );

  1116                                         MOV_r32_r32( R_EAX, R_ECX );

  1117                                         ADD_imm8s_r32( 4, R_EAX );

  1118                                         store_reg( R_EAX, Rm );

  1119                                         MEM_READ_LONG( R_ECX, R_EAX );

  1120                                         store_spreg( R_EAX, R_SSR );

  1121                                         }

  1122                                         break;

  1123                                     case 0x4:

  1124                                         { /* LDC.L @Rm+, SPC */

  1125                                         uint32_t Rm = ((ir>>8)&0xF);

  1126                                         load_reg( R_EAX, Rm );

  1127                                         MOV_r32_r32( R_EAX, R_ECX );

  1128                                         ADD_imm8s_r32( 4, R_EAX );

  1129                                         store_reg( R_EAX, Rm );

  1130                                         MEM_READ_LONG( R_ECX, R_EAX );

  1131                                         store_spreg( R_EAX, R_SPC );

  1132                                         }

  1133                                         break;

  1134                                     default:

  1135                                         UNDEF();

  1136                                         break;

  1137                                 }

  1138                                 break;

  1139                             case 0x1:

  1140                                 { /* LDC.L @Rm+, Rn_BANK */

  1141                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1142                                 }

  1143                                 break;

  1144                         }

  1145                         break;

  1146                     case 0x8:

  1147                         switch( (ir&0xF0) >> 4 ) {

  1148                             case 0x0:

  1149                                 { /* SHLL2 Rn */

  1150                                 uint32_t Rn = ((ir>>8)&0xF);

  1151                                 load_reg( R_EAX, Rn );

  1152                                 SHL_imm8_r32( 2, R_EAX );

  1153                                 store_reg( R_EAX, Rn );

  1154                                 }

  1155                                 break;

  1156                             case 0x1:

  1157                                 { /* SHLL8 Rn */

  1158                                 uint32_t Rn = ((ir>>8)&0xF);

  1159                                 load_reg( R_EAX, Rn );

  1160                                 SHL_imm8_r32( 8, R_EAX );

  1161                                 store_reg( R_EAX, Rn );

  1162                                 }

  1163                                 break;

  1164                             case 0x2:

  1165                                 { /* SHLL16 Rn */

  1166                                 uint32_t Rn = ((ir>>8)&0xF);

  1167                                 load_reg( R_EAX, Rn );

  1168                                 SHL_imm8_r32( 16, R_EAX );

  1169                                 store_reg( R_EAX, Rn );

  1170                                 }

  1171                                 break;

  1172                             default:

  1173                                 UNDEF();

  1174                                 break;

  1175                         }

  1176                         break;

  1177                     case 0x9:

  1178                         switch( (ir&0xF0) >> 4 ) {

  1179                             case 0x0:

  1180                                 { /* SHLR2 Rn */

  1181                                 uint32_t Rn = ((ir>>8)&0xF);

  1182                                 load_reg( R_EAX, Rn );

  1183                                 SHR_imm8_r32( 2, R_EAX );

  1184                                 store_reg( R_EAX, Rn );

  1185                                 }

  1186                                 break;

  1187                             case 0x1:

  1188                                 { /* SHLR8 Rn */

  1189                                 uint32_t Rn = ((ir>>8)&0xF);

  1190                                 load_reg( R_EAX, Rn );

  1191                                 SHR_imm8_r32( 8, R_EAX );

  1192                                 store_reg( R_EAX, Rn );

  1193                                 }

  1194                                 break;

  1195                             case 0x2:

  1196                                 { /* SHLR16 Rn */

  1197                                 uint32_t Rn = ((ir>>8)&0xF);

  1198                                 load_reg( R_EAX, Rn );

  1199                                 SHR_imm8_r32( 16, R_EAX );

  1200                                 store_reg( R_EAX, Rn );

  1201                                 }

  1202                                 break;

  1203                             default:

  1204                                 UNDEF();

  1205                                 break;

  1206                         }

  1207                         break;

  1208                     case 0xA:

  1209                         switch( (ir&0xF0) >> 4 ) {

  1210                             case 0x0:

  1211                                 { /* LDS Rm, MACH */

  1212                                 uint32_t Rm = ((ir>>8)&0xF);

  1213                                 load_reg( R_EAX, Rm );

  1214                                 store_spreg( R_EAX, R_MACH );

  1215                                 }

  1216                                 break;

  1217                             case 0x1:

  1218                                 { /* LDS Rm, MACL */

  1219                                 uint32_t Rm = ((ir>>8)&0xF);

  1220                                 load_reg( R_EAX, Rm );

  1221                                 store_spreg( R_EAX, R_MACL );

  1222                                 }

  1223                                 break;

  1224                             case 0x2:

  1225                                 { /* LDS Rm, PR */

  1226                                 uint32_t Rm = ((ir>>8)&0xF);

  1227                                 load_reg( R_EAX, Rm );

  1228                                 store_spreg( R_EAX, R_PR );

  1229                                 }

  1230                                 break;

  1231                             case 0x3:

  1232                                 { /* LDC Rm, SGR */

  1233                                 uint32_t Rm = ((ir>>8)&0xF);

  1234                                 load_reg( R_EAX, Rm );

  1235                                 store_spreg( R_EAX, R_SGR );

  1236                                 }

  1237                                 break;

  1238                             case 0x5:

  1239                                 { /* LDS Rm, FPUL */

  1240                                 uint32_t Rm = ((ir>>8)&0xF);

  1241                                 load_reg( R_EAX, Rm );

  1242                                 store_spreg( R_EAX, R_FPUL );

  1243                                 }

  1244                                 break;

  1245                             case 0x6:

  1246                                 { /* LDS Rm, FPSCR */

  1247                                 uint32_t Rm = ((ir>>8)&0xF);

  1248                                 load_reg( R_EAX, Rm );

  1249                                 store_spreg( R_EAX, R_FPSCR );

  1250                                 }

  1251                                 break;

  1252                             case 0xF:

  1253                                 { /* LDC Rm, DBR */

  1254                                 uint32_t Rm = ((ir>>8)&0xF);

  1255                                 load_reg( R_EAX, Rm );

  1256                                 store_spreg( R_EAX, R_DBR );

  1257                                 }

  1258                                 break;

  1259                             default:

  1260                                 UNDEF();

  1261                                 break;

  1262                         }

  1263                         break;

  1264                     case 0xB:

  1265                         switch( (ir&0xF0) >> 4 ) {

  1266                             case 0x0:

  1267                                 { /* JSR @Rn */

  1268                                 uint32_t Rn = ((ir>>8)&0xF);

  1269                                 }

  1270                                 break;

  1271                             case 0x1:

  1272                                 { /* TAS.B @Rn */

  1273                                 uint32_t Rn = ((ir>>8)&0xF);

  1274                                 load_reg( R_ECX, Rn );

  1275                                 MEM_READ_BYTE( R_ECX, R_EAX );

  1276                                 TEST_r8_r8( R_AL, R_AL );

  1277                                 SETE_t();

  1278                                 OR_imm8_r8( 0x80, R_AL );

  1279                                 MEM_WRITE_BYTE( R_ECX, R_EAX );

  1280                                 }

  1281                                 break;

  1282                             case 0x2:

  1283                                 { /* JMP @Rn */

  1284                                 uint32_t Rn = ((ir>>8)&0xF);

  1285                                 }

  1286                                 break;

  1287                             default:

  1288                                 UNDEF();

  1289                                 break;

  1290                         }

  1291                         break;

  1292                     case 0xC:

  1293                         { /* SHAD Rm, Rn */

  1294                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1295                         /* Annoyingly enough, not directly convertible */

  1296                         load_reg( R_EAX, Rn );

  1297                         load_reg( R_ECX, Rm );

  1298                         CMP_imm32_r32( 0, R_ECX );

  1299                         JAE_rel8(9);

  1301                         NEG_r32( R_ECX );      // 2

  1302                         AND_imm8_r8( 0x1F, R_CL ); // 3

  1303                         SAR_r32_CL( R_EAX );       // 2

  1304                         JMP_rel8(5);               // 2

  1306                         AND_imm8_r8( 0x1F, R_CL ); // 3

  1307                         SHL_r32_CL( R_EAX );       // 2

  1309                         store_reg( R_EAX, Rn );

  1310                         }

  1311                         break;

  1312                     case 0xD:

  1313                         { /* SHLD Rm, Rn */

  1314                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1315                         }

  1316                         break;

  1317                     case 0xE:

  1318                         switch( (ir&0x80) >> 7 ) {

  1319                             case 0x0:

  1320                                 switch( (ir&0x70) >> 4 ) {

  1321                                     case 0x0:

  1322                                         { /* LDC Rm, SR */

  1323                                         uint32_t Rm = ((ir>>8)&0xF);

  1324                                         /* We need to be a little careful about SR */

  1325                                         }

  1326                                         break;

  1327                                     case 0x1:

  1328                                         { /* LDC Rm, GBR */

  1329                                         uint32_t Rm = ((ir>>8)&0xF);

  1330                                         load_reg( R_EAX, Rm );

  1331                                         store_spreg( R_EAX, R_GBR );

  1332                                         }

  1333                                         break;

  1334                                     case 0x2:

  1335                                         { /* LDC Rm, VBR */

  1336                                         uint32_t Rm = ((ir>>8)&0xF);

  1337                                         load_reg( R_EAX, Rm );

  1338                                         store_spreg( R_EAX, R_VBR );

  1339                                         }

  1340                                         break;

  1341                                     case 0x3:

  1342                                         { /* LDC Rm, SSR */

  1343                                         uint32_t Rm = ((ir>>8)&0xF);

  1344                                         load_reg( R_EAX, Rm );

  1345                                         store_spreg( R_EAX, R_SSR );

  1346                                         }

  1347                                         break;

  1348                                     case 0x4:

  1349                                         { /* LDC Rm, SPC */

  1350                                         uint32_t Rm = ((ir>>8)&0xF);

  1351                                         load_reg( R_EAX, Rm );

  1352                                         store_spreg( R_EAX, R_SPC );

  1353                                         }

  1354                                         break;

  1355                                     default:

  1356                                         UNDEF();

  1357                                         break;

  1358                                 }

  1359                                 break;

  1360                             case 0x1:

  1361                                 { /* LDC Rm, Rn_BANK */

  1362                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1363                                 }

  1364                                 break;

  1365                         }

  1366                         break;

  1367                     case 0xF:

  1368                         { /* MAC.W @Rm+, @Rn+ */

  1369                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1370                         }

  1371                         break;

  1372                 }

  1373                 break;

  1374             case 0x5:

  1375                 { /* MOV.L @(disp, Rm), Rn */

  1376                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1377                 load_reg( R_ECX, Rm );

  1378                 ADD_imm8s_r32( disp, R_ECX );

  1379                 MEM_READ_LONG( R_ECX, R_EAX );

  1380                 store_reg( R_EAX, Rn );

  1381                 }

  1382                 break;

  1383             case 0x6:

  1384                 switch( ir&0xF ) {

  1385                     case 0x0:

  1386                         { /* MOV.B @Rm, Rn */

  1387                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1388                         load_reg( R_ECX, Rm );

  1389                         MEM_READ_BYTE( R_ECX, R_EAX );

  1390                         store_reg( R_ECX, Rn );

  1391                         }

  1392                         break;

  1393                     case 0x1:

  1394                         { /* MOV.W @Rm, Rn */

  1395                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1396                         load_reg( R_ECX, Rm );

  1397                         MEM_READ_WORD( R_ECX, R_EAX );

  1398                         store_reg( R_EAX, Rn );

  1399                         }

  1400                         break;

  1401                     case 0x2:

  1402                         { /* MOV.L @Rm, Rn */

  1403                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1404                         load_reg( R_ECX, Rm );

  1405                         MEM_READ_LONG( R_ECX, R_EAX );

  1406                         store_reg( R_EAX, Rn );

  1407                         }

  1408                         break;

  1409                     case 0x3:

  1410                         { /* MOV Rm, Rn */

  1411                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1412                         load_reg( R_EAX, Rm );

  1413                         store_reg( R_EAX, Rn );

  1414                         }

  1415                         break;

  1416                     case 0x4:

  1417                         { /* MOV.B @Rm+, Rn */

  1418                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1419                         load_reg( R_ECX, Rm );

  1420                         MOV_r32_r32( R_ECX, R_EAX );

  1421                         ADD_imm8s_r32( 1, R_EAX );

  1422                         store_reg( R_EAX, Rm );

  1423                         MEM_READ_BYTE( R_ECX, R_EAX );

  1424                         store_reg( R_EAX, Rn );

  1425                         }

  1426                         break;

  1427                     case 0x5:

  1428                         { /* MOV.W @Rm+, Rn */

  1429                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1430                         load_reg( R_EAX, Rm );

  1431                         MOV_r32_r32( R_EAX, R_ECX );

  1432                         ADD_imm8s_r32( 2, R_EAX );

  1433                         store_reg( R_EAX, Rm );

  1434                         MEM_READ_WORD( R_ECX, R_EAX );

  1435                         store_reg( R_EAX, Rn );

  1436                         }

  1437                         break;

  1438                     case 0x6:

  1439                         { /* MOV.L @Rm+, Rn */

  1440                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1441                         load_reg( R_EAX, Rm );

  1442                         MOV_r32_r32( R_EAX, R_ECX );

  1443                         ADD_imm8s_r32( 4, R_EAX );

  1444                         store_reg( R_EAX, Rm );

  1445                         MEM_READ_LONG( R_ECX, R_EAX );

  1446                         store_reg( R_EAX, Rn );

  1447                         }

  1448                         break;

  1449                     case 0x7:

  1450                         { /* NOT Rm, Rn */

  1451                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1452                         load_reg( R_EAX, Rm );

  1453                         NOT_r32( R_EAX );

  1454                         store_reg( R_EAX, Rn );

  1455                         }

  1456                         break;

  1457                     case 0x8:

  1458                         { /* SWAP.B Rm, Rn */

  1459                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1460                         load_reg( R_EAX, Rm );

  1461                         XCHG_r8_r8( R_AL, R_AH );

  1462                         store_reg( R_EAX, Rn );

  1463                         }

  1464                         break;

  1465                     case 0x9:

  1466                         { /* SWAP.W Rm, Rn */

  1467                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1468                         load_reg( R_EAX, Rm );

  1469                         MOV_r32_r32( R_EAX, R_ECX );

  1470                         SHL_imm8_r32( 16, R_ECX );

  1471                         SHR_imm8_r32( 16, R_EAX );

  1472                         OR_r32_r32( R_EAX, R_ECX );

  1473                         store_reg( R_ECX, Rn );

  1474                         }

  1475                         break;

  1476                     case 0xA:

  1477                         { /* NEGC Rm, Rn */

  1478                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1479                         load_reg( R_EAX, Rm );

  1480                         XOR_r32_r32( R_ECX, R_ECX );

  1481                         LDC_t();

  1482                         SBB_r32_r32( R_EAX, R_ECX );

  1483                         store_reg( R_ECX, Rn );

  1484                         SETC_t();

  1485                         }

  1486                         break;

  1487                     case 0xB:

  1488                         { /* NEG Rm, Rn */

  1489                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1490                         load_reg( R_EAX, Rm );

  1491                         NEG_r32( R_EAX );

  1492                         store_reg( R_EAX, Rn );

  1493                         }

  1494                         break;

  1495                     case 0xC:

  1496                         { /* EXTU.B Rm, Rn */

  1497                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1498                         load_reg( R_EAX, Rm );

  1499                         MOVZX_r8_r32( R_EAX, R_EAX );

  1500                         store_reg( R_EAX, Rn );

  1501                         }

  1502                         break;

  1503                     case 0xD:

  1504                         { /* EXTU.W Rm, Rn */

  1505                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1506                         load_reg( R_EAX, Rm );

  1507                         MOVZX_r16_r32( R_EAX, R_EAX );

  1508                         store_reg( R_EAX, Rn );

  1509                         }

  1510                         break;

  1511                     case 0xE:

  1512                         { /* EXTS.B Rm, Rn */

  1513                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1514                         load_reg( R_EAX, Rm );

  1515                         MOVSX_r8_r32( R_EAX, R_EAX );

  1516                         store_reg( R_EAX, Rn );

  1517                         }

  1518                         break;

  1519                     case 0xF:

  1520                         { /* EXTS.W Rm, Rn */

  1521                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1522                         load_reg( R_EAX, Rm );

  1523                         MOVSX_r16_r32( R_EAX, R_EAX );

  1524                         store_reg( R_EAX, Rn );

  1525                         }

  1526                         break;

  1527                 }

  1528                 break;

  1529             case 0x7:

  1530                 { /* ADD #imm, Rn */

  1531                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1532                 load_reg( R_EAX, Rn );

  1533                 ADD_imm8s_r32( imm, R_EAX );

  1534                 store_reg( R_EAX, Rn );

  1535                 }

  1536                 break;

  1537             case 0x8:

  1538                 switch( (ir&0xF00) >> 8 ) {

  1539                     case 0x0:

  1540                         { /* MOV.B R0, @(disp, Rn) */

  1541                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1542                         load_reg( R_EAX, 0 );

  1543                         load_reg( R_ECX, Rn );

  1544                         ADD_imm32_r32( disp, R_ECX );

  1545                         MEM_WRITE_BYTE( R_ECX, R_EAX );

  1546                         }

  1547                         break;

  1548                     case 0x1:

  1549                         { /* MOV.W R0, @(disp, Rn) */

  1550                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1551                         load_reg( R_ECX, Rn );

  1552                         load_reg( R_EAX, 0 );

  1553                         ADD_imm32_r32( disp, R_ECX );

  1554                         MEM_WRITE_WORD( R_ECX, R_EAX );

  1555                         }

  1556                         break;

  1557                     case 0x4:

  1558                         { /* MOV.B @(disp, Rm), R0 */

  1559                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1560                         load_reg( R_ECX, Rm );

  1561                         ADD_imm32_r32( disp, R_ECX );

  1562                         MEM_READ_BYTE( R_ECX, R_EAX );

  1563                         store_reg( R_EAX, 0 );

  1564                         }

  1565                         break;

  1566                     case 0x5:

  1567                         { /* MOV.W @(disp, Rm), R0 */

  1568                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1569                         load_reg( R_ECX, Rm );

  1570                         ADD_imm32_r32( disp, R_ECX );

  1571                         MEM_READ_WORD( R_ECX, R_EAX );

  1572                         store_reg( R_EAX, 0 );

  1573                         }

  1574                         break;

  1575                     case 0x8:

  1576                         { /* CMP/EQ #imm, R0 */

  1577                         int32_t imm = SIGNEXT8(ir&0xFF);

  1578                         load_reg( R_EAX, 0 );

  1579                         CMP_imm8s_r32(imm, R_EAX);

  1580                         SETE_t();

  1581                         }

  1582                         break;

  1583                     case 0x9:

  1584                         { /* BT disp */

  1585                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1586                         /* If true, result PC += 4 + disp. else result PC = pc+2 */

  1587                           return pc + 2;

  1588                         }

  1589                         break;

  1590                     case 0xB:

  1591                         { /* BF disp */

  1592                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1593                         }

  1594                         break;

  1595                     case 0xD:

  1596                         { /* BT/S disp */

  1597                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1598                         return pc + 4;

  1599                         }

  1600                         break;

  1601                     case 0xF:

  1602                         { /* BF/S disp */

  1603                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1604                         }

  1605                         break;

  1606                     default:

  1607                         UNDEF();

  1608                         break;

  1609                 }

  1610                 break;

  1611             case 0x9:

  1612                 { /* MOV.W @(disp, PC), Rn */

  1613                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1614                 load_imm32( R_ECX, pc + disp + 4 );

  1615                 MEM_READ_WORD( R_ECX, R_EAX );

  1616                 store_reg( R_EAX, Rn );

  1617                 }

  1618                 break;

  1619             case 0xA:

  1620                 { /* BRA disp */

  1621                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1622                 }

  1623                 break;

  1624             case 0xB:

  1625                 { /* BSR disp */

  1626                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1627                 }

  1628                 break;

  1629             case 0xC:

  1630                 switch( (ir&0xF00) >> 8 ) {

  1631                     case 0x0:

  1632                         { /* MOV.B R0, @(disp, GBR) */

  1633                         uint32_t disp = (ir&0xFF);

  1634                         load_reg( R_EAX, 0 );

  1635                         load_spreg( R_ECX, R_GBR );

  1636                         ADD_imm32_r32( disp, R_ECX );

  1637                         MEM_WRITE_BYTE( R_ECX, R_EAX );

  1638                         }

  1639                         break;

  1640                     case 0x1:

  1641                         { /* MOV.W R0, @(disp, GBR) */

  1642                         uint32_t disp = (ir&0xFF)<<1;

  1643                         load_spreg( R_ECX, R_GBR );

  1644                         load_reg( R_EAX, 0 );

  1645                         ADD_imm32_r32( disp, R_ECX );

  1646                         MEM_WRITE_WORD( R_ECX, R_EAX );

  1647                         }

  1648                         break;

  1649                     case 0x2:

  1650                         { /* MOV.L R0, @(disp, GBR) */

  1651                         uint32_t disp = (ir&0xFF)<<2;

  1652                         load_spreg( R_ECX, R_GBR );

  1653                         load_reg( R_EAX, 0 );

  1654                         ADD_imm32_r32( disp, R_ECX );

  1655                         MEM_WRITE_LONG( R_ECX, R_EAX );

  1656                         }

  1657                         break;

  1658                     case 0x3:

  1659                         { /* TRAPA #imm */

  1660                         uint32_t imm = (ir&0xFF);

  1661                         }

  1662                         break;

  1663                     case 0x4:

  1664                         { /* MOV.B @(disp, GBR), R0 */

  1665                         uint32_t disp = (ir&0xFF);

  1666                         load_spreg( R_ECX, R_GBR );

  1667                         ADD_imm32_r32( disp, R_ECX );

  1668                         MEM_READ_BYTE( R_ECX, R_EAX );

  1669                         store_reg( R_EAX, 0 );

  1670                         }

  1671                         break;

  1672                     case 0x5:

  1673                         { /* MOV.W @(disp, GBR), R0 */

  1674                         uint32_t disp = (ir&0xFF)<<1;

  1675                         load_spreg( R_ECX, R_GBR );

  1676                         ADD_imm32_r32( disp, R_ECX );

  1677                         MEM_READ_WORD( R_ECX, R_EAX );

  1678                         store_reg( R_EAX, 0 );

  1679                         }

  1680                         break;

  1681                     case 0x6:

  1682                         { /* MOV.L @(disp, GBR), R0 */

  1683                         uint32_t disp = (ir&0xFF)<<2;

  1684                         load_spreg( R_ECX, R_GBR );

  1685                         ADD_imm32_r32( disp, R_ECX );

  1686                         MEM_READ_LONG( R_ECX, R_EAX );

  1687                         store_reg( R_EAX, 0 );

  1688                         }

  1689                         break;

  1690                     case 0x7:

  1691                         { /* MOVA @(disp, PC), R0 */

  1692                         uint32_t disp = (ir&0xFF)<<2;

  1693                         load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );

  1694                         store_reg( R_ECX, 0 );

  1695                         }

  1696                         break;

  1697                     case 0x8:

  1698                         { /* TST #imm, R0 */

  1699                         uint32_t imm = (ir&0xFF);

  1700                         }

  1701                         break;

  1702                     case 0x9:

  1703                         { /* AND #imm, R0 */

  1704                         uint32_t imm = (ir&0xFF);

  1705                         load_reg( R_EAX, 0 );

  1706                         AND_imm32_r32(imm, R_EAX);

  1707                         store_reg( R_EAX, 0 );

  1708                         }

  1709                         break;

  1710                     case 0xA:

  1711                         { /* XOR #imm, R0 */

  1712                         uint32_t imm = (ir&0xFF);

  1713                         load_reg( R_EAX, 0 );

  1714                         XOR_imm32_r32( imm, R_EAX );

  1715                         store_reg( R_EAX, 0 );

  1716                         }

  1717                         break;

  1718                     case 0xB:

  1719                         { /* OR #imm, R0 */

  1720                         uint32_t imm = (ir&0xFF);

  1721                         load_reg( R_EAX, 0 );

  1722                         OR_imm32_r32(imm, R_EAX);

  1723                         store_reg( R_EAX, 0 );

  1724                         }

  1725                         break;

  1726                     case 0xC:

  1727                         { /* TST.B #imm, @(R0, GBR) */

  1728                         uint32_t imm = (ir&0xFF);

  1729                         }

  1730                         break;

  1731                     case 0xD:

  1732                         { /* AND.B #imm, @(R0, GBR) */

  1733                         uint32_t imm = (ir&0xFF);

  1734                         load_reg( R_EAX, 0 );

  1735                         load_spreg( R_ECX, R_GBR );

  1736                         ADD_r32_r32( R_EAX, R_EBX );

  1737                         MEM_READ_BYTE( R_ECX, R_EAX );

  1738                         AND_imm32_r32(imm, R_ECX );

  1739                         MEM_WRITE_BYTE( R_ECX, R_EAX );

  1740                         }

  1741                         break;

  1742                     case 0xE:

  1743                         { /* XOR.B #imm, @(R0, GBR) */

  1744                         uint32_t imm = (ir&0xFF);

  1745                         load_reg( R_EAX, 0 );

  1746                         load_spreg( R_ECX, R_GBR );

  1747                         ADD_r32_r32( R_EAX, R_ECX );

  1748                         MEM_READ_BYTE( R_ECX, R_EAX );

  1749                         XOR_imm32_r32( imm, R_EAX );

  1750                         MEM_WRITE_BYTE( R_ECX, R_EAX );

  1751                         }

  1752                         break;

  1753                     case 0xF:

  1754                         { /* OR.B #imm, @(R0, GBR) */

  1755                         uint32_t imm = (ir&0xFF);

  1756                         }

  1757                         break;

  1758                 }

  1759                 break;

  1760             case 0xD:

  1761                 { /* MOV.L @(disp, PC), Rn */

  1762                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1763                 load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );

  1764                 MEM_READ_LONG( R_ECX, R_EAX );

  1765                 store_reg( R_EAX, 0 );

  1766                 }

  1767                 break;

  1768             case 0xE:

  1769                 { /* MOV #imm, Rn */

  1770                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1771                 load_imm32( R_EAX, imm );

  1772                 store_reg( R_EAX, Rn );

  1773                 }

  1774                 break;

  1775             case 0xF:

  1776                 switch( ir&0xF ) {

  1777                     case 0x0:

  1778                         { /* FADD FRm, FRn */

  1779                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1780                         }

  1781                         break;

  1782                     case 0x1:

  1783                         { /* FSUB FRm, FRn */

  1784                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1785                         }

  1786                         break;

  1787                     case 0x2:

  1788                         { /* FMUL FRm, FRn */

  1789                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1790                         }

  1791                         break;

  1792                     case 0x3:

  1793                         { /* FDIV FRm, FRn */

  1794                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1795                         }

  1796                         break;

  1797                     case 0x4:

  1798                         { /* FCMP/EQ FRm, FRn */

  1799                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1800                         }

  1801                         break;

  1802                     case 0x5:

  1803                         { /* FCMP/GT FRm, FRn */

  1804                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1805                         }

  1806                         break;

  1807                     case 0x6:

  1808                         { /* FMOV @(R0, Rm), FRn */

  1809                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1810                         }

  1811                         break;

  1812                     case 0x7:

  1813                         { /* FMOV FRm, @(R0, Rn) */

  1814                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1815                         }

  1816                         break;

  1817                     case 0x8:

  1818                         { /* FMOV @Rm, FRn */

  1819                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1820                         }

  1821                         break;

  1822                     case 0x9:

  1823                         { /* FMOV @Rm+, FRn */

  1824                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1825                         }

  1826                         break;

  1827                     case 0xA:

  1828                         { /* FMOV FRm, @Rn */

  1829                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1830                         }

  1831                         break;

  1832                     case 0xB:

  1833                         { /* FMOV FRm, @-Rn */

  1834                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1835                         }

  1836                         break;

  1837                     case 0xC:

  1838                         { /* FMOV FRm, FRn */

  1839                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1840                         }

  1841                         break;

  1842                     case 0xD:

  1843                         switch( (ir&0xF0) >> 4 ) {

  1844                             case 0x0:

  1845                                 { /* FSTS FPUL, FRn */

  1846                                 uint32_t FRn = ((ir>>8)&0xF);

  1847                                 }

  1848                                 break;

  1849                             case 0x1:

  1850                                 { /* FLDS FRm, FPUL */

  1851                                 uint32_t FRm = ((ir>>8)&0xF);

  1852                                 }

  1853                                 break;

  1854                             case 0x2:

  1855                                 { /* FLOAT FPUL, FRn */

  1856                                 uint32_t FRn = ((ir>>8)&0xF);

  1857                                 }

  1858                                 break;

  1859                             case 0x3:

  1860                                 { /* FTRC FRm, FPUL */

  1861                                 uint32_t FRm = ((ir>>8)&0xF);

  1862                                 }

  1863                                 break;

  1864                             case 0x4:

  1865                                 { /* FNEG FRn */

  1866                                 uint32_t FRn = ((ir>>8)&0xF);

  1867                                 }

  1868                                 break;

  1869                             case 0x5:

  1870                                 { /* FABS FRn */

  1871                                 uint32_t FRn = ((ir>>8)&0xF);

  1872                                 }

  1873                                 break;

  1874                             case 0x6:

  1875                                 { /* FSQRT FRn */

  1876                                 uint32_t FRn = ((ir>>8)&0xF);

  1877                                 }

  1878                                 break;

  1879                             case 0x7:

  1880                                 { /* FSRRA FRn */

  1881                                 uint32_t FRn = ((ir>>8)&0xF);

  1882                                 }

  1883                                 break;

  1884                             case 0x8:

  1885                                 { /* FLDI0 FRn */

  1886                                 uint32_t FRn = ((ir>>8)&0xF);

  1887                                 }

  1888                                 break;

  1889                             case 0x9:

  1890                                 { /* FLDI1 FRn */

  1891                                 uint32_t FRn = ((ir>>8)&0xF);

  1892                                 }

  1893                                 break;

  1894                             case 0xA:

  1895                                 { /* FCNVSD FPUL, FRn */

  1896                                 uint32_t FRn = ((ir>>8)&0xF);

  1897                                 }

  1898                                 break;

  1899                             case 0xB:

  1900                                 { /* FCNVDS FRm, FPUL */

  1901                                 uint32_t FRm = ((ir>>8)&0xF);

  1902                                 }

  1903                                 break;

  1904                             case 0xE:

  1905                                 { /* FIPR FVm, FVn */

  1906                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  1907                                 }

  1908                                 break;

  1909                             case 0xF:

  1910                                 switch( (ir&0x100) >> 8 ) {

  1911                                     case 0x0:

  1912                                         { /* FSCA FPUL, FRn */

  1913                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  1914                                         }

  1915                                         break;

  1916                                     case 0x1:

  1917                                         switch( (ir&0x200) >> 9 ) {

  1918                                             case 0x0:

  1919                                                 { /* FTRV XMTRX, FVn */

  1920                                                 uint32_t FVn = ((ir>>10)&0x3);

  1921                                                 }

  1922                                                 break;

  1923                                             case 0x1:

  1924                                                 switch( (ir&0xC00) >> 10 ) {

  1925                                                     case 0x0:

  1926                                                         { /* FSCHG */

  1927                                                         }

  1928                                                         break;

  1929                                                     case 0x2:

  1930                                                         { /* FRCHG */

  1931                                                         }

  1932                                                         break;

  1933                                                     case 0x3:

  1934                                                         { /* UNDEF */

  1935                                                         }

  1936                                                         break;

  1937                                                     default:

  1938                                                         UNDEF();

  1939                                                         break;

  1940                                                 }

  1941                                                 break;

  1942                                         }

  1943                                         break;

  1944                                 }

  1945                                 break;

  1946                             default:

  1947                                 UNDEF();

  1948                                 break;

  1949                         }

  1950                         break;

  1951                     case 0xE:

  1952                         { /* FMAC FR0, FRm, FRn */

  1953                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1954                         }

  1955                         break;

  1956                     default:

  1957                         UNDEF();

  1958                         break;

  1959                 }

  1960                 break;

  1961         }

  1964     return 0;

  1965 }