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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 361:be3de4ecd954
prev359:c588dce7ebde
next368:36fac4c42322
author nkeynes
date Tue Aug 28 08:46:14 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Translator WIP: fill out and correct another batch of instructions
file annotate diff log raw
nkeynes@359
     1
/**
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 * $Id: sh4x86.c,v 1.2 2007-08-28 08:46:14 nkeynes Exp $
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     3
 * 
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     4
 * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359
     5
 * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359
     6
 * to test the optimizing versions against.
nkeynes@359
     7
 *
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     8
 * Copyright (c) 2007 Nathan Keynes.
nkeynes@359
     9
 *
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    10
 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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    12
 * the Free Software Foundation; either version 2 of the License, or
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    13
 * (at your option) any later version.
nkeynes@359
    14
 *
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    15
 * This program is distributed in the hope that it will be useful,
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    16
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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    17
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    18
 * GNU General Public License for more details.
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    19
 */
nkeynes@359
    20
nkeynes@359
    21
#include "sh4core.h"
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    22
#include "sh4trans.h"
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    23
#include "x86op.h"
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    24
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    25
/**
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    26
 * Emit an instruction to load an SH4 reg into a real register
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    27
 */
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    28
static inline void load_reg( int x86reg, int sh4reg ) 
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    29
{
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    30
    /* mov [bp+n], reg */
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    31
    OP(0x8B);
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    32
    OP(0x45 + (x86reg<<3));
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    33
    OP(REG_OFFSET(r[sh4reg]));
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    34
}
nkeynes@359
    35
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    36
static inline void load_spreg( int x86reg, int regoffset )
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    37
{
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    38
    /* mov [bp+n], reg */
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    39
    OP(0x8B);
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    40
    OP(0x45 + (x86reg<<3));
nkeynes@359
    41
    OP(regoffset);
nkeynes@359
    42
}
nkeynes@359
    43
nkeynes@359
    44
/**
nkeynes@359
    45
 * Emit an instruction to load an immediate value into a register
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    46
 */
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    47
static inline void load_imm32( int x86reg, uint32_t value ) {
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    48
    /* mov #value, reg */
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    49
    OP(0xB8 + x86reg);
nkeynes@359
    50
    OP32(value);
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    51
}
nkeynes@359
    52
nkeynes@359
    53
/**
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    54
 * Emit an instruction to store an SH4 reg (RN)
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    55
 */
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    56
void static inline store_reg( int x86reg, int sh4reg ) {
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    57
    /* mov reg, [bp+n] */
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    58
    OP(0x89);
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    59
    OP(0x45 + (x86reg<<3));
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    60
    OP(REG_OFFSET(r[sh4reg]));
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    61
}
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    62
void static inline store_spreg( int x86reg, int regoffset ) {
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    63
    /* mov reg, [bp+n] */
nkeynes@361
    64
    OP(0x89);
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    65
    OP(0x45 + (x86reg<<3));
nkeynes@359
    66
    OP(regoffset);
nkeynes@359
    67
}
nkeynes@359
    68
nkeynes@361
    69
/**
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    70
 * Note: clobbers EAX to make the indirect call - this isn't usually
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    71
 * a problem since the callee will usually clobber it anyway.
nkeynes@361
    72
 */
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    73
static inline void call_func0( void *ptr )
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    74
{
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    75
    load_imm32(R_EAX, (uint32_t)ptr);
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    76
    OP(0xFF);
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    77
    MODRM_rm32_r32(R_EAX, 2);
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    78
}
nkeynes@361
    79
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    80
static inline void call_func1( void *ptr, int arg1 )
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    81
{
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    82
    PUSH_r32(arg1);
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    83
    call_func0(ptr);
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    84
    ADD_imm8s_r32( -4, R_ESP );
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    85
}
nkeynes@361
    86
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    87
static inline void call_func2( void *ptr, int arg1, int arg2 )
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    88
{
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    89
    PUSH_r32(arg2);
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    90
    PUSH_r32(arg1);
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    91
    call_func0(ptr);
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    92
    ADD_imm8s_r32( -4, R_ESP );
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    93
}
nkeynes@361
    94
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    95
#define UNDEF()
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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    98
#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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    99
#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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   100
#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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   101
#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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   104
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/**
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 * Emit the 'start of block' assembly. Sets up the stack frame and save
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 * SI/DI as required
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 */
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void sh4_translate_begin_block() {
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    /* push ebp */
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    *xlat_output++ = 0x50 + R_EBP;
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   112
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   113
    /* mov &sh4r, ebp */
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   114
    load_imm32( R_EBP, (uint32_t)&sh4r );
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   115
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   116
    /* load carry from SR */
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   117
}
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   118
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   119
/**
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 * Flush any open regs back to memory, restore SI/DI/, update PC, etc
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   121
 */
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   122
void sh4_translate_end_block( sh4addr_t pc ) {
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    /* pop ebp */
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   124
    *xlat_output++ = 0x58 + R_EBP;
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   125
nkeynes@359
   126
    /* ret */
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    *xlat_output++ = 0xC3;
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   128
}
nkeynes@359
   129
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   130
/**
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 * Translate a single instruction. Delayed branches are handled specially
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 * by translating both branch and delayed instruction as a single unit (as
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 * 
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   134
 *
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 * @return true if the instruction marks the end of a basic block
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   136
 * (eg a branch or 
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   137
 */
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   138
uint32_t sh4_x86_translate_instruction( uint32_t pc )
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   139
{
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   140
    uint16_t ir = sh4_read_word( pc );
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   141
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   142
        switch( (ir&0xF000) >> 12 ) {
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   143
            case 0x0:
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   144
                switch( ir&0xF ) {
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   145
                    case 0x2:
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   146
                        switch( (ir&0x80) >> 7 ) {
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   147
                            case 0x0:
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   148
                                switch( (ir&0x70) >> 4 ) {
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   149
                                    case 0x0:
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   150
                                        { /* STC SR, Rn */
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   151
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   152
                                        /* TODO */
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   153
                                        }
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   154
                                        break;
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   155
                                    case 0x1:
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   156
                                        { /* STC GBR, Rn */
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   157
                                        uint32_t Rn = ((ir>>8)&0xF); 
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   158
                                        load_spreg( R_EAX, R_GBR );
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   159
                                        store_reg( R_EAX, Rn );
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   160
                                        }
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                                        break;
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   162
                                    case 0x2:
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                                        { /* STC VBR, Rn */
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                                        uint32_t Rn = ((ir>>8)&0xF); 
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                                        load_spreg( R_EAX, R_VBR );
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                                        store_reg( R_EAX, Rn );
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   167
                                        }
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   168
                                        break;
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   169
                                    case 0x3:
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   170
                                        { /* STC SSR, Rn */
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                                        uint32_t Rn = ((ir>>8)&0xF); 
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                                        load_spreg( R_EAX, R_SSR );
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                                        store_reg( R_EAX, Rn );
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   174
                                        }
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                                        break;
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   176
                                    case 0x4:
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                                        { /* STC SPC, Rn */
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                                        uint32_t Rn = ((ir>>8)&0xF); 
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                                        load_spreg( R_EAX, R_SPC );
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                                        store_reg( R_EAX, Rn );
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                                        }
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                                        break;
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   183
                                    default:
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                                        UNDEF();
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                                        break;
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   186
                                }
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                                break;
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   188
                            case 0x1:
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                                { /* STC Rm_BANK, Rn */
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   190
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
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   191
                                /* TODO */
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   192
                                }
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   193
                                break;
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   194
                        }
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   195
                        break;
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   196
                    case 0x3:
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                        switch( (ir&0xF0) >> 4 ) {
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   198
                            case 0x0:
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   199
                                { /* BSRF Rn */
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   200
                                uint32_t Rn = ((ir>>8)&0xF); 
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   201
                                }
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                                break;
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   203
                            case 0x2:
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                                { /* BRAF Rn */
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                                uint32_t Rn = ((ir>>8)&0xF); 
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   206
                                }
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                                break;
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   208
                            case 0x8:
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                                { /* PREF @Rn */
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                                uint32_t Rn = ((ir>>8)&0xF); 
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                                }
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                                break;
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   213
                            case 0x9:
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                                { /* OCBI @Rn */
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                                uint32_t Rn = ((ir>>8)&0xF); 
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   216
                                }
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   217
                                break;
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   218
                            case 0xA:
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   219
                                { /* OCBP @Rn */
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   220
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   221
                                }
nkeynes@359
   222
                                break;
nkeynes@359
   223
                            case 0xB:
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   224
                                { /* OCBWB @Rn */
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                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   226
                                }
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   227
                                break;
nkeynes@359
   228
                            case 0xC:
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   229
                                { /* MOVCA.L R0, @Rn */
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   230
                                uint32_t Rn = ((ir>>8)&0xF); 
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                                load_reg( R_EAX, 0 );
nkeynes@361
   232
                                load_reg( R_ECX, Rn );
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   233
                                MEM_WRITE_LONG( R_ECX, R_EAX );
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   234
                                }
nkeynes@359
   235
                                break;
nkeynes@359
   236
                            default:
nkeynes@359
   237
                                UNDEF();
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                                break;
nkeynes@359
   239
                        }
nkeynes@359
   240
                        break;
nkeynes@359
   241
                    case 0x4:
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   242
                        { /* MOV.B Rm, @(R0, Rn) */
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                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   244
                        load_reg( R_EAX, 0 );
nkeynes@359
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                        load_reg( R_ECX, Rn );
nkeynes@359
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                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   247
                        load_reg( R_EAX, Rm );
nkeynes@359
   248
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   249
                        }
nkeynes@359
   250
                        break;
nkeynes@359
   251
                    case 0x5:
nkeynes@359
   252
                        { /* MOV.W Rm, @(R0, Rn) */
nkeynes@359
   253
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   254
                        load_reg( R_EAX, 0 );
nkeynes@361
   255
                        load_reg( R_ECX, Rn );
nkeynes@361
   256
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   257
                        load_reg( R_EAX, Rm );
nkeynes@361
   258
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   259
                        }
nkeynes@359
   260
                        break;
nkeynes@359
   261
                    case 0x6:
nkeynes@359
   262
                        { /* MOV.L Rm, @(R0, Rn) */
nkeynes@359
   263
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   264
                        load_reg( R_EAX, 0 );
nkeynes@361
   265
                        load_reg( R_ECX, Rn );
nkeynes@361
   266
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   267
                        load_reg( R_EAX, Rm );
nkeynes@361
   268
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   269
                        }
nkeynes@359
   270
                        break;
nkeynes@359
   271
                    case 0x7:
nkeynes@359
   272
                        { /* MUL.L Rm, Rn */
nkeynes@359
   273
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   274
                        load_reg( R_EAX, Rm );
nkeynes@361
   275
                        load_reg( R_ECX, Rn );
nkeynes@361
   276
                        MUL_r32( R_ECX );
nkeynes@361
   277
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   278
                        }
nkeynes@359
   279
                        break;
nkeynes@359
   280
                    case 0x8:
nkeynes@359
   281
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   282
                            case 0x0:
nkeynes@359
   283
                                { /* CLRT */
nkeynes@359
   284
                                }
nkeynes@359
   285
                                break;
nkeynes@359
   286
                            case 0x1:
nkeynes@359
   287
                                { /* SETT */
nkeynes@359
   288
                                }
nkeynes@359
   289
                                break;
nkeynes@359
   290
                            case 0x2:
nkeynes@359
   291
                                { /* CLRMAC */
nkeynes@359
   292
                                }
nkeynes@359
   293
                                break;
nkeynes@359
   294
                            case 0x3:
nkeynes@359
   295
                                { /* LDTLB */
nkeynes@359
   296
                                }
nkeynes@359
   297
                                break;
nkeynes@359
   298
                            case 0x4:
nkeynes@359
   299
                                { /* CLRS */
nkeynes@359
   300
                                }
nkeynes@359
   301
                                break;
nkeynes@359
   302
                            case 0x5:
nkeynes@359
   303
                                { /* SETS */
nkeynes@359
   304
                                }
nkeynes@359
   305
                                break;
nkeynes@359
   306
                            default:
nkeynes@359
   307
                                UNDEF();
nkeynes@359
   308
                                break;
nkeynes@359
   309
                        }
nkeynes@359
   310
                        break;
nkeynes@359
   311
                    case 0x9:
nkeynes@359
   312
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   313
                            case 0x0:
nkeynes@359
   314
                                { /* NOP */
nkeynes@359
   315
                                /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359
   316
                                }
nkeynes@359
   317
                                break;
nkeynes@359
   318
                            case 0x1:
nkeynes@359
   319
                                { /* DIV0U */
nkeynes@361
   320
                                XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   321
                                store_spreg( R_EAX, R_Q );
nkeynes@361
   322
                                store_spreg( R_EAX, R_M );
nkeynes@361
   323
                                store_spreg( R_EAX, R_T );
nkeynes@359
   324
                                }
nkeynes@359
   325
                                break;
nkeynes@359
   326
                            case 0x2:
nkeynes@359
   327
                                { /* MOVT Rn */
nkeynes@359
   328
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   329
                                load_spreg( R_EAX, R_T );
nkeynes@359
   330
                                store_reg( R_EAX, Rn );
nkeynes@359
   331
                                }
nkeynes@359
   332
                                break;
nkeynes@359
   333
                            default:
nkeynes@359
   334
                                UNDEF();
nkeynes@359
   335
                                break;
nkeynes@359
   336
                        }
nkeynes@359
   337
                        break;
nkeynes@359
   338
                    case 0xA:
nkeynes@359
   339
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   340
                            case 0x0:
nkeynes@359
   341
                                { /* STS MACH, Rn */
nkeynes@359
   342
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   343
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   344
                                store_reg( R_EAX, Rn );
nkeynes@359
   345
                                }
nkeynes@359
   346
                                break;
nkeynes@359
   347
                            case 0x1:
nkeynes@359
   348
                                { /* STS MACL, Rn */
nkeynes@359
   349
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   350
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   351
                                store_reg( R_EAX, Rn );
nkeynes@359
   352
                                }
nkeynes@359
   353
                                break;
nkeynes@359
   354
                            case 0x2:
nkeynes@359
   355
                                { /* STS PR, Rn */
nkeynes@359
   356
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   357
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   358
                                store_reg( R_EAX, Rn );
nkeynes@359
   359
                                }
nkeynes@359
   360
                                break;
nkeynes@359
   361
                            case 0x3:
nkeynes@359
   362
                                { /* STC SGR, Rn */
nkeynes@359
   363
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   364
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   365
                                store_reg( R_EAX, Rn );
nkeynes@359
   366
                                }
nkeynes@359
   367
                                break;
nkeynes@359
   368
                            case 0x5:
nkeynes@359
   369
                                { /* STS FPUL, Rn */
nkeynes@359
   370
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   371
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   372
                                store_reg( R_EAX, Rn );
nkeynes@359
   373
                                }
nkeynes@359
   374
                                break;
nkeynes@359
   375
                            case 0x6:
nkeynes@359
   376
                                { /* STS FPSCR, Rn */
nkeynes@359
   377
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   378
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   379
                                store_reg( R_EAX, Rn );
nkeynes@359
   380
                                }
nkeynes@359
   381
                                break;
nkeynes@359
   382
                            case 0xF:
nkeynes@359
   383
                                { /* STC DBR, Rn */
nkeynes@359
   384
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   385
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   386
                                store_reg( R_EAX, Rn );
nkeynes@359
   387
                                }
nkeynes@359
   388
                                break;
nkeynes@359
   389
                            default:
nkeynes@359
   390
                                UNDEF();
nkeynes@359
   391
                                break;
nkeynes@359
   392
                        }
nkeynes@359
   393
                        break;
nkeynes@359
   394
                    case 0xB:
nkeynes@359
   395
                        switch( (ir&0xFF0) >> 4 ) {
nkeynes@359
   396
                            case 0x0:
nkeynes@359
   397
                                { /* RTS */
nkeynes@359
   398
                                }
nkeynes@359
   399
                                break;
nkeynes@359
   400
                            case 0x1:
nkeynes@359
   401
                                { /* SLEEP */
nkeynes@359
   402
                                }
nkeynes@359
   403
                                break;
nkeynes@359
   404
                            case 0x2:
nkeynes@359
   405
                                { /* RTE */
nkeynes@359
   406
                                }
nkeynes@359
   407
                                break;
nkeynes@359
   408
                            default:
nkeynes@359
   409
                                UNDEF();
nkeynes@359
   410
                                break;
nkeynes@359
   411
                        }
nkeynes@359
   412
                        break;
nkeynes@359
   413
                    case 0xC:
nkeynes@359
   414
                        { /* MOV.B @(R0, Rm), Rn */
nkeynes@359
   415
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   416
                        load_reg( R_EAX, 0 );
nkeynes@359
   417
                        load_reg( R_ECX, Rm );
nkeynes@359
   418
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   419
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
   420
                        store_reg( R_EAX, Rn );
nkeynes@359
   421
                        }
nkeynes@359
   422
                        break;
nkeynes@359
   423
                    case 0xD:
nkeynes@359
   424
                        { /* MOV.W @(R0, Rm), Rn */
nkeynes@359
   425
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   426
                        load_reg( R_EAX, 0 );
nkeynes@361
   427
                        load_reg( R_ECX, Rm );
nkeynes@361
   428
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   429
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   430
                        store_reg( R_EAX, Rn );
nkeynes@359
   431
                        }
nkeynes@359
   432
                        break;
nkeynes@359
   433
                    case 0xE:
nkeynes@359
   434
                        { /* MOV.L @(R0, Rm), Rn */
nkeynes@359
   435
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   436
                        load_reg( R_EAX, 0 );
nkeynes@361
   437
                        load_reg( R_ECX, Rm );
nkeynes@361
   438
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@361
   439
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
   440
                        store_reg( R_EAX, Rn );
nkeynes@359
   441
                        }
nkeynes@359
   442
                        break;
nkeynes@359
   443
                    case 0xF:
nkeynes@359
   444
                        { /* MAC.L @Rm+, @Rn+ */
nkeynes@359
   445
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   446
                        }
nkeynes@359
   447
                        break;
nkeynes@359
   448
                    default:
nkeynes@359
   449
                        UNDEF();
nkeynes@359
   450
                        break;
nkeynes@359
   451
                }
nkeynes@359
   452
                break;
nkeynes@359
   453
            case 0x1:
nkeynes@359
   454
                { /* MOV.L Rm, @(disp, Rn) */
nkeynes@359
   455
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
   456
                load_reg( R_ECX, Rn );
nkeynes@361
   457
                load_reg( R_EAX, Rm );
nkeynes@361
   458
                ADD_imm32_r32( disp, R_ECX );
nkeynes@361
   459
                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   460
                }
nkeynes@359
   461
                break;
nkeynes@359
   462
            case 0x2:
nkeynes@359
   463
                switch( ir&0xF ) {
nkeynes@359
   464
                    case 0x0:
nkeynes@359
   465
                        { /* MOV.B Rm, @Rn */
nkeynes@359
   466
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   467
                        load_reg( R_EAX, Rm );
nkeynes@359
   468
                        load_reg( R_ECX, Rn );
nkeynes@359
   469
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   470
                        }
nkeynes@359
   471
                        break;
nkeynes@359
   472
                    case 0x1:
nkeynes@359
   473
                        { /* MOV.W Rm, @Rn */
nkeynes@359
   474
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   475
                        load_reg( R_ECX, Rn );
nkeynes@361
   476
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
   477
                        store_reg( R_EAX, Rn );
nkeynes@359
   478
                        }
nkeynes@359
   479
                        break;
nkeynes@359
   480
                    case 0x2:
nkeynes@359
   481
                        { /* MOV.L Rm, @Rn */
nkeynes@359
   482
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   483
                        load_reg( R_EAX, Rm );
nkeynes@361
   484
                        load_reg( R_ECX, Rn );
nkeynes@361
   485
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   486
                        }
nkeynes@359
   487
                        break;
nkeynes@359
   488
                    case 0x4:
nkeynes@359
   489
                        { /* MOV.B Rm, @-Rn */
nkeynes@359
   490
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   491
                        load_reg( R_EAX, Rm );
nkeynes@359
   492
                        load_reg( R_ECX, Rn );
nkeynes@359
   493
                        ADD_imm8s_r32( -1, Rn );
nkeynes@359
   494
                        store_reg( R_ECX, Rn );
nkeynes@359
   495
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
   496
                        }
nkeynes@359
   497
                        break;
nkeynes@359
   498
                    case 0x5:
nkeynes@359
   499
                        { /* MOV.W Rm, @-Rn */
nkeynes@359
   500
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   501
                        load_reg( R_ECX, Rn );
nkeynes@361
   502
                        load_reg( R_EAX, Rm );
nkeynes@361
   503
                        ADD_imm8s_r32( -2, R_ECX );
nkeynes@361
   504
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
   505
                        }
nkeynes@359
   506
                        break;
nkeynes@359
   507
                    case 0x6:
nkeynes@359
   508
                        { /* MOV.L Rm, @-Rn */
nkeynes@359
   509
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   510
                        load_reg( R_EAX, Rm );
nkeynes@361
   511
                        load_reg( R_ECX, Rn );
nkeynes@361
   512
                        ADD_imm8s_r32( -4, R_ECX );
nkeynes@361
   513
                        store_reg( R_ECX, Rn );
nkeynes@361
   514
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   515
                        }
nkeynes@359
   516
                        break;
nkeynes@359
   517
                    case 0x7:
nkeynes@359
   518
                        { /* DIV0S Rm, Rn */
nkeynes@359
   519
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   520
                        load_reg( R_EAX, Rm );
nkeynes@361
   521
                        load_reg( R_ECX, Rm );
nkeynes@361
   522
                        SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   523
                        SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   524
                        store_spreg( R_EAX, R_M );
nkeynes@361
   525
                        store_spreg( R_ECX, R_Q );
nkeynes@361
   526
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@361
   527
                        SETE_t();
nkeynes@359
   528
                        }
nkeynes@359
   529
                        break;
nkeynes@359
   530
                    case 0x8:
nkeynes@359
   531
                        { /* TST Rm, Rn */
nkeynes@359
   532
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   533
                        load_reg( R_EAX, Rm );
nkeynes@361
   534
                        load_reg( R_ECX, Rn );
nkeynes@361
   535
                        TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
   536
                        SETE_t();
nkeynes@359
   537
                        }
nkeynes@359
   538
                        break;
nkeynes@359
   539
                    case 0x9:
nkeynes@359
   540
                        { /* AND Rm, Rn */
nkeynes@359
   541
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   542
                        load_reg( R_EAX, Rm );
nkeynes@359
   543
                        load_reg( R_ECX, Rn );
nkeynes@359
   544
                        AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   545
                        store_reg( R_ECX, Rn );
nkeynes@359
   546
                        }
nkeynes@359
   547
                        break;
nkeynes@359
   548
                    case 0xA:
nkeynes@359
   549
                        { /* XOR Rm, Rn */
nkeynes@359
   550
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   551
                        load_reg( R_EAX, Rm );
nkeynes@359
   552
                        load_reg( R_ECX, Rn );
nkeynes@359
   553
                        XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   554
                        store_reg( R_ECX, Rn );
nkeynes@359
   555
                        }
nkeynes@359
   556
                        break;
nkeynes@359
   557
                    case 0xB:
nkeynes@359
   558
                        { /* OR Rm, Rn */
nkeynes@359
   559
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   560
                        load_reg( R_EAX, Rm );
nkeynes@359
   561
                        load_reg( R_ECX, Rn );
nkeynes@359
   562
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   563
                        store_reg( R_ECX, Rn );
nkeynes@359
   564
                        }
nkeynes@359
   565
                        break;
nkeynes@359
   566
                    case 0xC:
nkeynes@359
   567
                        { /* CMP/STR Rm, Rn */
nkeynes@359
   568
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   569
                        }
nkeynes@359
   570
                        break;
nkeynes@359
   571
                    case 0xD:
nkeynes@359
   572
                        { /* XTRCT Rm, Rn */
nkeynes@359
   573
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   574
                        load_reg( R_EAX, Rm );
nkeynes@361
   575
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
   576
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@361
   577
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@361
   578
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
   579
                        store_reg( R_ECX, Rn );
nkeynes@359
   580
                        }
nkeynes@359
   581
                        break;
nkeynes@359
   582
                    case 0xE:
nkeynes@359
   583
                        { /* MULU.W Rm, Rn */
nkeynes@359
   584
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   585
                        }
nkeynes@359
   586
                        break;
nkeynes@359
   587
                    case 0xF:
nkeynes@359
   588
                        { /* MULS.W Rm, Rn */
nkeynes@359
   589
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   590
                        }
nkeynes@359
   591
                        break;
nkeynes@359
   592
                    default:
nkeynes@359
   593
                        UNDEF();
nkeynes@359
   594
                        break;
nkeynes@359
   595
                }
nkeynes@359
   596
                break;
nkeynes@359
   597
            case 0x3:
nkeynes@359
   598
                switch( ir&0xF ) {
nkeynes@359
   599
                    case 0x0:
nkeynes@359
   600
                        { /* CMP/EQ Rm, Rn */
nkeynes@359
   601
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   602
                        load_reg( R_EAX, Rm );
nkeynes@359
   603
                        load_reg( R_ECX, Rn );
nkeynes@359
   604
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   605
                        SETE_t();
nkeynes@359
   606
                        }
nkeynes@359
   607
                        break;
nkeynes@359
   608
                    case 0x2:
nkeynes@359
   609
                        { /* CMP/HS Rm, Rn */
nkeynes@359
   610
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   611
                        load_reg( R_EAX, Rm );
nkeynes@359
   612
                        load_reg( R_ECX, Rn );
nkeynes@359
   613
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   614
                        SETAE_t();
nkeynes@359
   615
                        }
nkeynes@359
   616
                        break;
nkeynes@359
   617
                    case 0x3:
nkeynes@359
   618
                        { /* CMP/GE Rm, Rn */
nkeynes@359
   619
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   620
                        load_reg( R_EAX, Rm );
nkeynes@359
   621
                        load_reg( R_ECX, Rn );
nkeynes@359
   622
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   623
                        SETGE_t();
nkeynes@359
   624
                        }
nkeynes@359
   625
                        break;
nkeynes@359
   626
                    case 0x4:
nkeynes@359
   627
                        { /* DIV1 Rm, Rn */
nkeynes@359
   628
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   629
                        }
nkeynes@359
   630
                        break;
nkeynes@359
   631
                    case 0x5:
nkeynes@359
   632
                        { /* DMULU.L Rm, Rn */
nkeynes@359
   633
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   634
                        load_reg( R_EAX, Rm );
nkeynes@361
   635
                        load_reg( R_ECX, Rn );
nkeynes@361
   636
                        MUL_r32(R_ECX);
nkeynes@361
   637
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
   638
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   639
                        }
nkeynes@359
   640
                        break;
nkeynes@359
   641
                    case 0x6:
nkeynes@359
   642
                        { /* CMP/HI Rm, Rn */
nkeynes@359
   643
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   644
                        load_reg( R_EAX, Rm );
nkeynes@359
   645
                        load_reg( R_ECX, Rn );
nkeynes@359
   646
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   647
                        SETA_t();
nkeynes@359
   648
                        }
nkeynes@359
   649
                        break;
nkeynes@359
   650
                    case 0x7:
nkeynes@359
   651
                        { /* CMP/GT Rm, Rn */
nkeynes@359
   652
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   653
                        load_reg( R_EAX, Rm );
nkeynes@359
   654
                        load_reg( R_ECX, Rn );
nkeynes@359
   655
                        CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   656
                        SETG_t();
nkeynes@359
   657
                        }
nkeynes@359
   658
                        break;
nkeynes@359
   659
                    case 0x8:
nkeynes@359
   660
                        { /* SUB Rm, Rn */
nkeynes@359
   661
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   662
                        load_reg( R_EAX, Rm );
nkeynes@359
   663
                        load_reg( R_ECX, Rn );
nkeynes@359
   664
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   665
                        store_reg( R_ECX, Rn );
nkeynes@359
   666
                        }
nkeynes@359
   667
                        break;
nkeynes@359
   668
                    case 0xA:
nkeynes@359
   669
                        { /* SUBC Rm, Rn */
nkeynes@359
   670
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   671
                        load_reg( R_EAX, Rm );
nkeynes@359
   672
                        load_reg( R_ECX, Rn );
nkeynes@359
   673
                        LDC_t();
nkeynes@359
   674
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   675
                        store_reg( R_ECX, Rn );
nkeynes@359
   676
                        }
nkeynes@359
   677
                        break;
nkeynes@359
   678
                    case 0xB:
nkeynes@359
   679
                        { /* SUBV Rm, Rn */
nkeynes@359
   680
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   681
                        load_reg( R_EAX, Rm );
nkeynes@359
   682
                        load_reg( R_ECX, Rn );
nkeynes@359
   683
                        SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   684
                        store_reg( R_ECX, Rn );
nkeynes@359
   685
                        SETO_t();
nkeynes@359
   686
                        }
nkeynes@359
   687
                        break;
nkeynes@359
   688
                    case 0xC:
nkeynes@359
   689
                        { /* ADD Rm, Rn */
nkeynes@359
   690
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   691
                        load_reg( R_EAX, Rm );
nkeynes@359
   692
                        load_reg( R_ECX, Rn );
nkeynes@359
   693
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   694
                        store_reg( R_ECX, Rn );
nkeynes@359
   695
                        }
nkeynes@359
   696
                        break;
nkeynes@359
   697
                    case 0xD:
nkeynes@359
   698
                        { /* DMULS.L Rm, Rn */
nkeynes@359
   699
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
   700
                        load_reg( R_EAX, Rm );
nkeynes@361
   701
                        load_reg( R_ECX, Rn );
nkeynes@361
   702
                        IMUL_r32(R_ECX);
nkeynes@361
   703
                        store_spreg( R_EDX, R_MACH );
nkeynes@361
   704
                        store_spreg( R_EAX, R_MACL );
nkeynes@359
   705
                        }
nkeynes@359
   706
                        break;
nkeynes@359
   707
                    case 0xE:
nkeynes@359
   708
                        { /* ADDC Rm, Rn */
nkeynes@359
   709
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   710
                        load_reg( R_EAX, Rm );
nkeynes@359
   711
                        load_reg( R_ECX, Rn );
nkeynes@359
   712
                        LDC_t();
nkeynes@359
   713
                        ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   714
                        store_reg( R_ECX, Rn );
nkeynes@359
   715
                        SETC_t();
nkeynes@359
   716
                        }
nkeynes@359
   717
                        break;
nkeynes@359
   718
                    case 0xF:
nkeynes@359
   719
                        { /* ADDV Rm, Rn */
nkeynes@359
   720
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
   721
                        load_reg( R_EAX, Rm );
nkeynes@359
   722
                        load_reg( R_ECX, Rn );
nkeynes@359
   723
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   724
                        store_reg( R_ECX, Rn );
nkeynes@359
   725
                        SETO_t();
nkeynes@359
   726
                        }
nkeynes@359
   727
                        break;
nkeynes@359
   728
                    default:
nkeynes@359
   729
                        UNDEF();
nkeynes@359
   730
                        break;
nkeynes@359
   731
                }
nkeynes@359
   732
                break;
nkeynes@359
   733
            case 0x4:
nkeynes@359
   734
                switch( ir&0xF ) {
nkeynes@359
   735
                    case 0x0:
nkeynes@359
   736
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   737
                            case 0x0:
nkeynes@359
   738
                                { /* SHLL Rn */
nkeynes@359
   739
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   740
                                load_reg( R_EAX, Rn );
nkeynes@359
   741
                                SHL1_r32( R_EAX );
nkeynes@359
   742
                                store_reg( R_EAX, Rn );
nkeynes@359
   743
                                }
nkeynes@359
   744
                                break;
nkeynes@359
   745
                            case 0x1:
nkeynes@359
   746
                                { /* DT Rn */
nkeynes@359
   747
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   748
                                load_reg( R_EAX, Rn );
nkeynes@359
   749
                                ADD_imm8s_r32( -1, Rn );
nkeynes@359
   750
                                store_reg( R_EAX, Rn );
nkeynes@359
   751
                                SETE_t();
nkeynes@359
   752
                                }
nkeynes@359
   753
                                break;
nkeynes@359
   754
                            case 0x2:
nkeynes@359
   755
                                { /* SHAL Rn */
nkeynes@359
   756
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   757
                                load_reg( R_EAX, Rn );
nkeynes@359
   758
                                SHL1_r32( R_EAX );
nkeynes@359
   759
                                store_reg( R_EAX, Rn );
nkeynes@359
   760
                                }
nkeynes@359
   761
                                break;
nkeynes@359
   762
                            default:
nkeynes@359
   763
                                UNDEF();
nkeynes@359
   764
                                break;
nkeynes@359
   765
                        }
nkeynes@359
   766
                        break;
nkeynes@359
   767
                    case 0x1:
nkeynes@359
   768
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   769
                            case 0x0:
nkeynes@359
   770
                                { /* SHLR Rn */
nkeynes@359
   771
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   772
                                load_reg( R_EAX, Rn );
nkeynes@359
   773
                                SHR1_r32( R_EAX );
nkeynes@359
   774
                                store_reg( R_EAX, Rn );
nkeynes@359
   775
                                }
nkeynes@359
   776
                                break;
nkeynes@359
   777
                            case 0x1:
nkeynes@359
   778
                                { /* CMP/PZ Rn */
nkeynes@359
   779
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   780
                                load_reg( R_EAX, Rn );
nkeynes@359
   781
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   782
                                SETGE_t();
nkeynes@359
   783
                                }
nkeynes@359
   784
                                break;
nkeynes@359
   785
                            case 0x2:
nkeynes@359
   786
                                { /* SHAR Rn */
nkeynes@359
   787
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   788
                                load_reg( R_EAX, Rn );
nkeynes@359
   789
                                SAR1_r32( R_EAX );
nkeynes@359
   790
                                store_reg( R_EAX, Rn );
nkeynes@359
   791
                                }
nkeynes@359
   792
                                break;
nkeynes@359
   793
                            default:
nkeynes@359
   794
                                UNDEF();
nkeynes@359
   795
                                break;
nkeynes@359
   796
                        }
nkeynes@359
   797
                        break;
nkeynes@359
   798
                    case 0x2:
nkeynes@359
   799
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   800
                            case 0x0:
nkeynes@359
   801
                                { /* STS.L MACH, @-Rn */
nkeynes@359
   802
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   803
                                load_reg( R_ECX, Rn );
nkeynes@359
   804
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   805
                                store_reg( R_ECX, Rn );
nkeynes@359
   806
                                load_spreg( R_EAX, R_MACH );
nkeynes@359
   807
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   808
                                }
nkeynes@359
   809
                                break;
nkeynes@359
   810
                            case 0x1:
nkeynes@359
   811
                                { /* STS.L MACL, @-Rn */
nkeynes@359
   812
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   813
                                load_reg( R_ECX, Rn );
nkeynes@359
   814
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   815
                                store_reg( R_ECX, Rn );
nkeynes@359
   816
                                load_spreg( R_EAX, R_MACL );
nkeynes@359
   817
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   818
                                }
nkeynes@359
   819
                                break;
nkeynes@359
   820
                            case 0x2:
nkeynes@359
   821
                                { /* STS.L PR, @-Rn */
nkeynes@359
   822
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   823
                                load_reg( R_ECX, Rn );
nkeynes@359
   824
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   825
                                store_reg( R_ECX, Rn );
nkeynes@359
   826
                                load_spreg( R_EAX, R_PR );
nkeynes@359
   827
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   828
                                }
nkeynes@359
   829
                                break;
nkeynes@359
   830
                            case 0x3:
nkeynes@359
   831
                                { /* STC.L SGR, @-Rn */
nkeynes@359
   832
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   833
                                load_reg( R_ECX, Rn );
nkeynes@359
   834
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   835
                                store_reg( R_ECX, Rn );
nkeynes@359
   836
                                load_spreg( R_EAX, R_SGR );
nkeynes@359
   837
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   838
                                }
nkeynes@359
   839
                                break;
nkeynes@359
   840
                            case 0x5:
nkeynes@359
   841
                                { /* STS.L FPUL, @-Rn */
nkeynes@359
   842
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   843
                                load_reg( R_ECX, Rn );
nkeynes@359
   844
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   845
                                store_reg( R_ECX, Rn );
nkeynes@359
   846
                                load_spreg( R_EAX, R_FPUL );
nkeynes@359
   847
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   848
                                }
nkeynes@359
   849
                                break;
nkeynes@359
   850
                            case 0x6:
nkeynes@359
   851
                                { /* STS.L FPSCR, @-Rn */
nkeynes@359
   852
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   853
                                load_reg( R_ECX, Rn );
nkeynes@359
   854
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   855
                                store_reg( R_ECX, Rn );
nkeynes@359
   856
                                load_spreg( R_EAX, R_FPSCR );
nkeynes@359
   857
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   858
                                }
nkeynes@359
   859
                                break;
nkeynes@359
   860
                            case 0xF:
nkeynes@359
   861
                                { /* STC.L DBR, @-Rn */
nkeynes@359
   862
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   863
                                load_reg( R_ECX, Rn );
nkeynes@359
   864
                                ADD_imm8s_r32( -4, Rn );
nkeynes@359
   865
                                store_reg( R_ECX, Rn );
nkeynes@359
   866
                                load_spreg( R_EAX, R_DBR );
nkeynes@359
   867
                                MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   868
                                }
nkeynes@359
   869
                                break;
nkeynes@359
   870
                            default:
nkeynes@359
   871
                                UNDEF();
nkeynes@359
   872
                                break;
nkeynes@359
   873
                        }
nkeynes@359
   874
                        break;
nkeynes@359
   875
                    case 0x3:
nkeynes@359
   876
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
   877
                            case 0x0:
nkeynes@359
   878
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
   879
                                    case 0x0:
nkeynes@359
   880
                                        { /* STC.L SR, @-Rn */
nkeynes@359
   881
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   882
                                        /* TODO */
nkeynes@359
   883
                                        }
nkeynes@359
   884
                                        break;
nkeynes@359
   885
                                    case 0x1:
nkeynes@359
   886
                                        { /* STC.L GBR, @-Rn */
nkeynes@359
   887
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   888
                                        load_reg( R_ECX, Rn );
nkeynes@359
   889
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   890
                                        store_reg( R_ECX, Rn );
nkeynes@359
   891
                                        load_spreg( R_EAX, R_GBR );
nkeynes@359
   892
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   893
                                        }
nkeynes@359
   894
                                        break;
nkeynes@359
   895
                                    case 0x2:
nkeynes@359
   896
                                        { /* STC.L VBR, @-Rn */
nkeynes@359
   897
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   898
                                        load_reg( R_ECX, Rn );
nkeynes@359
   899
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   900
                                        store_reg( R_ECX, Rn );
nkeynes@359
   901
                                        load_spreg( R_EAX, R_VBR );
nkeynes@359
   902
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   903
                                        }
nkeynes@359
   904
                                        break;
nkeynes@359
   905
                                    case 0x3:
nkeynes@359
   906
                                        { /* STC.L SSR, @-Rn */
nkeynes@359
   907
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   908
                                        load_reg( R_ECX, Rn );
nkeynes@359
   909
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   910
                                        store_reg( R_ECX, Rn );
nkeynes@359
   911
                                        load_spreg( R_EAX, R_SSR );
nkeynes@359
   912
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   913
                                        }
nkeynes@359
   914
                                        break;
nkeynes@359
   915
                                    case 0x4:
nkeynes@359
   916
                                        { /* STC.L SPC, @-Rn */
nkeynes@359
   917
                                        uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   918
                                        load_reg( R_ECX, Rn );
nkeynes@359
   919
                                        ADD_imm8s_r32( -4, Rn );
nkeynes@359
   920
                                        store_reg( R_ECX, Rn );
nkeynes@359
   921
                                        load_spreg( R_EAX, R_SPC );
nkeynes@359
   922
                                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
   923
                                        }
nkeynes@359
   924
                                        break;
nkeynes@359
   925
                                    default:
nkeynes@359
   926
                                        UNDEF();
nkeynes@359
   927
                                        break;
nkeynes@359
   928
                                }
nkeynes@359
   929
                                break;
nkeynes@359
   930
                            case 0x1:
nkeynes@359
   931
                                { /* STC.L Rm_BANK, @-Rn */
nkeynes@359
   932
                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
nkeynes@359
   933
                                }
nkeynes@359
   934
                                break;
nkeynes@359
   935
                        }
nkeynes@359
   936
                        break;
nkeynes@359
   937
                    case 0x4:
nkeynes@359
   938
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   939
                            case 0x0:
nkeynes@359
   940
                                { /* ROTL Rn */
nkeynes@359
   941
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   942
                                load_reg( R_EAX, Rn );
nkeynes@359
   943
                                ROL1_r32( R_EAX );
nkeynes@359
   944
                                store_reg( R_EAX, Rn );
nkeynes@359
   945
                                SETC_t();
nkeynes@359
   946
                                }
nkeynes@359
   947
                                break;
nkeynes@359
   948
                            case 0x2:
nkeynes@359
   949
                                { /* ROTCL Rn */
nkeynes@359
   950
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   951
                                load_reg( R_EAX, Rn );
nkeynes@359
   952
                                LDC_t();
nkeynes@359
   953
                                RCL1_r32( R_EAX );
nkeynes@359
   954
                                store_reg( R_EAX, Rn );
nkeynes@359
   955
                                SETC_t();
nkeynes@359
   956
                                }
nkeynes@359
   957
                                break;
nkeynes@359
   958
                            default:
nkeynes@359
   959
                                UNDEF();
nkeynes@359
   960
                                break;
nkeynes@359
   961
                        }
nkeynes@359
   962
                        break;
nkeynes@359
   963
                    case 0x5:
nkeynes@359
   964
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   965
                            case 0x0:
nkeynes@359
   966
                                { /* ROTR Rn */
nkeynes@359
   967
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   968
                                load_reg( R_EAX, Rn );
nkeynes@359
   969
                                ROR1_r32( R_EAX );
nkeynes@359
   970
                                store_reg( R_EAX, Rn );
nkeynes@359
   971
                                SETC_t();
nkeynes@359
   972
                                }
nkeynes@359
   973
                                break;
nkeynes@359
   974
                            case 0x1:
nkeynes@359
   975
                                { /* CMP/PL Rn */
nkeynes@359
   976
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   977
                                load_reg( R_EAX, Rn );
nkeynes@359
   978
                                CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   979
                                SETG_t();
nkeynes@359
   980
                                }
nkeynes@359
   981
                                break;
nkeynes@359
   982
                            case 0x2:
nkeynes@359
   983
                                { /* ROTCR Rn */
nkeynes@359
   984
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
   985
                                load_reg( R_EAX, Rn );
nkeynes@359
   986
                                LDC_t();
nkeynes@359
   987
                                RCR1_r32( R_EAX );
nkeynes@359
   988
                                store_reg( R_EAX, Rn );
nkeynes@359
   989
                                SETC_t();
nkeynes@359
   990
                                }
nkeynes@359
   991
                                break;
nkeynes@359
   992
                            default:
nkeynes@359
   993
                                UNDEF();
nkeynes@359
   994
                                break;
nkeynes@359
   995
                        }
nkeynes@359
   996
                        break;
nkeynes@359
   997
                    case 0x6:
nkeynes@359
   998
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
   999
                            case 0x0:
nkeynes@359
  1000
                                { /* LDS.L @Rm+, MACH */
nkeynes@359
  1001
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1002
                                load_reg( R_EAX, Rm );
nkeynes@359
  1003
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1005
                                store_reg( R_EAX, Rm );
nkeynes@359
  1006
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1007
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1008
                                }
nkeynes@359
  1009
                                break;
nkeynes@359
  1010
                            case 0x1:
nkeynes@359
  1011
                                { /* LDS.L @Rm+, MACL */
nkeynes@359
  1012
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1013
                                load_reg( R_EAX, Rm );
nkeynes@359
  1014
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1015
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1016
                                store_reg( R_EAX, Rm );
nkeynes@359
  1017
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1018
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1019
                                }
nkeynes@359
  1020
                                break;
nkeynes@359
  1021
                            case 0x2:
nkeynes@359
  1022
                                { /* LDS.L @Rm+, PR */
nkeynes@359
  1023
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1024
                                load_reg( R_EAX, Rm );
nkeynes@359
  1025
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1026
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1027
                                store_reg( R_EAX, Rm );
nkeynes@359
  1028
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1029
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1030
                                }
nkeynes@359
  1031
                                break;
nkeynes@359
  1032
                            case 0x3:
nkeynes@359
  1033
                                { /* LDC.L @Rm+, SGR */
nkeynes@359
  1034
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1035
                                load_reg( R_EAX, Rm );
nkeynes@359
  1036
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1037
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1038
                                store_reg( R_EAX, Rm );
nkeynes@359
  1039
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1040
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1041
                                }
nkeynes@359
  1042
                                break;
nkeynes@359
  1043
                            case 0x5:
nkeynes@359
  1044
                                { /* LDS.L @Rm+, FPUL */
nkeynes@359
  1045
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1046
                                load_reg( R_EAX, Rm );
nkeynes@359
  1047
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1048
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1049
                                store_reg( R_EAX, Rm );
nkeynes@359
  1050
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1051
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1052
                                }
nkeynes@359
  1053
                                break;
nkeynes@359
  1054
                            case 0x6:
nkeynes@359
  1055
                                { /* LDS.L @Rm+, FPSCR */
nkeynes@359
  1056
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1057
                                load_reg( R_EAX, Rm );
nkeynes@359
  1058
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1059
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1060
                                store_reg( R_EAX, Rm );
nkeynes@359
  1061
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1062
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1063
                                }
nkeynes@359
  1064
                                break;
nkeynes@359
  1065
                            case 0xF:
nkeynes@359
  1066
                                { /* LDC.L @Rm+, DBR */
nkeynes@359
  1067
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1068
                                load_reg( R_EAX, Rm );
nkeynes@359
  1069
                                MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1070
                                ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1071
                                store_reg( R_EAX, Rm );
nkeynes@359
  1072
                                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1073
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1074
                                }
nkeynes@359
  1075
                                break;
nkeynes@359
  1076
                            default:
nkeynes@359
  1077
                                UNDEF();
nkeynes@359
  1078
                                break;
nkeynes@359
  1079
                        }
nkeynes@359
  1080
                        break;
nkeynes@359
  1081
                    case 0x7:
nkeynes@359
  1082
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1083
                            case 0x0:
nkeynes@359
  1084
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1085
                                    case 0x0:
nkeynes@359
  1086
                                        { /* LDC.L @Rm+, SR */
nkeynes@359
  1087
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1088
                                        }
nkeynes@359
  1089
                                        break;
nkeynes@359
  1090
                                    case 0x1:
nkeynes@359
  1091
                                        { /* LDC.L @Rm+, GBR */
nkeynes@359
  1092
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1093
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1094
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1095
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1096
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1097
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1098
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1099
                                        }
nkeynes@359
  1100
                                        break;
nkeynes@359
  1101
                                    case 0x2:
nkeynes@359
  1102
                                        { /* LDC.L @Rm+, VBR */
nkeynes@359
  1103
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1104
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1105
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1106
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1107
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1108
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1109
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1110
                                        }
nkeynes@359
  1111
                                        break;
nkeynes@359
  1112
                                    case 0x3:
nkeynes@359
  1113
                                        { /* LDC.L @Rm+, SSR */
nkeynes@359
  1114
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1115
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1116
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1117
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1118
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1119
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1120
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1121
                                        }
nkeynes@359
  1122
                                        break;
nkeynes@359
  1123
                                    case 0x4:
nkeynes@359
  1124
                                        { /* LDC.L @Rm+, SPC */
nkeynes@359
  1125
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1126
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1127
                                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1128
                                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@359
  1129
                                        store_reg( R_EAX, Rm );
nkeynes@359
  1130
                                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359
  1131
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1132
                                        }
nkeynes@359
  1133
                                        break;
nkeynes@359
  1134
                                    default:
nkeynes@359
  1135
                                        UNDEF();
nkeynes@359
  1136
                                        break;
nkeynes@359
  1137
                                }
nkeynes@359
  1138
                                break;
nkeynes@359
  1139
                            case 0x1:
nkeynes@359
  1140
                                { /* LDC.L @Rm+, Rn_BANK */
nkeynes@359
  1141
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1142
                                }
nkeynes@359
  1143
                                break;
nkeynes@359
  1144
                        }
nkeynes@359
  1145
                        break;
nkeynes@359
  1146
                    case 0x8:
nkeynes@359
  1147
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1148
                            case 0x0:
nkeynes@359
  1149
                                { /* SHLL2 Rn */
nkeynes@359
  1150
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1151
                                load_reg( R_EAX, Rn );
nkeynes@359
  1152
                                SHL_imm8_r32( 2, R_EAX );
nkeynes@359
  1153
                                store_reg( R_EAX, Rn );
nkeynes@359
  1154
                                }
nkeynes@359
  1155
                                break;
nkeynes@359
  1156
                            case 0x1:
nkeynes@359
  1157
                                { /* SHLL8 Rn */
nkeynes@359
  1158
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1159
                                load_reg( R_EAX, Rn );
nkeynes@359
  1160
                                SHL_imm8_r32( 8, R_EAX );
nkeynes@359
  1161
                                store_reg( R_EAX, Rn );
nkeynes@359
  1162
                                }
nkeynes@359
  1163
                                break;
nkeynes@359
  1164
                            case 0x2:
nkeynes@359
  1165
                                { /* SHLL16 Rn */
nkeynes@359
  1166
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1167
                                load_reg( R_EAX, Rn );
nkeynes@359
  1168
                                SHL_imm8_r32( 16, R_EAX );
nkeynes@359
  1169
                                store_reg( R_EAX, Rn );
nkeynes@359
  1170
                                }
nkeynes@359
  1171
                                break;
nkeynes@359
  1172
                            default:
nkeynes@359
  1173
                                UNDEF();
nkeynes@359
  1174
                                break;
nkeynes@359
  1175
                        }
nkeynes@359
  1176
                        break;
nkeynes@359
  1177
                    case 0x9:
nkeynes@359
  1178
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1179
                            case 0x0:
nkeynes@359
  1180
                                { /* SHLR2 Rn */
nkeynes@359
  1181
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1182
                                load_reg( R_EAX, Rn );
nkeynes@359
  1183
                                SHR_imm8_r32( 2, R_EAX );
nkeynes@359
  1184
                                store_reg( R_EAX, Rn );
nkeynes@359
  1185
                                }
nkeynes@359
  1186
                                break;
nkeynes@359
  1187
                            case 0x1:
nkeynes@359
  1188
                                { /* SHLR8 Rn */
nkeynes@359
  1189
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1190
                                load_reg( R_EAX, Rn );
nkeynes@359
  1191
                                SHR_imm8_r32( 8, R_EAX );
nkeynes@359
  1192
                                store_reg( R_EAX, Rn );
nkeynes@359
  1193
                                }
nkeynes@359
  1194
                                break;
nkeynes@359
  1195
                            case 0x2:
nkeynes@359
  1196
                                { /* SHLR16 Rn */
nkeynes@359
  1197
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1198
                                load_reg( R_EAX, Rn );
nkeynes@359
  1199
                                SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1200
                                store_reg( R_EAX, Rn );
nkeynes@359
  1201
                                }
nkeynes@359
  1202
                                break;
nkeynes@359
  1203
                            default:
nkeynes@359
  1204
                                UNDEF();
nkeynes@359
  1205
                                break;
nkeynes@359
  1206
                        }
nkeynes@359
  1207
                        break;
nkeynes@359
  1208
                    case 0xA:
nkeynes@359
  1209
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1210
                            case 0x0:
nkeynes@359
  1211
                                { /* LDS Rm, MACH */
nkeynes@359
  1212
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1213
                                load_reg( R_EAX, Rm );
nkeynes@359
  1214
                                store_spreg( R_EAX, R_MACH );
nkeynes@359
  1215
                                }
nkeynes@359
  1216
                                break;
nkeynes@359
  1217
                            case 0x1:
nkeynes@359
  1218
                                { /* LDS Rm, MACL */
nkeynes@359
  1219
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1220
                                load_reg( R_EAX, Rm );
nkeynes@359
  1221
                                store_spreg( R_EAX, R_MACL );
nkeynes@359
  1222
                                }
nkeynes@359
  1223
                                break;
nkeynes@359
  1224
                            case 0x2:
nkeynes@359
  1225
                                { /* LDS Rm, PR */
nkeynes@359
  1226
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1227
                                load_reg( R_EAX, Rm );
nkeynes@359
  1228
                                store_spreg( R_EAX, R_PR );
nkeynes@359
  1229
                                }
nkeynes@359
  1230
                                break;
nkeynes@359
  1231
                            case 0x3:
nkeynes@359
  1232
                                { /* LDC Rm, SGR */
nkeynes@359
  1233
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1234
                                load_reg( R_EAX, Rm );
nkeynes@359
  1235
                                store_spreg( R_EAX, R_SGR );
nkeynes@359
  1236
                                }
nkeynes@359
  1237
                                break;
nkeynes@359
  1238
                            case 0x5:
nkeynes@359
  1239
                                { /* LDS Rm, FPUL */
nkeynes@359
  1240
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1241
                                load_reg( R_EAX, Rm );
nkeynes@359
  1242
                                store_spreg( R_EAX, R_FPUL );
nkeynes@359
  1243
                                }
nkeynes@359
  1244
                                break;
nkeynes@359
  1245
                            case 0x6:
nkeynes@359
  1246
                                { /* LDS Rm, FPSCR */
nkeynes@359
  1247
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1248
                                load_reg( R_EAX, Rm );
nkeynes@359
  1249
                                store_spreg( R_EAX, R_FPSCR );
nkeynes@359
  1250
                                }
nkeynes@359
  1251
                                break;
nkeynes@359
  1252
                            case 0xF:
nkeynes@359
  1253
                                { /* LDC Rm, DBR */
nkeynes@359
  1254
                                uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1255
                                load_reg( R_EAX, Rm );
nkeynes@359
  1256
                                store_spreg( R_EAX, R_DBR );
nkeynes@359
  1257
                                }
nkeynes@359
  1258
                                break;
nkeynes@359
  1259
                            default:
nkeynes@359
  1260
                                UNDEF();
nkeynes@359
  1261
                                break;
nkeynes@359
  1262
                        }
nkeynes@359
  1263
                        break;
nkeynes@359
  1264
                    case 0xB:
nkeynes@359
  1265
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1266
                            case 0x0:
nkeynes@359
  1267
                                { /* JSR @Rn */
nkeynes@359
  1268
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1269
                                }
nkeynes@359
  1270
                                break;
nkeynes@359
  1271
                            case 0x1:
nkeynes@359
  1272
                                { /* TAS.B @Rn */
nkeynes@359
  1273
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@361
  1274
                                load_reg( R_ECX, Rn );
nkeynes@361
  1275
                                MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361
  1276
                                TEST_r8_r8( R_AL, R_AL );
nkeynes@361
  1277
                                SETE_t();
nkeynes@361
  1278
                                OR_imm8_r8( 0x80, R_AL );
nkeynes@361
  1279
                                MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1280
                                }
nkeynes@359
  1281
                                break;
nkeynes@359
  1282
                            case 0x2:
nkeynes@359
  1283
                                { /* JMP @Rn */
nkeynes@359
  1284
                                uint32_t Rn = ((ir>>8)&0xF); 
nkeynes@359
  1285
                                }
nkeynes@359
  1286
                                break;
nkeynes@359
  1287
                            default:
nkeynes@359
  1288
                                UNDEF();
nkeynes@359
  1289
                                break;
nkeynes@359
  1290
                        }
nkeynes@359
  1291
                        break;
nkeynes@359
  1292
                    case 0xC:
nkeynes@359
  1293
                        { /* SHAD Rm, Rn */
nkeynes@359
  1294
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1295
                        /* Annoyingly enough, not directly convertible */
nkeynes@361
  1296
                        load_reg( R_EAX, Rn );
nkeynes@361
  1297
                        load_reg( R_ECX, Rm );
nkeynes@361
  1298
                        CMP_imm32_r32( 0, R_ECX );
nkeynes@361
  1299
                        JAE_rel8(9);
nkeynes@361
  1300
                                        
nkeynes@361
  1301
                        NEG_r32( R_ECX );      // 2
nkeynes@361
  1302
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1303
                        SAR_r32_CL( R_EAX );       // 2
nkeynes@361
  1304
                        JMP_rel8(5);               // 2
nkeynes@361
  1305
                        
nkeynes@361
  1306
                        AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
  1307
                        SHL_r32_CL( R_EAX );       // 2
nkeynes@361
  1308
                                        
nkeynes@361
  1309
                        store_reg( R_EAX, Rn );
nkeynes@359
  1310
                        }
nkeynes@359
  1311
                        break;
nkeynes@359
  1312
                    case 0xD:
nkeynes@359
  1313
                        { /* SHLD Rm, Rn */
nkeynes@359
  1314
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1315
                        }
nkeynes@359
  1316
                        break;
nkeynes@359
  1317
                    case 0xE:
nkeynes@359
  1318
                        switch( (ir&0x80) >> 7 ) {
nkeynes@359
  1319
                            case 0x0:
nkeynes@359
  1320
                                switch( (ir&0x70) >> 4 ) {
nkeynes@359
  1321
                                    case 0x0:
nkeynes@359
  1322
                                        { /* LDC Rm, SR */
nkeynes@359
  1323
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1324
                                        /* We need to be a little careful about SR */
nkeynes@359
  1325
                                        }
nkeynes@359
  1326
                                        break;
nkeynes@359
  1327
                                    case 0x1:
nkeynes@359
  1328
                                        { /* LDC Rm, GBR */
nkeynes@359
  1329
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1330
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1331
                                        store_spreg( R_EAX, R_GBR );
nkeynes@359
  1332
                                        }
nkeynes@359
  1333
                                        break;
nkeynes@359
  1334
                                    case 0x2:
nkeynes@359
  1335
                                        { /* LDC Rm, VBR */
nkeynes@359
  1336
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1337
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1338
                                        store_spreg( R_EAX, R_VBR );
nkeynes@359
  1339
                                        }
nkeynes@359
  1340
                                        break;
nkeynes@359
  1341
                                    case 0x3:
nkeynes@359
  1342
                                        { /* LDC Rm, SSR */
nkeynes@359
  1343
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1344
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1345
                                        store_spreg( R_EAX, R_SSR );
nkeynes@359
  1346
                                        }
nkeynes@359
  1347
                                        break;
nkeynes@359
  1348
                                    case 0x4:
nkeynes@359
  1349
                                        { /* LDC Rm, SPC */
nkeynes@359
  1350
                                        uint32_t Rm = ((ir>>8)&0xF); 
nkeynes@359
  1351
                                        load_reg( R_EAX, Rm );
nkeynes@359
  1352
                                        store_spreg( R_EAX, R_SPC );
nkeynes@359
  1353
                                        }
nkeynes@359
  1354
                                        break;
nkeynes@359
  1355
                                    default:
nkeynes@359
  1356
                                        UNDEF();
nkeynes@359
  1357
                                        break;
nkeynes@359
  1358
                                }
nkeynes@359
  1359
                                break;
nkeynes@359
  1360
                            case 0x1:
nkeynes@359
  1361
                                { /* LDC Rm, Rn_BANK */
nkeynes@359
  1362
                                uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
nkeynes@359
  1363
                                }
nkeynes@359
  1364
                                break;
nkeynes@359
  1365
                        }
nkeynes@359
  1366
                        break;
nkeynes@359
  1367
                    case 0xF:
nkeynes@359
  1368
                        { /* MAC.W @Rm+, @Rn+ */
nkeynes@359
  1369
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1370
                        }
nkeynes@359
  1371
                        break;
nkeynes@359
  1372
                }
nkeynes@359
  1373
                break;
nkeynes@359
  1374
            case 0x5:
nkeynes@359
  1375
                { /* MOV.L @(disp, Rm), Rn */
nkeynes@359
  1376
                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
nkeynes@361
  1377
                load_reg( R_ECX, Rm );
nkeynes@361
  1378
                ADD_imm8s_r32( disp, R_ECX );
nkeynes@361
  1379
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1380
                store_reg( R_EAX, Rn );
nkeynes@359
  1381
                }
nkeynes@359
  1382
                break;
nkeynes@359
  1383
            case 0x6:
nkeynes@359
  1384
                switch( ir&0xF ) {
nkeynes@359
  1385
                    case 0x0:
nkeynes@359
  1386
                        { /* MOV.B @Rm, Rn */
nkeynes@359
  1387
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1388
                        load_reg( R_ECX, Rm );
nkeynes@359
  1389
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1390
                        store_reg( R_ECX, Rn );
nkeynes@359
  1391
                        }
nkeynes@359
  1392
                        break;
nkeynes@359
  1393
                    case 0x1:
nkeynes@359
  1394
                        { /* MOV.W @Rm, Rn */
nkeynes@359
  1395
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1396
                        load_reg( R_ECX, Rm );
nkeynes@361
  1397
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1398
                        store_reg( R_EAX, Rn );
nkeynes@359
  1399
                        }
nkeynes@359
  1400
                        break;
nkeynes@359
  1401
                    case 0x2:
nkeynes@359
  1402
                        { /* MOV.L @Rm, Rn */
nkeynes@359
  1403
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1404
                        load_reg( R_ECX, Rm );
nkeynes@361
  1405
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1406
                        store_reg( R_EAX, Rn );
nkeynes@359
  1407
                        }
nkeynes@359
  1408
                        break;
nkeynes@359
  1409
                    case 0x3:
nkeynes@359
  1410
                        { /* MOV Rm, Rn */
nkeynes@359
  1411
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1412
                        load_reg( R_EAX, Rm );
nkeynes@359
  1413
                        store_reg( R_EAX, Rn );
nkeynes@359
  1414
                        }
nkeynes@359
  1415
                        break;
nkeynes@359
  1416
                    case 0x4:
nkeynes@359
  1417
                        { /* MOV.B @Rm+, Rn */
nkeynes@359
  1418
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1419
                        load_reg( R_ECX, Rm );
nkeynes@359
  1420
                        MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359
  1421
                        ADD_imm8s_r32( 1, R_EAX );
nkeynes@359
  1422
                        store_reg( R_EAX, Rm );
nkeynes@359
  1423
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1424
                        store_reg( R_EAX, Rn );
nkeynes@359
  1425
                        }
nkeynes@359
  1426
                        break;
nkeynes@359
  1427
                    case 0x5:
nkeynes@359
  1428
                        { /* MOV.W @Rm+, Rn */
nkeynes@359
  1429
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1430
                        load_reg( R_EAX, Rm );
nkeynes@361
  1431
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1432
                        ADD_imm8s_r32( 2, R_EAX );
nkeynes@361
  1433
                        store_reg( R_EAX, Rm );
nkeynes@361
  1434
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1435
                        store_reg( R_EAX, Rn );
nkeynes@359
  1436
                        }
nkeynes@359
  1437
                        break;
nkeynes@359
  1438
                    case 0x6:
nkeynes@359
  1439
                        { /* MOV.L @Rm+, Rn */
nkeynes@359
  1440
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1441
                        load_reg( R_EAX, Rm );
nkeynes@361
  1442
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1443
                        ADD_imm8s_r32( 4, R_EAX );
nkeynes@361
  1444
                        store_reg( R_EAX, Rm );
nkeynes@361
  1445
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1446
                        store_reg( R_EAX, Rn );
nkeynes@359
  1447
                        }
nkeynes@359
  1448
                        break;
nkeynes@359
  1449
                    case 0x7:
nkeynes@359
  1450
                        { /* NOT Rm, Rn */
nkeynes@359
  1451
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1452
                        load_reg( R_EAX, Rm );
nkeynes@359
  1453
                        NOT_r32( R_EAX );
nkeynes@359
  1454
                        store_reg( R_EAX, Rn );
nkeynes@359
  1455
                        }
nkeynes@359
  1456
                        break;
nkeynes@359
  1457
                    case 0x8:
nkeynes@359
  1458
                        { /* SWAP.B Rm, Rn */
nkeynes@359
  1459
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1460
                        load_reg( R_EAX, Rm );
nkeynes@359
  1461
                        XCHG_r8_r8( R_AL, R_AH );
nkeynes@359
  1462
                        store_reg( R_EAX, Rn );
nkeynes@359
  1463
                        }
nkeynes@359
  1464
                        break;
nkeynes@359
  1465
                    case 0x9:
nkeynes@359
  1466
                        { /* SWAP.W Rm, Rn */
nkeynes@359
  1467
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1468
                        load_reg( R_EAX, Rm );
nkeynes@359
  1469
                        MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1470
                        SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1471
                        SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1472
                        OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1473
                        store_reg( R_ECX, Rn );
nkeynes@359
  1474
                        }
nkeynes@359
  1475
                        break;
nkeynes@359
  1476
                    case 0xA:
nkeynes@359
  1477
                        { /* NEGC Rm, Rn */
nkeynes@359
  1478
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1479
                        load_reg( R_EAX, Rm );
nkeynes@359
  1480
                        XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
  1481
                        LDC_t();
nkeynes@359
  1482
                        SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1483
                        store_reg( R_ECX, Rn );
nkeynes@359
  1484
                        SETC_t();
nkeynes@359
  1485
                        }
nkeynes@359
  1486
                        break;
nkeynes@359
  1487
                    case 0xB:
nkeynes@359
  1488
                        { /* NEG Rm, Rn */
nkeynes@359
  1489
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1490
                        load_reg( R_EAX, Rm );
nkeynes@359
  1491
                        NEG_r32( R_EAX );
nkeynes@359
  1492
                        store_reg( R_EAX, Rn );
nkeynes@359
  1493
                        }
nkeynes@359
  1494
                        break;
nkeynes@359
  1495
                    case 0xC:
nkeynes@359
  1496
                        { /* EXTU.B Rm, Rn */
nkeynes@359
  1497
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1498
                        load_reg( R_EAX, Rm );
nkeynes@361
  1499
                        MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
  1500
                        store_reg( R_EAX, Rn );
nkeynes@359
  1501
                        }
nkeynes@359
  1502
                        break;
nkeynes@359
  1503
                    case 0xD:
nkeynes@359
  1504
                        { /* EXTU.W Rm, Rn */
nkeynes@359
  1505
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1506
                        load_reg( R_EAX, Rm );
nkeynes@361
  1507
                        MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1508
                        store_reg( R_EAX, Rn );
nkeynes@359
  1509
                        }
nkeynes@359
  1510
                        break;
nkeynes@359
  1511
                    case 0xE:
nkeynes@359
  1512
                        { /* EXTS.B Rm, Rn */
nkeynes@359
  1513
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1514
                        load_reg( R_EAX, Rm );
nkeynes@359
  1515
                        MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
  1516
                        store_reg( R_EAX, Rn );
nkeynes@359
  1517
                        }
nkeynes@359
  1518
                        break;
nkeynes@359
  1519
                    case 0xF:
nkeynes@359
  1520
                        { /* EXTS.W Rm, Rn */
nkeynes@359
  1521
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@361
  1522
                        load_reg( R_EAX, Rm );
nkeynes@361
  1523
                        MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
  1524
                        store_reg( R_EAX, Rn );
nkeynes@359
  1525
                        }
nkeynes@359
  1526
                        break;
nkeynes@359
  1527
                }
nkeynes@359
  1528
                break;
nkeynes@359
  1529
            case 0x7:
nkeynes@359
  1530
                { /* ADD #imm, Rn */
nkeynes@359
  1531
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1532
                load_reg( R_EAX, Rn );
nkeynes@359
  1533
                ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
  1534
                store_reg( R_EAX, Rn );
nkeynes@359
  1535
                }
nkeynes@359
  1536
                break;
nkeynes@359
  1537
            case 0x8:
nkeynes@359
  1538
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1539
                    case 0x0:
nkeynes@359
  1540
                        { /* MOV.B R0, @(disp, Rn) */
nkeynes@359
  1541
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1542
                        load_reg( R_EAX, 0 );
nkeynes@359
  1543
                        load_reg( R_ECX, Rn );
nkeynes@359
  1544
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1545
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1546
                        }
nkeynes@359
  1547
                        break;
nkeynes@359
  1548
                    case 0x1:
nkeynes@359
  1549
                        { /* MOV.W R0, @(disp, Rn) */
nkeynes@359
  1550
                        uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1551
                        load_reg( R_ECX, Rn );
nkeynes@361
  1552
                        load_reg( R_EAX, 0 );
nkeynes@361
  1553
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1554
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  1555
                        }
nkeynes@359
  1556
                        break;
nkeynes@359
  1557
                    case 0x4:
nkeynes@359
  1558
                        { /* MOV.B @(disp, Rm), R0 */
nkeynes@359
  1559
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
nkeynes@359
  1560
                        load_reg( R_ECX, Rm );
nkeynes@359
  1561
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1562
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1563
                        store_reg( R_EAX, 0 );
nkeynes@359
  1564
                        }
nkeynes@359
  1565
                        break;
nkeynes@359
  1566
                    case 0x5:
nkeynes@359
  1567
                        { /* MOV.W @(disp, Rm), R0 */
nkeynes@359
  1568
                        uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
nkeynes@361
  1569
                        load_reg( R_ECX, Rm );
nkeynes@361
  1570
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1571
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1572
                        store_reg( R_EAX, 0 );
nkeynes@359
  1573
                        }
nkeynes@359
  1574
                        break;
nkeynes@359
  1575
                    case 0x8:
nkeynes@359
  1576
                        { /* CMP/EQ #imm, R0 */
nkeynes@359
  1577
                        int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1578
                        load_reg( R_EAX, 0 );
nkeynes@359
  1579
                        CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
  1580
                        SETE_t();
nkeynes@359
  1581
                        }
nkeynes@359
  1582
                        break;
nkeynes@359
  1583
                    case 0x9:
nkeynes@359
  1584
                        { /* BT disp */
nkeynes@359
  1585
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1586
                        /* If true, result PC += 4 + disp. else result PC = pc+2 */
nkeynes@359
  1587
                          return pc + 2;
nkeynes@359
  1588
                        }
nkeynes@359
  1589
                        break;
nkeynes@359
  1590
                    case 0xB:
nkeynes@359
  1591
                        { /* BF disp */
nkeynes@359
  1592
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1593
                        }
nkeynes@359
  1594
                        break;
nkeynes@359
  1595
                    case 0xD:
nkeynes@359
  1596
                        { /* BT/S disp */
nkeynes@359
  1597
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1598
                        return pc + 4;
nkeynes@359
  1599
                        }
nkeynes@359
  1600
                        break;
nkeynes@359
  1601
                    case 0xF:
nkeynes@359
  1602
                        { /* BF/S disp */
nkeynes@359
  1603
                        int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
nkeynes@359
  1604
                        }
nkeynes@359
  1605
                        break;
nkeynes@359
  1606
                    default:
nkeynes@359
  1607
                        UNDEF();
nkeynes@359
  1608
                        break;
nkeynes@359
  1609
                }
nkeynes@359
  1610
                break;
nkeynes@359
  1611
            case 0x9:
nkeynes@359
  1612
                { /* MOV.W @(disp, PC), Rn */
nkeynes@359
  1613
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1614
                load_imm32( R_ECX, pc + disp + 4 );
nkeynes@361
  1615
                MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1616
                store_reg( R_EAX, Rn );
nkeynes@359
  1617
                }
nkeynes@359
  1618
                break;
nkeynes@359
  1619
            case 0xA:
nkeynes@359
  1620
                { /* BRA disp */
nkeynes@359
  1621
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@359
  1622
                }
nkeynes@359
  1623
                break;
nkeynes@359
  1624
            case 0xB:
nkeynes@359
  1625
                { /* BSR disp */
nkeynes@359
  1626
                int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
nkeynes@359
  1627
                }
nkeynes@359
  1628
                break;
nkeynes@359
  1629
            case 0xC:
nkeynes@359
  1630
                switch( (ir&0xF00) >> 8 ) {
nkeynes@359
  1631
                    case 0x0:
nkeynes@359
  1632
                        { /* MOV.B R0, @(disp, GBR) */
nkeynes@359
  1633
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1634
                        load_reg( R_EAX, 0 );
nkeynes@359
  1635
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1636
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1637
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1638
                        }
nkeynes@359
  1639
                        break;
nkeynes@359
  1640
                    case 0x1:
nkeynes@359
  1641
                        { /* MOV.W R0, @(disp, GBR) */
nkeynes@359
  1642
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1643
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1644
                        load_reg( R_EAX, 0 );
nkeynes@361
  1645
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1646
                        MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359
  1647
                        }
nkeynes@359
  1648
                        break;
nkeynes@359
  1649
                    case 0x2:
nkeynes@359
  1650
                        { /* MOV.L R0, @(disp, GBR) */
nkeynes@359
  1651
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1652
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1653
                        load_reg( R_EAX, 0 );
nkeynes@361
  1654
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1655
                        MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359
  1656
                        }
nkeynes@359
  1657
                        break;
nkeynes@359
  1658
                    case 0x3:
nkeynes@359
  1659
                        { /* TRAPA #imm */
nkeynes@359
  1660
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1661
                        }
nkeynes@359
  1662
                        break;
nkeynes@359
  1663
                    case 0x4:
nkeynes@359
  1664
                        { /* MOV.B @(disp, GBR), R0 */
nkeynes@359
  1665
                        uint32_t disp = (ir&0xFF); 
nkeynes@359
  1666
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1667
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@359
  1668
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1669
                        store_reg( R_EAX, 0 );
nkeynes@359
  1670
                        }
nkeynes@359
  1671
                        break;
nkeynes@359
  1672
                    case 0x5:
nkeynes@359
  1673
                        { /* MOV.W @(disp, GBR), R0 */
nkeynes@359
  1674
                        uint32_t disp = (ir&0xFF)<<1; 
nkeynes@361
  1675
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1676
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1677
                        MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361
  1678
                        store_reg( R_EAX, 0 );
nkeynes@359
  1679
                        }
nkeynes@359
  1680
                        break;
nkeynes@359
  1681
                    case 0x6:
nkeynes@359
  1682
                        { /* MOV.L @(disp, GBR), R0 */
nkeynes@359
  1683
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1684
                        load_spreg( R_ECX, R_GBR );
nkeynes@361
  1685
                        ADD_imm32_r32( disp, R_ECX );
nkeynes@361
  1686
                        MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1687
                        store_reg( R_EAX, 0 );
nkeynes@359
  1688
                        }
nkeynes@359
  1689
                        break;
nkeynes@359
  1690
                    case 0x7:
nkeynes@359
  1691
                        { /* MOVA @(disp, PC), R0 */
nkeynes@359
  1692
                        uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1693
                        load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
  1694
                        store_reg( R_ECX, 0 );
nkeynes@359
  1695
                        }
nkeynes@359
  1696
                        break;
nkeynes@359
  1697
                    case 0x8:
nkeynes@359
  1698
                        { /* TST #imm, R0 */
nkeynes@359
  1699
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1700
                        }
nkeynes@359
  1701
                        break;
nkeynes@359
  1702
                    case 0x9:
nkeynes@359
  1703
                        { /* AND #imm, R0 */
nkeynes@359
  1704
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1705
                        load_reg( R_EAX, 0 );
nkeynes@359
  1706
                        AND_imm32_r32(imm, R_EAX); 
nkeynes@359
  1707
                        store_reg( R_EAX, 0 );
nkeynes@359
  1708
                        }
nkeynes@359
  1709
                        break;
nkeynes@359
  1710
                    case 0xA:
nkeynes@359
  1711
                        { /* XOR #imm, R0 */
nkeynes@359
  1712
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1713
                        load_reg( R_EAX, 0 );
nkeynes@359
  1714
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1715
                        store_reg( R_EAX, 0 );
nkeynes@359
  1716
                        }
nkeynes@359
  1717
                        break;
nkeynes@359
  1718
                    case 0xB:
nkeynes@359
  1719
                        { /* OR #imm, R0 */
nkeynes@359
  1720
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1721
                        load_reg( R_EAX, 0 );
nkeynes@359
  1722
                        OR_imm32_r32(imm, R_EAX);
nkeynes@359
  1723
                        store_reg( R_EAX, 0 );
nkeynes@359
  1724
                        }
nkeynes@359
  1725
                        break;
nkeynes@359
  1726
                    case 0xC:
nkeynes@359
  1727
                        { /* TST.B #imm, @(R0, GBR) */
nkeynes@359
  1728
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1729
                        }
nkeynes@359
  1730
                        break;
nkeynes@359
  1731
                    case 0xD:
nkeynes@359
  1732
                        { /* AND.B #imm, @(R0, GBR) */
nkeynes@359
  1733
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1734
                        load_reg( R_EAX, 0 );
nkeynes@359
  1735
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1736
                        ADD_r32_r32( R_EAX, R_EBX );
nkeynes@359
  1737
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1738
                        AND_imm32_r32(imm, R_ECX );
nkeynes@359
  1739
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1740
                        }
nkeynes@359
  1741
                        break;
nkeynes@359
  1742
                    case 0xE:
nkeynes@359
  1743
                        { /* XOR.B #imm, @(R0, GBR) */
nkeynes@359
  1744
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1745
                        load_reg( R_EAX, 0 );
nkeynes@359
  1746
                        load_spreg( R_ECX, R_GBR );
nkeynes@359
  1747
                        ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1748
                        MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359
  1749
                        XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1750
                        MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359
  1751
                        }
nkeynes@359
  1752
                        break;
nkeynes@359
  1753
                    case 0xF:
nkeynes@359
  1754
                        { /* OR.B #imm, @(R0, GBR) */
nkeynes@359
  1755
                        uint32_t imm = (ir&0xFF); 
nkeynes@359
  1756
                        }
nkeynes@359
  1757
                        break;
nkeynes@359
  1758
                }
nkeynes@359
  1759
                break;
nkeynes@359
  1760
            case 0xD:
nkeynes@359
  1761
                { /* MOV.L @(disp, PC), Rn */
nkeynes@359
  1762
                uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
nkeynes@361
  1763
                load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@361
  1764
                MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361
  1765
                store_reg( R_EAX, 0 );
nkeynes@359
  1766
                }
nkeynes@359
  1767
                break;
nkeynes@359
  1768
            case 0xE:
nkeynes@359
  1769
                { /* MOV #imm, Rn */
nkeynes@359
  1770
                uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
nkeynes@359
  1771
                load_imm32( R_EAX, imm );
nkeynes@359
  1772
                store_reg( R_EAX, Rn );
nkeynes@359
  1773
                }
nkeynes@359
  1774
                break;
nkeynes@359
  1775
            case 0xF:
nkeynes@359
  1776
                switch( ir&0xF ) {
nkeynes@359
  1777
                    case 0x0:
nkeynes@359
  1778
                        { /* FADD FRm, FRn */
nkeynes@359
  1779
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1780
                        }
nkeynes@359
  1781
                        break;
nkeynes@359
  1782
                    case 0x1:
nkeynes@359
  1783
                        { /* FSUB FRm, FRn */
nkeynes@359
  1784
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1785
                        }
nkeynes@359
  1786
                        break;
nkeynes@359
  1787
                    case 0x2:
nkeynes@359
  1788
                        { /* FMUL FRm, FRn */
nkeynes@359
  1789
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1790
                        }
nkeynes@359
  1791
                        break;
nkeynes@359
  1792
                    case 0x3:
nkeynes@359
  1793
                        { /* FDIV FRm, FRn */
nkeynes@359
  1794
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1795
                        }
nkeynes@359
  1796
                        break;
nkeynes@359
  1797
                    case 0x4:
nkeynes@359
  1798
                        { /* FCMP/EQ FRm, FRn */
nkeynes@359
  1799
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1800
                        }
nkeynes@359
  1801
                        break;
nkeynes@359
  1802
                    case 0x5:
nkeynes@359
  1803
                        { /* FCMP/GT FRm, FRn */
nkeynes@359
  1804
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1805
                        }
nkeynes@359
  1806
                        break;
nkeynes@359
  1807
                    case 0x6:
nkeynes@359
  1808
                        { /* FMOV @(R0, Rm), FRn */
nkeynes@359
  1809
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1810
                        }
nkeynes@359
  1811
                        break;
nkeynes@359
  1812
                    case 0x7:
nkeynes@359
  1813
                        { /* FMOV FRm, @(R0, Rn) */
nkeynes@359
  1814
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1815
                        }
nkeynes@359
  1816
                        break;
nkeynes@359
  1817
                    case 0x8:
nkeynes@359
  1818
                        { /* FMOV @Rm, FRn */
nkeynes@359
  1819
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1820
                        }
nkeynes@359
  1821
                        break;
nkeynes@359
  1822
                    case 0x9:
nkeynes@359
  1823
                        { /* FMOV @Rm+, FRn */
nkeynes@359
  1824
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
nkeynes@359
  1825
                        }
nkeynes@359
  1826
                        break;
nkeynes@359
  1827
                    case 0xA:
nkeynes@359
  1828
                        { /* FMOV FRm, @Rn */
nkeynes@359
  1829
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1830
                        }
nkeynes@359
  1831
                        break;
nkeynes@359
  1832
                    case 0xB:
nkeynes@359
  1833
                        { /* FMOV FRm, @-Rn */
nkeynes@359
  1834
                        uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1835
                        }
nkeynes@359
  1836
                        break;
nkeynes@359
  1837
                    case 0xC:
nkeynes@359
  1838
                        { /* FMOV FRm, FRn */
nkeynes@359
  1839
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1840
                        }
nkeynes@359
  1841
                        break;
nkeynes@359
  1842
                    case 0xD:
nkeynes@359
  1843
                        switch( (ir&0xF0) >> 4 ) {
nkeynes@359
  1844
                            case 0x0:
nkeynes@359
  1845
                                { /* FSTS FPUL, FRn */
nkeynes@359
  1846
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1847
                                }
nkeynes@359
  1848
                                break;
nkeynes@359
  1849
                            case 0x1:
nkeynes@359
  1850
                                { /* FLDS FRm, FPUL */
nkeynes@359
  1851
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1852
                                }
nkeynes@359
  1853
                                break;
nkeynes@359
  1854
                            case 0x2:
nkeynes@359
  1855
                                { /* FLOAT FPUL, FRn */
nkeynes@359
  1856
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1857
                                }
nkeynes@359
  1858
                                break;
nkeynes@359
  1859
                            case 0x3:
nkeynes@359
  1860
                                { /* FTRC FRm, FPUL */
nkeynes@359
  1861
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1862
                                }
nkeynes@359
  1863
                                break;
nkeynes@359
  1864
                            case 0x4:
nkeynes@359
  1865
                                { /* FNEG FRn */
nkeynes@359
  1866
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1867
                                }
nkeynes@359
  1868
                                break;
nkeynes@359
  1869
                            case 0x5:
nkeynes@359
  1870
                                { /* FABS FRn */
nkeynes@359
  1871
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1872
                                }
nkeynes@359
  1873
                                break;
nkeynes@359
  1874
                            case 0x6:
nkeynes@359
  1875
                                { /* FSQRT FRn */
nkeynes@359
  1876
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1877
                                }
nkeynes@359
  1878
                                break;
nkeynes@359
  1879
                            case 0x7:
nkeynes@359
  1880
                                { /* FSRRA FRn */
nkeynes@359
  1881
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1882
                                }
nkeynes@359
  1883
                                break;
nkeynes@359
  1884
                            case 0x8:
nkeynes@359
  1885
                                { /* FLDI0 FRn */
nkeynes@359
  1886
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1887
                                }
nkeynes@359
  1888
                                break;
nkeynes@359
  1889
                            case 0x9:
nkeynes@359
  1890
                                { /* FLDI1 FRn */
nkeynes@359
  1891
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1892
                                }
nkeynes@359
  1893
                                break;
nkeynes@359
  1894
                            case 0xA:
nkeynes@359
  1895
                                { /* FCNVSD FPUL, FRn */
nkeynes@359
  1896
                                uint32_t FRn = ((ir>>8)&0xF); 
nkeynes@359
  1897
                                }
nkeynes@359
  1898
                                break;
nkeynes@359
  1899
                            case 0xB:
nkeynes@359
  1900
                                { /* FCNVDS FRm, FPUL */
nkeynes@359
  1901
                                uint32_t FRm = ((ir>>8)&0xF); 
nkeynes@359
  1902
                                }
nkeynes@359
  1903
                                break;
nkeynes@359
  1904
                            case 0xE:
nkeynes@359
  1905
                                { /* FIPR FVm, FVn */
nkeynes@359
  1906
                                uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
nkeynes@359
  1907
                                }
nkeynes@359
  1908
                                break;
nkeynes@359
  1909
                            case 0xF:
nkeynes@359
  1910
                                switch( (ir&0x100) >> 8 ) {
nkeynes@359
  1911
                                    case 0x0:
nkeynes@359
  1912
                                        { /* FSCA FPUL, FRn */
nkeynes@359
  1913
                                        uint32_t FRn = ((ir>>9)&0x7)<<1; 
nkeynes@359
  1914
                                        }
nkeynes@359
  1915
                                        break;
nkeynes@359
  1916
                                    case 0x1:
nkeynes@359
  1917
                                        switch( (ir&0x200) >> 9 ) {
nkeynes@359
  1918
                                            case 0x0:
nkeynes@359
  1919
                                                { /* FTRV XMTRX, FVn */
nkeynes@359
  1920
                                                uint32_t FVn = ((ir>>10)&0x3); 
nkeynes@359
  1921
                                                }
nkeynes@359
  1922
                                                break;
nkeynes@359
  1923
                                            case 0x1:
nkeynes@359
  1924
                                                switch( (ir&0xC00) >> 10 ) {
nkeynes@359
  1925
                                                    case 0x0:
nkeynes@359
  1926
                                                        { /* FSCHG */
nkeynes@359
  1927
                                                        }
nkeynes@359
  1928
                                                        break;
nkeynes@359
  1929
                                                    case 0x2:
nkeynes@359
  1930
                                                        { /* FRCHG */
nkeynes@359
  1931
                                                        }
nkeynes@359
  1932
                                                        break;
nkeynes@359
  1933
                                                    case 0x3:
nkeynes@359
  1934
                                                        { /* UNDEF */
nkeynes@359
  1935
                                                        }
nkeynes@359
  1936
                                                        break;
nkeynes@359
  1937
                                                    default:
nkeynes@359
  1938
                                                        UNDEF();
nkeynes@359
  1939
                                                        break;
nkeynes@359
  1940
                                                }
nkeynes@359
  1941
                                                break;
nkeynes@359
  1942
                                        }
nkeynes@359
  1943
                                        break;
nkeynes@359
  1944
                                }
nkeynes@359
  1945
                                break;
nkeynes@359
  1946
                            default:
nkeynes@359
  1947
                                UNDEF();
nkeynes@359
  1948
                                break;
nkeynes@359
  1949
                        }
nkeynes@359
  1950
                        break;
nkeynes@359
  1951
                    case 0xE:
nkeynes@359
  1952
                        { /* FMAC FR0, FRm, FRn */
nkeynes@359
  1953
                        uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
nkeynes@359
  1954
                        }
nkeynes@359
  1955
                        break;
nkeynes@359
  1956
                    default:
nkeynes@359
  1957
                        UNDEF();
nkeynes@359
  1958
                        break;
nkeynes@359
  1959
                }
nkeynes@359
  1960
                break;
nkeynes@359
  1961
        }
nkeynes@359
  1962
nkeynes@359
  1963
nkeynes@359
  1964
    return 0;
nkeynes@359
  1965
}
.