lxdream 0.9.1| filename | src/sh4/intc.h |
| changeset | 736:a02d1475ccfd |
| prev | 561:533f6b478071 |
| author | nkeynes |
| date | Sat Dec 27 02:59:35 2008 +0000 (15 years ago) |
| branch | lxdream-mem |
| permissions | -rw-r--r-- |
| last change | Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode, which tracks the field of the same name in sh4r - actually a little faster this way. Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR flag yet). Also fixed the failure to check the flags in the common case (code address returned by previous block) which took away the performance benefits, but oh well. |
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1 /**
2 * $Id$
3 *
4 * SH4 onboard interrupt controller (INTC) definitions.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef lxdream_intc_H
20 #define lxdream_intc_H 1
22 #include "sh4core.h"
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
28 #define INT_IRQ0 0 /* External Interrupt request 0 */
29 #define INT_IRQ1 1
30 #define INT_IRQ2 2
31 #define INT_IRQ3 3
32 #define INT_IRQ4 4
33 #define INT_IRQ5 5
34 #define INT_IRQ6 6
35 #define INT_IRQ7 7
36 #define INT_IRQ8 8
37 #define INT_IRQ9 9
38 #define INT_IRQ10 10
39 #define INT_IRQ11 11
40 #define INT_IRQ12 12
41 #define INT_IRQ13 13
42 #define INT_IRQ14 14
43 #define INT_NMI 15 /* Non-Maskable Interrupt */
44 #define INT_HUDI 16 /* Hitachi use debug interface */
45 #define INT_GPIO 17 /* I/O port interrupt */
46 #define INT_DMA_DMTE0 18 /* DMA transfer end 0 */
47 #define INT_DMA_DMTE1 19 /* DMA transfer end 1 */
48 #define INT_DMA_DMTE2 20 /* DMA transfer end 2 */
49 #define INT_DMA_DMTE3 21 /* DMA transfer end 3 */
50 #define INT_DMA_DMAE 22 /* DMA address error */
51 #define INT_TMU_TUNI0 23 /* Timer underflow interrupt 0 */
52 #define INT_TMU_TUNI1 24 /* Timer underflow interrupt 1 */
53 #define INT_TMU_TUNI2 25 /* Timer underflow interrupt 2 */
54 #define INT_TMU_TICPI2 26 /* Timer input capture interrupt */
55 #define INT_RTC_ATI 27 /* RTC Alarm interrupt */
56 #define INT_RTC_PRI 28 /* RTC periodic interrupt */
57 #define INT_RTC_CUI 29 /* RTC Carry-up interrupt */
58 #define INT_SCI_ERI 30 /* SCI receive-error interrupt */
59 #define INT_SCI_RXI 31 /* SCI receive-data-full interrupt */
60 #define INT_SCI_TXI 32 /* SCI transmit-data-empty interrupt */
61 #define INT_SCI_TEI 33 /* SCI transmit-end interrupt */
62 #define INT_SCIF_ERI 34 /* SCIF receive-error interrupt */
63 #define INT_SCIF_RXI 35 /* SCIF receive-data-full interrupt */
64 #define INT_SCIF_BRI 36 /* SCIF break interrupt request */
65 #define INT_SCIF_TXI 37 /* SCIF Transmit-data-empty interrupt */
66 #define INT_WDT_ITI 38 /* WDT Interval timer interval (CPG) */
67 #define INT_REF_RCMI 39 /* Compare-match interrupt */
68 #define INT_REF_ROVI 40 /* Refresh counter overflow interrupt */
70 #define INT_NUM_SOURCES 41
72 char *intc_get_interrupt_name( int which );
73 void intc_raise_interrupt( int which );
74 void intc_clear_interrupt( int which );
75 uint32_t intc_accept_interrupt( void );
76 void intc_reset( void );
77 void intc_mask_changed( void );
79 #ifdef __cplusplus
80 }
81 #endif
83 #endif /* !lxdream_intc_H */
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