filename | src/sh4/sh4dasm.in |
changeset | 873:cb3a8c502727 |
prev | 730:a0f02e769c2e |
next | 939:6f2302afeb89 |
author | nkeynes |
date | Sat Dec 27 02:59:35 2008 +0000 (15 years ago) |
branch | lxdream-mem |
permissions | -rw-r--r-- |
last change | Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode, which tracks the field of the same name in sh4r - actually a little faster this way. Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR flag yet). Also fixed the failure to check the flags in the common case (code address returned by previous block) which took away the performance benefits, but oh well. |
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1 /**
2 * $Id$
3 *
4 * SH4 CPU definition and disassembly functions
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "sh4/sh4core.h"
20 #include "sh4/sh4dasm.h"
21 #include "mem.h"
23 #define UNIMP(ir) snprintf( buf, len, "??? " )
26 const struct reg_desc_struct sh4_reg_map[] =
27 { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
28 {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
29 {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
30 {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
31 {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
32 {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
33 {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
34 {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
35 {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},
36 {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
37 {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
38 {"VBR",REG_INT, &sh4r.vbr},
39 {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
40 {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
41 {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
42 {NULL, 0, NULL} };
45 const struct cpu_desc_struct sh4_cpu_desc =
46 { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page,
47 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
48 (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
49 &sh4r.pc };
51 uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )
52 {
53 sh4addr_t addr = mmu_vma_to_phys_disasm(pc);
54 uint16_t ir = sh4_read_word(addr);
56 #define UNDEF(ir) snprintf( buf, len, "???? " );
57 #define RN(ir) ((ir&0x0F00)>>8)
58 #define RN_BANK(ir) ((ir&0x0070)>>4)
59 #define RM(ir) ((ir&0x00F0)>>4)
60 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *not* sign extended */
61 #define DISP8(ir) (ir&0x00FF)
62 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
63 #define UIMM8(ir) (ir&0x00FF)
64 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
65 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
66 #define FVN(ir) ((ir&0x0C00)>>10)
67 #define FVM(ir) ((ir&0x0300)>>8)
69 sprintf( opcode, "%02X %02X", ir&0xFF, ir>>8 );
71 %%
72 ADD Rm, Rn {: snprintf( buf, len, "ADD R%d, R%d", Rm, Rn ); :}
73 ADD #imm, Rn {: snprintf( buf, len, "ADD #%d, R%d", imm, Rn ); :}
74 ADDC Rm, Rn {: snprintf( buf, len, "ADDC R%d, R%d", Rm, Rn ); :}
75 ADDV Rm, Rn {: snprintf( buf, len, "ADDV R%d, R%d", Rm, Rn ); :}
76 AND Rm, Rn {: snprintf( buf, len, "AND R%d, R%d", Rm, Rn ); :}
77 AND #imm, R0 {: snprintf( buf, len, "AND #%d, R0", imm ); :}
78 AND.B #imm, @(R0, GBR) {: snprintf( buf, len, "AND.B #%d, @(R0, GBR)", imm ); :}
79 BF disp {: snprintf( buf, len, "BF $%xh", disp+pc+4 ); :}
80 BF/S disp {: snprintf( buf, len, "BF/S $%xh", disp+pc+4 ); :}
81 BRA disp {: snprintf( buf, len, "BRA $%xh", disp+pc+4 ); :}
82 BRAF Rn {: snprintf( buf, len, "BRAF R%d", Rn ); :}
83 BSR disp {: snprintf( buf, len, "BSR $%xh", disp+pc+4 ); :}
84 BSRF Rn {: snprintf( buf, len, "BSRF R%d", Rn ); :}
85 BT disp {: snprintf( buf, len, "BT $%xh", disp+pc+4 ); :}
86 BT/S disp {: snprintf( buf, len, "BT/S $%xh", disp+pc+4 ); :}
87 CLRMAC {: snprintf( buf, len, "CLRMAC " ); :}
88 CLRS {: snprintf( buf, len, "CLRS " ); :}
89 CLRT {: snprintf( buf, len, "CLRT " ); :}
90 CMP/EQ Rm, Rn {: snprintf( buf, len, "CMP/EQ R%d, R%d", Rm, Rn ); :}
91 CMP/EQ #imm, R0 {: snprintf( buf, len, "CMP/EQ #%d, R0", imm ); :}
92 CMP/GE Rm, Rn {: snprintf( buf, len, "CMP/GE R%d, R%d", Rm, Rn ); :}
93 CMP/GT Rm, Rn {: snprintf( buf, len, "CMP/GT R%d, R%d", Rm, Rn ); :}
94 CMP/HI Rm, Rn {: snprintf( buf, len, "CMP/HI R%d, R%d", Rm, Rn ); :}
95 CMP/HS Rm, Rn {: snprintf( buf, len, "CMP/HS R%d, R%d", Rm, Rn ); :}
96 CMP/PL Rn {: snprintf( buf, len, "CMP/PL R%d", Rn ); :}
97 CMP/PZ Rn {: snprintf( buf, len, "CMP/PZ R%d", Rn ); :}
98 CMP/STR Rm, Rn {: snprintf( buf, len, "CMP/STR R%d, R%d", Rm, Rn ); :}
99 DIV0S Rm, Rn {: snprintf( buf, len, "DIV0S R%d, R%d", Rm, Rn ); :}
100 DIV0U {: snprintf( buf, len, "DIV0U " ); :}
101 DIV1 Rm, Rn {: snprintf( buf, len, "DIV1 R%d, R%d", Rm, Rn ); :}
102 DMULS.L Rm, Rn {: snprintf( buf, len, "DMULS.L R%d, R%d", Rm, Rn ); :}
103 DMULU.L RM, Rn {: snprintf( buf, len, "DMULU.L R%d, R%d", Rm, Rn ); :}
104 DT Rn {: snprintf( buf, len, "DT R%d", Rn ); :}
105 EXTS.B Rm, Rn {: snprintf( buf, len, "EXTS.B R%d, R%d", Rm, Rn ); :}
106 EXTS.W Rm, Rn {: snprintf( buf, len, "EXTS.W R%d, R%d", Rm, Rn ); :}
107 EXTU.B Rm, Rn {: snprintf( buf, len, "EXTU.B R%d, R%d", Rm, Rn ); :}
108 EXTU.W Rm, Rn {: snprintf( buf, len, "EXTU.W R%d, R%d", Rm, Rn ); :}
109 FABS FRn {: snprintf( buf, len, "FABS FR%d", FRn ); :}
110 FADD FRm, FRn {: snprintf( buf, len, "FADD FR%d, FR%d", FRm, FRn ); :}
111 FCMP/EQ FRm, FRn {: snprintf( buf, len, "FCMP/EQ FR%d, FR%d", FRm, FRn ); :}
112 FCMP/GT FRm, FRn {: snprintf( buf, len, "FCMP/GT FR%d, FR%d", FRm, FRn ); :}
113 FCNVDS FRm, FPUL {: snprintf( buf, len, "FCNVDS FR%d, FPUL", FRm ); :}
114 FCNVSD FPUL, FRn {: snprintf( buf, len, "FCNVSD FPUL, FR%d", FRn ); :}
115 FDIV FRm, FRn {: snprintf( buf, len, "FDIV FR%d, FR%d", FRm, FRn ); :}
116 FIPR FVm, FVn {: snprintf( buf, len, "FIPR FV%d, FV%d", FVm, FVn ); :}
117 FLDS FRm, FPUL {: snprintf( buf, len, "FLDS FR%d, FPUL", FRm ); :}
118 FLDI0 FRn {: snprintf( buf, len, "FLDI0 FR%d", FRn ); :}
119 FLDI1 FRn {: snprintf( buf, len, "FLDI1 FR%d", FRn ); :}
120 FLOAT FPUL, FRn {: snprintf( buf, len, "FLOAT FPUL, FR%d", FRn ); :}
121 FMAC FR0, FRm, FRn {: snprintf( buf, len, "FMAC FR0, FR%d, FR%d", FRm, FRn ); :}
122 FMOV FRm, FRn {: snprintf( buf, len, "FMOV FR%d, FR%d", FRm, FRn ); :}
123 FMOV FRm, @Rn {: snprintf( buf, len, "FMOV FR%d, @R%d", FRm, Rn ); :}
124 FMOV FRm, @-Rn {: snprintf( buf, len, "FMOV FR%d, @-R%d", FRm, Rn ); :}
125 FMOV FRm, @(R0, Rn) {: snprintf( buf, len, "FMOV FR%d, @(R0, R%d)", FRm, Rn ); :}
126 FMOV @Rm, FRn {: snprintf( buf, len, "FMOV @R%d, FR%d", Rm, FRn ); :}
127 FMOV @Rm+, FRn {: snprintf( buf, len, "FMOV @R%d+, FR%d", Rm, FRn ); :}
128 FMOV @(R0, Rm), FRn {: snprintf( buf, len, "FMOV @(R0, R%d), FR%d", Rm, FRn ); :}
129 FMUL FRm, FRn {: snprintf( buf, len, "FMUL FR%d, FR%d", FRm, FRn ); :}
130 FNEG FRn {: snprintf( buf, len, "FNEG FR%d", FRn ); :}
131 FRCHG {: snprintf( buf, len, "FRCHG " ); :}
132 FSCA FPUL, FRn {: snprintf( buf, len, "FSCA FPUL, FR%d", FRn ); :}
133 FSCHG {: snprintf( buf, len, "FSCHG " ); :}
134 FSQRT FRn {: snprintf( buf, len, "FSQRT FR%d", FRn ); :}
135 FSRRA FRn {: snprintf( buf, len, "FSRRA FR%d", FRn ); :}
136 FSTS FPUL, FRn {: snprintf( buf, len, "FSTS FPUL, FR%d", FRn ); :}
137 FSUB FRm, FRn {: snprintf( buf, len, "FSUB FR%d, FR%d", FRm, FRn ); :}
138 FTRC FRm, FPUL {: snprintf( buf, len, "FTRC FR%d, FPUL", FRm ); :}
139 FTRV XMTRX, FVn {: snprintf( buf, len, "FTRV XMTRX, FV%d", FVn ); :}
140 JMP @Rn {: snprintf( buf, len, "JMP @R%d", Rn ); :}
141 JSR @Rn {: snprintf( buf, len, "JSR @R%d", Rn ); :}
142 LDC Rm, GBR {: snprintf( buf, len, "LDC R%d, GBR", Rm ); :}
143 LDC Rm, SR {: snprintf( buf, len, "LDC R%d, SR", Rm ); :}
144 LDC Rm, VBR {: snprintf( buf, len, "LDC R%d, VBR", Rm ); :}
145 LDC Rm, SSR {: snprintf( buf, len, "LDC R%d, SSR", Rm ); :}
146 LDC Rm, SGR {: snprintf( buf, len, "LDC R%d, SGR", Rm ); :}
147 LDC Rm, SPC {: snprintf( buf, len, "LDC R%d, SPC", Rm ); :}
148 LDC Rm, DBR {: snprintf( buf, len, "LDC R%d, DBR", Rm ); :}
149 LDC Rm, Rn_BANK {: snprintf( buf, len, "LDC R%d, R%d_BANK", Rm, Rn_BANK ); :}
150 LDS Rm, FPSCR {: snprintf( buf, len, "LDS R%d, FPSCR", Rm ); :}
151 LDS Rm, FPUL {: snprintf( buf, len, "LDS R%d, FPUL", Rm ); :}
152 LDS Rm, MACH {: snprintf( buf, len, "LDS R%d, MACH", Rm ); :}
153 LDS Rm, MACL {: snprintf( buf, len, "LDS R%d, MACL", Rm ); :}
154 LDS Rm, PR {: snprintf( buf, len, "LDS R%d, PR", Rm ); :}
155 LDC.L @Rm+, GBR {: snprintf( buf, len, "LDC.L @R%d+, GBR", Rm ); :}
156 LDC.L @Rm+, SR {: snprintf( buf, len, "LDC.L @R%d+, SR", Rm ); :}
157 LDC.L @Rm+, VBR {: snprintf( buf, len, "LDC.L @R%d+, VBR", Rm ); :}
158 LDC.L @Rm+, SSR {: snprintf( buf, len, "LDC.L @R%d+, SSR", Rm ); :}
159 LDC.L @Rm+, SGR {: snprintf( buf, len, "LDC.L @R%d+, SGR", Rm ); :}
160 LDC.L @Rm+, SPC {: snprintf( buf, len, "LDC.L @R%d+, SPC", Rm ); :}
161 LDC.L @Rm+, DBR {: snprintf( buf, len, "LDC.L @R%d+, DBR", Rm ); :}
162 LDC.L @Rm+, Rn_BANK{: snprintf( buf, len, "LDC.L @R%d+, @R%d+_BANK", Rm, Rn_BANK ); :}
163 LDS.L @Rm+, FPSCR{: snprintf( buf, len, "LDS.L @R%d+, FPSCR", Rm ); :}
164 LDS.L @Rm+, FPUL {: snprintf( buf, len, "LDS.L @R%d+, FPUL", Rm ); :}
165 LDS.L @Rm+, MACH {: snprintf( buf, len, "LDS.L @R%d+, MACH", Rm ); :}
166 LDS.L @Rm+, MACL {: snprintf( buf, len, "LDS.L @R%d+, MACL", Rm ); :}
167 LDS.L @Rm+, PR {: snprintf( buf, len, "LDS.L @R%d+, PR", Rm ); :}
168 LDTLB {: snprintf( buf, len, "LDTLB " ); :}
169 MAC.L @Rm+, @Rn+ {: snprintf( buf, len, "MAC.L @R%d+, @R%d+", Rm, Rn ); :}
170 MAC.W @Rm+, @Rn+ {: snprintf( buf, len, "MAC.W @R%d+, @R%d+", Rm, Rn ); :}
171 MOV Rm, Rn {: snprintf( buf, len, "MOV R%d, R%d", Rm, Rn ); :}
172 MOV #imm, Rn {: snprintf( buf, len, "MOV #%d, R%d", imm, Rn ); :}
173 MOV.B Rm, @Rn {: snprintf( buf, len, "MOV.B R%d, @R%d", Rm, Rn ); :}
174 MOV.B Rm, @-Rn {: snprintf( buf, len, "MOV.B R%d, @-R%d", Rm, Rn ); :}
175 MOV.B Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.B R%d, @(R0, R%d)", Rm, Rn ); :}
176 MOV.B R0, @(disp, GBR) {: snprintf( buf, len, "MOV.B R0, @(%d, GBR)", disp ); :}
177 MOV.B R0, @(disp, Rn) {: snprintf( buf, len, "MOV.B R0, @(%d, R%d)", disp, Rn ); :}
178 MOV.B @Rm, Rn {: snprintf( buf, len, "MOV.B @R%d, R%d", Rm, Rn ); :}
179 MOV.B @Rm+, Rn {: snprintf( buf, len, "MOV.B @R%d+, R%d", Rm, Rn ); :}
180 MOV.B @(R0, Rm), Rn {: snprintf( buf, len, "MOV.B @(R0, R%d), R%d", Rm, Rn ); :}
181 MOV.B @(disp, GBR), R0{: snprintf( buf, len, "MOV.B @(%d, GBR), R0", disp ); :}
182 MOV.B @(disp, Rm), R0 {: snprintf( buf, len, "MOV.B @(%d, R%d), R0", disp, Rm ); :}
183 MOV.L Rm, @Rn {: snprintf( buf, len, "MOV.L R%d, @R%d", Rm, Rn ); :}
184 MOV.L Rm, @-Rn {: snprintf( buf, len, "MOV.L R%d, @-R%d", Rm, Rn ); :}
185 MOV.L Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.L R%d, @(R0, R%d)", Rm, Rn ); :}
186 MOV.L R0, @(disp, GBR) {: snprintf( buf, len, "MOV.L R0, @(%d, GBR)", disp ); :}
187 MOV.L Rm, @(disp, Rn) {: snprintf( buf, len, "MOV.L R%d, @(%d, R%d)", Rm, disp, Rn ); :}
188 MOV.L @Rm, Rn {: snprintf( buf, len, "MOV.L @R%d, R%d", Rm, Rn ); :}
189 MOV.L @Rm+, Rn {: snprintf( buf, len, "MOV.L @R%d+, R%d", Rm, Rn ); :}
190 MOV.L @(R0, Rm), Rn {: snprintf( buf, len, "MOV.L @(R0, R%d), R%d", Rm, Rn ); :}
191 MOV.L @(disp, GBR), R0 {: snprintf( buf, len, "MOV.L @(%d, GBR), R0",disp ); :}
192 MOV.L @(disp, PC), Rn {: snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(addr&0xFFFFFFFC)+4) ); :}
193 MOV.L @(disp, Rm), Rn {: snprintf( buf, len, "MOV.L @(%d, R%d), R%d", disp, Rm, Rn ); :}
194 MOV.W Rm, @Rn {: snprintf( buf, len, "MOV.W R%d, @R%d", Rm, Rn ); :}
195 MOV.W Rm, @-Rn {: snprintf( buf, len, "MOV.W R%d, @-R%d", Rm, Rn ); :}
196 MOV.W Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.W R%d, @(R0, R%d)", Rm, Rn ); :}
197 MOV.W R0, @(disp, GBR) {: snprintf( buf, len, "MOV.W R0, @(%d, GBR)", disp); :}
198 MOV.W R0, @(disp, Rn) {: snprintf( buf, len, "MOV.W R0, @(%d, R%d)", disp, Rn ); :}
199 MOV.W @Rm, Rn {: snprintf( buf, len, "MOV.W @R%d, R%d", Rm, Rn ); :}
200 MOV.W @Rm+, Rn {: snprintf( buf, len, "MOV.W @R%d+, R%d", Rm, Rn ); :}
201 MOV.W @(R0, Rm), Rn {: snprintf( buf, len, "MOV.W @(R0, R%d), R%d", Rm, Rn ); :}
202 MOV.W @(disp, GBR), R0 {: snprintf( buf, len, "MOV.W @(%d, GBR), R0", disp ); :}
203 MOV.W @(disp, PC), Rn {: snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+addr+4) ); :}
204 MOV.W @(disp, Rm), R0 {: snprintf( buf, len, "MOV.W @(%d, R%d), R0", disp, Rm ); :}
205 MOVA @(disp, PC), R0 {: snprintf( buf, len, "MOVA @($%xh), R0", disp + (pc&0xFFFFFFFC) + 4 ); :}
206 MOVCA.L R0, @Rn {: snprintf( buf, len, "MOVCA.L R0, @R%d", Rn ); :}
207 MOVT Rn {: snprintf( buf, len, "MOVT R%d", Rn ); :}
208 MUL.L Rm, Rn {: snprintf( buf, len, "MUL.L R%d, R%d", Rm, Rn ); :}
209 MULS.W Rm, Rn {: snprintf( buf, len, "MULS.W R%d, R%d", Rm, Rn ); :}
210 MULU.W Rm, Rn {: snprintf( buf, len, "MULU.W R%d, R%d", Rm, Rn ); :}
211 NEG Rm, Rn {: snprintf( buf, len, "NEG R%d, R%d", Rm, Rn ); :}
212 NEGC Rm, Rn {: snprintf( buf, len, "NEGC R%d, R%d", Rm, Rn ); :}
213 NOP {: snprintf( buf, len, "NOP " ); :}
214 NOT Rm, Rn {: snprintf( buf, len, "NOT R%d, R%d", Rm, Rn ); :}
215 OCBI @Rn {: snprintf( buf, len, "OCBI @R%d", Rn ); :}
216 OCBP @Rn {: snprintf( buf, len, "OCBP @R%d", Rn ); :}
217 OCBWB @Rn {: snprintf( buf, len, "OCBWB @R%d", Rn ); :}
218 OR Rm, Rn {: snprintf( buf, len, "OR R%d, R%d", Rm, Rn ); :}
219 OR #imm, R0 {: snprintf( buf, len, "OR #%d, R0", imm ); :}
220 OR.B #imm, @(R0, GBR) {: snprintf( buf, len, "OR.B #%d, @(R0, GBR)", imm ); :}
221 PREF @Rn {: snprintf( buf, len, "PREF R%d", Rn ); :}
222 ROTCL Rn {: snprintf( buf, len, "ROTCL R%d", Rn ); :}
223 ROTCR Rn {: snprintf( buf, len, "ROTCR R%d", Rn ); :}
224 ROTL Rn {: snprintf( buf, len, "ROTL R%d", Rn ); :}
225 ROTR Rn {: snprintf( buf, len, "ROTR R%d", Rn ); :}
226 RTE {: snprintf( buf, len, "RTE " ); :}
227 RTS {: snprintf( buf, len, "RTS " ); :}
228 SETS {: snprintf( buf, len, "SETS " ); :}
229 SETT {: snprintf( buf, len, "SETT " ); :}
230 SHAD Rm, Rn {: snprintf( buf, len, "SHAD R%d, R%d", Rm, Rn ); :}
231 SHAL Rn {: snprintf( buf, len, "SHAL R%d", Rn ); :}
232 SHAR Rn {: snprintf( buf, len, "SHAR R%d", Rn ); :}
233 SHLD Rm, Rn {: snprintf( buf, len, "SHLD R%d, R%d", Rm, Rn ); :}
234 SHLL Rn {: snprintf( buf, len, "SHLL R%d", Rn ); :}
235 SHLL2 Rn {: snprintf( buf, len, "SHLL2 R%d", Rn ); :}
236 SHLL8 Rn {: snprintf( buf, len, "SHLL8 R%d", Rn ); :}
237 SHLL16 Rn {: snprintf( buf, len, "SHLL16 R%d", Rn ); :}
238 SHLR Rn {: snprintf( buf, len, "SHLR R%d", Rn ); :}
239 SHLR2 Rn {: snprintf( buf, len, "SHLR2 R%d", Rn ); :}
240 SHLR8 Rn {: snprintf( buf, len, "SHLR8 R%d", Rn ); :}
241 SHLR16 Rn {: snprintf( buf, len, "SHLR16 R%d", Rn ); :}
242 SLEEP {: snprintf( buf, len, "SLEEP " ); :}
243 STC SR, Rn {: snprintf( buf, len, "STC SR, R%d", Rn ); :}
244 STC GBR, Rn {: snprintf( buf, len, "STC GBR, R%d", Rn ); :}
245 STC VBR, Rn {: snprintf( buf, len, "STC VBR, R%d", Rn ); :}
246 STC SSR, Rn {: snprintf( buf, len, "STC SSR, R%d", Rn ); :}
247 STC SPC, Rn {: snprintf( buf, len, "STC SPC, R%d", Rn ); :}
248 STC SGR, Rn {: snprintf( buf, len, "STC SGR, R%d", Rn ); :}
249 STC DBR, Rn {: snprintf( buf, len, "STC DBR, R%d", Rn ); :}
250 STC Rm_BANK, Rn {: snprintf( buf, len, "STC R%d_BANK, R%d", Rm_BANK, Rn ); :}
251 STS FPSCR, Rn {: snprintf( buf, len, "STS FPSCR, R%d", Rn ); :}
252 STS FPUL, Rn {: snprintf( buf, len, "STS FPUL, R%d", Rn ); :}
253 STS MACH, Rn {: snprintf( buf, len, "STS MACH, R%d", Rn ); :}
254 STS MACL, Rn {: snprintf( buf, len, "STS MACL, R%d", Rn ); :}
255 STS PR, Rn {: snprintf( buf, len, "STS PR, R%d", Rn ); :}
256 STC.L SR, @-Rn {: snprintf( buf, len, "STC.L SR, @-R%d", Rn ); :}
257 STC.L GBR, @-Rn {: snprintf( buf, len, "STC.L GBR, @-R%d", Rn ); :}
258 STC.L VBR, @-Rn {: snprintf( buf, len, "STC.L VBR, @-R%d", Rn ); :}
259 STC.L SSR, @-Rn {: snprintf( buf, len, "STC.L SSR, @-R%d", Rn ); :}
260 STC.L SPC, @-Rn {: snprintf( buf, len, "STC.L SPC, @-R%d", Rn ); :}
261 STC.L SGR, @-Rn {: snprintf( buf, len, "STC.L SGR, @-R%d", Rn ); :}
262 STC.L DBR, @-Rn {: snprintf( buf, len, "STC.L DBR, @-R%d", Rn ); :}
263 STC.L Rm_BANK, @-Rn {: snprintf( buf, len, "STC.L @-R%d_BANK, @-R%d", Rm_BANK, Rn ); :}
264 STS.L FPSCR, @-Rn{: snprintf( buf, len, "STS.L FPSCR, @-R%d", Rn ); :}
265 STS.L FPUL, @-Rn {: snprintf( buf, len, "STS.L FPUL, @-R%d", Rn ); :}
266 STS.L MACH, @-Rn {: snprintf( buf, len, "STS.L MACH, @-R%d", Rn ); :}
267 STS.L MACL, @-Rn {: snprintf( buf, len, "STS.L MACL, @-R%d", Rn ); :}
268 STS.L PR, @-Rn {: snprintf( buf, len, "STS.L PR, @-R%d", Rn ); :}
269 SUB Rm, Rn {: snprintf( buf, len, "SUB R%d, R%d", Rm, Rn ); :}
270 SUBC Rm, Rn {: snprintf( buf, len, "SUBC R%d, R%d", Rm, Rn ); :}
271 SUBV Rm, Rn {: snprintf( buf, len, "SUBV R%d, R%d", Rm, Rn ); :}
272 SWAP.B Rm, Rn {: snprintf( buf, len, "SWAP.B R%d, R%d", Rm, Rn ); :}
273 SWAP.W Rm, Rn {: snprintf( buf, len, "SWAP.W R%d, R%d", Rm, Rn ); :}
274 TAS.B @Rn {: snprintf( buf, len, "TAS.B R%d", Rn ); :}
275 TRAPA #imm {: snprintf( buf, len, "TRAPA #%d", imm ); :}
276 TST Rm, Rn {: snprintf( buf, len, "TST R%d, R%d", Rm, Rn ); :}
277 TST #imm, R0 {: snprintf( buf, len, "TST #%d, R0", imm ); :}
278 TST.B #imm, @(R0, GBR) {: snprintf( buf, len, "TST.B #%d, @(R0, GBR)", imm ); :}
279 XOR Rm, Rn {: snprintf( buf, len, "XOR R%d, R%d", Rm, Rn ); :}
280 XOR #imm, R0 {: snprintf( buf, len, "XOR #%d, R0", imm ); :}
281 XOR.B #imm, @(R0, GBR) {: snprintf( buf, len, "XOR.B #%d, @(R0, GBR)", imm ); :}
282 XTRCT Rm, Rn {: snprintf( buf, len, "XTRCT R%d, R%d", Rm, Rn ); :}
283 UNDEF {: snprintf( buf, len, "UNDEF " ); :}
284 %%
285 return pc+2;
286 }
289 void sh4_disasm_region( FILE *f, int from, int to )
290 {
291 int pc;
292 char buf[80];
293 char opcode[16];
295 for( pc = from; pc < to; pc+=2 ) {
296 buf[0] = '\0';
297 sh4_disasm_instruction( pc,
298 buf, sizeof(buf), opcode );
299 fprintf( f, " %08x: %s %s\n", pc, opcode, buf );
300 }
301 }
303 void sh4_dump_region( int from, int to )
304 {
305 sh4_disasm_region( stdout, from, to );
306 }
.