lxdream 0.9.1revision 1012:0b8cc74ac83a
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raw | bz2 | zip | gz | changeset | 1012:0b8cc74ac83a |
| parent | 1011:fdd58619b760 |
| child | 1013:76196dbc804a |
| author | nkeynes |
| date | Sun Apr 19 05:14:19 2009 +0000 (15 years ago) |
| branch | xlat-refactor |
Remove branch instructions and replace with direct modification of PC + EXIT
Add MIN/MAX instructions (for bound checks)
Implement x86_target_is_legal
Correct a few sh4 instructions
Add MIN/MAX instructions (for bound checks)
Implement x86_target_is_legal
Correct a few sh4 instructions
1.1 --- a/src/sh4/sh4xir.in Sun Apr 12 07:24:45 2009 +00001.2 +++ b/src/sh4/sh4xir.in Sun Apr 19 05:14:19 2009 +00001.3 @@ -139,7 +139,7 @@1.4 XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );1.5 }1.6 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.7 - XOP1S( OP_BR, R_SPC )->next = NULL;1.8 + XOP0( OP_EXIT )->next = NULL;1.9 start->prev = NULL;1.10 return start;1.11 }1.12 @@ -160,7 +160,7 @@1.13 XOP2IS( OP_ADD, pc - xbb->pc_begin, R_SPC );1.14 }1.15 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.16 - XOP1S( OP_BR, R_SPC )->next = NULL;1.17 + XOP0( OP_EXIT )->next = NULL;1.19 ins->next = xbb->ir_ptr;1.20 xbb->ir_ptr->prev = ins;1.21 @@ -214,7 +214,7 @@1.22 XOP2IS( OP_MOV, 1, R_DELAY_SLOT ); \1.23 XOP0( OP_BARRIER ); \1.24 XOPCALL0( sh4_execute_instruction ); \1.25 - XOP1S( OP_BR, R_PC ); \1.26 + XOP0( OP_EXIT ); \1.27 } while(0)1.30 @@ -644,8 +644,7 @@1.31 // behaviour to confirm) Unlikely to be anyone depending on this1.32 // behaviour though.1.33 sh4ptr_t ptr = GET_ICACHE_PTR(target);1.34 - XOP2PT( OP_LOADPTRL, ptr, REG_TMP0 );1.35 - XOP2TS( OP_MOVSX16, REG_TMP0, R_R(Rn) );1.36 + XOP2PT( OP_LOADPTRW, ptr, REG_TMP0 );1.37 } else {1.38 // Note: we use sh4r.pc for the calc as we could be running at a1.39 // different virtual address than the translation was done with,1.40 @@ -794,9 +793,15 @@1.41 FTRC FRm, FPUL {:1.42 CHECKFPUEN();1.43 if( sh4_xir.double_prec ) {1.44 - XOP2SS( OP_DTOI, R_DR(FRm), R_FPUL );1.45 + XOP2SS( OP_MOVQ, R_DR(FRm), REG_TMPD0 );1.46 + XOP2FS( OP_MAXD, (double)0x8000000000000000, REG_TMPD0 );1.47 + XOP2FS( OP_MIND, (double)0x7FFFFFFFFFFFFFFF, REG_TMPD0 );1.48 + XOP2SS( OP_DTOI, REG_TMPD0, R_FPUL );1.49 } else {1.50 - XOP2SS( OP_FTOI, R_FR(FRm), R_FPUL );1.51 + XOP2SS( OP_MOV, R_FR(FRm), REG_TMPF0 );1.52 + XOP2FS( OP_MAXF, (double)0x80000000, REG_TMPF0 );1.53 + XOP2FS( OP_MINF, (double)0x7FFFFFFF, REG_TMPF0 );1.54 + XOP2SS( OP_FTOI, REG_TMPF0, R_FPUL );1.55 }1.56 :}1.57 FLDS FRm, FPUL {:1.58 @@ -1181,7 +1186,9 @@1.59 } else {1.60 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.61 XOP2IS( OP_CMP, 0, R_T );1.62 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );1.63 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );1.64 + XOP2ISCC( OP_ADD, CC_NE, pc+2-xbb->pc_begin, R_PC );1.65 + XOP0( OP_EXIT );1.66 }1.67 return 2;1.68 :}1.69 @@ -1191,8 +1198,11 @@1.70 return 2;1.71 } else {1.72 if( UNTRANSLATABLE(pc+2 ) ) {1.73 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.74 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );1.75 XOP2IS( OP_CMP, 0, R_T );1.76 - XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );1.77 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_NEW_PC );1.78 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_NEW_PC );1.79 EMU_DELAY_SLOT();1.80 return 2;1.81 } else {1.82 @@ -1201,7 +1211,9 @@1.83 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.84 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.85 XOP2IT( OP_CMP, 0, REG_TMP2 );1.86 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );1.87 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );1.88 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_PC );1.89 + XOP0( OP_EXIT );1.90 }1.91 return 4;1.92 }1.93 @@ -1213,7 +1225,9 @@1.94 } else {1.95 XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.96 XOP2IS( OP_CMP, 1, R_T );1.97 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );1.98 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );1.99 + XOP2ISCC( OP_ADD, CC_NE, pc+2-xbb->pc_begin, R_PC );1.100 + XOP0( OP_EXIT );1.101 }1.102 return 2;1.103 :}1.104 @@ -1223,8 +1237,11 @@1.105 return 2;1.106 } else {1.107 if( UNTRANSLATABLE(pc+2 ) ) {1.108 + XOP2IS( OP_ADD, (pc+2 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.109 + XOP2SS( OP_MOV, R_PC, R_NEW_PC );1.110 XOP2IS( OP_CMP, 1, R_T );1.111 - XOP2IICC( OP_BRCONDDEL, CC_EQ, disp+pc+4-xbb->pc_begin, pc+2-xbb->pc_begin );1.112 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_NEW_PC );1.113 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_NEW_PC );1.114 EMU_DELAY_SLOT();1.115 return 2;1.116 } else {1.117 @@ -1233,7 +1250,9 @@1.118 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.119 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.120 XOP2IT( OP_CMP, 1, REG_TMP2 );1.121 - XOP2IICC( OP_BRCOND, CC_EQ, disp+pc+4-xbb->pc_begin, pc+4-xbb->pc_begin );1.122 + XOP2ISCC( OP_ADD, CC_EQ, disp+pc+4-xbb->pc_begin, R_PC );1.123 + XOP2ISCC( OP_ADD, CC_NE, pc+4-xbb->pc_begin, R_PC );1.124 + XOP0( OP_EXIT );1.125 }1.126 return 4;1.127 }1.128 @@ -1253,7 +1272,8 @@1.129 sh4_decode_instruction( xbb, pc+2, TRUE );1.130 if( xbb->ir_ptr->prev == NULL || !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.131 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.132 - XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );1.133 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_PC );1.134 + XOP0( OP_EXIT );1.135 }1.136 return 4;1.137 }1.138 @@ -1264,9 +1284,9 @@1.139 SLOTILLEGAL();1.140 return 2;1.141 } else {1.142 - XOP2ST( OP_MOV, R_R(Rn), REG_TMP2 );1.143 - XOP2ST( OP_ADD, R_PC, REG_TMP2 );1.144 + XOP2ST( OP_MOV, R_PC, REG_TMP2 );1.145 XOP2IT( OP_ADD, pc - xbb->pc_begin + 4, REG_TMP2 );1.146 + XOP2ST( OP_ADD, R_R(Rn), REG_TMP2 );1.147 if( UNTRANSLATABLE(pc+2) ) {1.148 XOP2TS( OP_MOV, REG_TMP2, R_NEW_PC );1.149 EMU_DELAY_SLOT();1.150 @@ -1275,7 +1295,8 @@1.151 sh4_decode_instruction( xbb, pc + 2, TRUE );1.152 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.153 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.154 - XOP1T( OP_BR, REG_TMP2 );1.155 + XOP2TS( OP_MOV, REG_TMP2, R_PC );1.156 + XOP0( OP_EXIT );1.157 }1.158 return 4;1.159 }1.160 @@ -1297,7 +1318,8 @@1.161 sh4_decode_instruction( xbb, pc+2, TRUE );1.162 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.163 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.164 - XOP1I( OP_BRREL, pc+disp+4-xbb->pc_begin );1.165 + XOP2IS( OP_ADD, pc+disp+4-xbb->pc_begin, R_PC );1.166 + XOP0( OP_EXIT );1.167 }1.168 return 4;1.169 }1.170 @@ -1321,7 +1343,8 @@1.171 sh4_decode_instruction( xbb, pc+2, TRUE );1.172 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.173 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.174 - XOP1T( OP_BR, REG_TMP2 );1.175 + XOP2TS( OP_ADD, REG_TMP2, R_PC );1.176 + XOP0( OP_EXIT );1.177 }1.178 return 4;1.179 }1.180 @@ -1341,7 +1364,8 @@1.181 sh4_decode_instruction( xbb, pc+2, TRUE );1.182 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.183 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.184 - XOP1T( OP_BR, REG_TMP2 );1.185 + XOP2TS( OP_MOV, REG_TMP2, R_PC );1.186 + XOP0( OP_EXIT );1.187 }1.188 return 4;1.189 }1.190 @@ -1363,7 +1387,8 @@1.191 sh4_decode_instruction( xbb, pc+2, TRUE );1.192 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.193 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.194 - XOP1T( OP_BR, REG_TMP2 );1.195 + XOP2TS( OP_MOV, REG_TMP2, R_PC );1.196 + XOP0( OP_EXIT );1.197 }1.198 return 4;1.199 }1.200 @@ -1385,7 +1410,8 @@1.201 sh4_decode_instruction( xbb, pc+2, TRUE );1.202 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.203 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.204 - XOP1T( OP_BR, REG_TMP2 );1.205 + XOP2TS( OP_MOV, REG_TMP2, R_PC );1.206 + XOP0( OP_EXIT );1.207 }1.208 return 4;1.209 }1.210 @@ -1405,14 +1431,25 @@1.211 sh4_decode_instruction( xbb, pc+2, TRUE );1.212 if( !XOP_IS_TERMINATOR( xbb->ir_ptr->prev ) ) {1.213 XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.214 - XOP1T( OP_BR, REG_TMP2 );1.215 + XOP2TS( OP_MOV, REG_TMP2, R_PC );1.216 + XOP0( OP_EXIT );1.217 }1.218 return 4;1.219 }1.220 }1.221 :}1.222 -TRAPA #imm {: XOPCALL1I( sh4_raise_trap, imm ); return pc+2; :}1.223 -SLEEP {: XOPCALL0( sh4_sleep ); return pc+2; :}1.224 +TRAPA #imm {:1.225 + XOP2IS( OP_ADD, (pc+4 - xbb->pc_begin) * sh4_cpu_period, R_SLICE_CYCLE );1.226 + XOP2IS( OP_ADD, pc+4-xbb->pc_begin, R_PC );1.227 + XOPCALL1I( sh4_raise_trap, imm );1.228 + XOP0( OP_EXIT );1.229 + return 2;1.230 +:}1.231 +SLEEP {:1.232 + XOPCALL0( sh4_sleep );1.233 + XOP0( OP_EXIT);1.234 + return 2;1.235 +:}1.236 UNDEF {: UNDEF(ir); :}1.237 NOP {: /* Do nothing */ :}
2.1 --- a/src/xlat/x86/x86gen.c Sun Apr 12 07:24:45 2009 +00002.2 +++ b/src/xlat/x86/x86gen.c Sun Apr 19 05:14:19 2009 +00002.3 @@ -431,11 +431,6 @@2.4 case OP_ITOF:2.5 case OP_FTOI:2.7 - case OP_BRCOND:2.8 - case OP_BRREL:2.9 - case OP_BR:2.10 - case OP_BRCONDDEL:2.11 -2.12 case OP_CALL0:2.13 if( XOP_IS_IMM(it,0) ) {2.14 CALL_imm32( XOP_INT(it,0) );
3.1 --- a/src/xlat/x86/x86target.c Sun Apr 12 07:24:45 2009 +00003.2 +++ b/src/xlat/x86/x86target.c Sun Apr 19 05:14:19 2009 +00003.3 @@ -52,17 +52,58 @@3.4 static gboolean x86_target_is_legal( xir_opcode_t op, xir_operand_form_t arg0, xir_operand_form_t arg1 )3.5 {3.6 switch( op ) {3.7 - case OP_DEC: case OP_ST: case OP_LD:3.8 - case OP_SHUFFLE:3.9 - return arg0 == IMMEDIATE_OPERAND && arg1 == DEST_OPERAND;3.10 + case OP_DEC: case OP_ST: case OP_LD: case OP_RESTFLAGS: case OP_SAVEFLAGS:3.11 + return arg0 == DEST_OPERAND;3.12 +3.13 + /* XLAT, LOADPTR* need real registers */3.14 + case OP_LOADPTRL: case OP_LOADPTRQ:3.15 + case OP_XLAT: case OP_CALLLUT:3.16 + return (arg0 == IMMEDIATE_OPERAND || arg0 == DEST_OPERAND) &&3.17 + arg1 == DEST_OPERAND;3.18 +3.19 + /* Most SSE instructions plus MOVSX, MUL, and a few others must have a3.20 + * register target operand3.21 + */3.22 + case OP_MOVSX8: case OP_MOVSX16: case OP_MOVSX32: case OP_MOVZX8:3.23 + case OP_MOVZX16: case OP_MOVZX32: case OP_MUL: case OP_MULS: case OP_MULQ:3.24 + case OP_MULQS: case OP_SHUFFLE:3.25 + case OP_ABSD: case OP_ABSF: case OP_ABSV: case OP_ADDD: case OP_ADDF:3.26 + case OP_ADDV: case OP_CMPD: case OP_DIVD: case OP_DIVF: case OP_DIVV:3.27 + case OP_MULD: case OP_MULF: case OP_MULV: case OP_NEGD: case OP_NEGF:3.28 + case OP_NEGV: case OP_SQRTD: case OP_SQRTF: case OP_SQRTV:3.29 + case OP_RSQRTD: case OP_RSQRTF: case OP_RSQRTV: case OP_SUBD: case OP_SUBF:3.30 + case OP_SUBV: case OP_DTOF: case OP_DTOI: case OP_FTOD: case OP_FTOI:3.31 + case OP_ITOD: case OP_ITOF: case OP_SINCOSF:3.32 + return arg1 == DEST_OPERAND;3.33 +3.34 + /* MOV and most ALU ops - there can be at most one memory operand, but3.35 + * otherwise anything goes3.36 + */3.37 + case OP_MOV: case OP_MOVQ: case OP_MOVV: case OP_MOVM:3.38 + case OP_ADD: case OP_ADDS: case OP_ADDC: case OP_ADDCS:3.39 + case OP_AND: case OP_ANDS: case OP_CMP: case OP_DIV: case OP_DIVS:3.40 + case OP_NEG: case OP_NEGS: case OP_NOT: case OP_NOTS: case OP_OR:3.41 + case OP_ORS: case OP_RCL: case OP_RCR: case OP_ROL: case OP_ROLS:3.42 + case OP_ROR: case OP_RORS: case OP_SAR: case OP_SARS: case OP_SDIV:3.43 + case OP_SDIVS: case OP_SLL: case OP_SLLS: case OP_SLR: case OP_SLRS:3.44 + case OP_SUB: case OP_SUBS: case OP_SUBB: case OP_SUBBS: case OP_TST:3.45 + case OP_XOR: case OP_XORS: case OP_RAISEME: case OP_RAISEMNE:3.46 + return arg0 == IMMEDIATE_OPERAND || arg0 == DEST_OPERAND ||3.47 + arg1 == DEST_OPERAND;3.48 +3.49 + /* Finally operations we're going to lower anyway can have arbitrary args */3.50 + case OP_DOTPRODV: case OP_MATMULV:3.51 + case OP_LOADB: case OP_LOADBFW: case OP_LOADW: case OP_LOADL:3.52 + case OP_LOADQ: case OP_STOREB: case OP_STOREW: case OP_STOREL:3.53 + case OP_STOREQ: case OP_STORELCA: case OP_CALL1: case OP_CALLR:3.54 + case OP_CALL0: case OP_ADDQSAT32: case OP_ADDQSAT48: case OP_CMPSTR:3.55 + case OP_DIV1: case OP_SHAD: case OP_SHLD: case OP_OCBI: case OP_OCBP:3.56 + case OP_OCBWB: case OP_PREF: case OP_ENTER: case OP_EXIT:3.57 + case OP_BARRIER: case OP_NOP:3.58 + return TRUE;3.59 + default:3.60 + return FALSE;3.61 }3.62 - if( arg0 == DEST_OPERAND ) {3.63 - if( arg1 == DEST_OPERAND ) {3.64 - return TRUE;3.65 - } else if( arg1 == SOURCE_OPERAND || arg1 == TEMP_OPERAND ) {3.66 - }3.67 - }3.68 -3.69 }
4.1 --- a/src/xlat/xir.c Sun Apr 12 07:24:45 2009 +00004.2 +++ b/src/xlat/xir.c Sun Apr 19 05:14:19 2009 +00004.3 @@ -34,6 +34,7 @@4.5 const struct xir_opcode_entry XIR_OPCODE_TABLE[] = {4.6 { "NOP", OPM_NO },4.7 + { "EXIT", OPM_NO | OPM_TERM },4.8 { "BARRIER", OPM_NO | OPM_CLB },4.9 { "DEC", OPM_RW_TW },4.10 { "LD", OPM_R | OPM_TW },4.11 @@ -41,8 +42,6 @@4.12 { "RESTFLAGS", OPM_R | OPM_TW },4.13 { "SAVEFLAGS", OPM_W | OPM_TR },4.14 { "ENTER", OPM_R },4.15 - { "BRREL", OPM_R | OPM_TERM },4.16 - { "BR", OPM_R | OPM_TERM },4.17 { "CALL0", OPM_R | OPM_CLB },4.18 { "OCBI", OPM_R_EXC },4.19 { "OCBP", OPM_R_EXC },4.20 @@ -69,6 +68,10 @@4.21 { "CMP", OPM_R_R_TW },4.22 { "DIV", OPM_R_RW },4.23 { "DIVS", OPM_R_RW_TW },4.24 + { "MAX", OPM_R_RW },4.25 + { "MAXQ", OPM_R_RW },4.26 + { "MIN", OPM_R_RW },4.27 + { "MINQ", OPM_R_RW },4.28 { "MUL", OPM_R_RW },4.29 { "MULS", OPM_R_RW_TW },4.30 { "MULQ", OPM_R_RW|OPM_Q_Q },4.31 @@ -113,6 +116,12 @@4.32 { "DIVD", OPM_DR_DRW },4.33 { "DIVF", OPM_FR_FRW },4.34 { "DIVV", OPM_VR_VRW },4.35 + { "MAXD", OPM_DR_DRW },4.36 + { "MAXF", OPM_FR_FRW },4.37 + { "MAXV", OPM_VR_VRW },4.38 + { "MIND", OPM_DR_DRW },4.39 + { "MINF", OPM_FR_FRW },4.40 + { "MINV", OPM_VR_VRW },4.41 { "MULD", OPM_DR_DRW },4.42 { "MULF", OPM_FR_FRW },4.43 { "MULV", OPM_VR_VRW },4.44 @@ -159,8 +168,6 @@4.45 { "STORE.Q", OPM_R_R_EXC|OPM_I_Q },4.46 { "STORE.LCA", OPM_R_R_EXC },4.48 - { "BRCOND", OPM_R_R|OPM_TR | OPM_TERM },4.49 - { "BRCONDDEL", OPM_R_R|OPM_TR },4.50 { "RAISE/ME", OPM_R_R | OPM_EXC },4.51 { "RAISE/MNE", OPM_R_R | OPM_EXC },4.53 @@ -168,6 +175,7 @@4.54 { "CALL/LUT", OPM_R_R | OPM_EXC },4.55 { "CALL1", OPM_R_R | OPM_CLB },4.56 { "CALLR", OPM_R_W | OPM_CLB },4.57 + { "LOADPTRW", OPM_R_W | 0x060 },4.58 { "LOADPTRL", OPM_R_W | 0x060 },4.59 { "LOADPTRQ", OPM_R_W | 0x160 },4.60 { "XLAT", OPM_R_RW | 0x600 }, /* Xlat Rm, Rn - Read native [Rm+Rn] and store in Rn */4.61 @@ -189,6 +197,8 @@4.62 xir_alloc_temp_reg( xbb, XTY_LONG, -1 );4.63 xir_alloc_temp_reg( xbb, XTY_QUAD, -1 );4.64 xir_alloc_temp_reg( xbb, XTY_QUAD, -1 );4.65 + xir_alloc_temp_reg( xbb, XTY_FLOAT, -1 );4.66 + xir_alloc_temp_reg( xbb, XTY_DOUBLE, -1 );4.67 }4.69 uint32_t xir_alloc_temp_reg( xir_basic_block_t xbb, xir_type_t type, int home )
5.1 --- a/src/xlat/xir.h Sun Apr 12 07:24:45 2009 +00005.2 +++ b/src/xlat/xir.h Sun Apr 19 05:14:19 2009 +00005.3 @@ -58,6 +58,8 @@5.4 #define REG_TMP2 25.5 #define REG_TMPQ0 35.6 #define REG_TMPQ1 45.7 +#define REG_TMPF0 55.8 +#define REG_TMPD0 65.11 /**5.12 @@ -120,6 +122,7 @@5.13 typedef enum {5.14 // No operands5.15 OP_NOP = 0,5.16 + OP_EXIT,5.17 OP_BARRIER, // Direction to register allocator - Ensure all state is committed5.19 // One operand5.20 @@ -129,8 +132,6 @@5.21 OP_RESTFLAGS, /* Restore flags from register */5.22 OP_SAVEFLAGS, /* Save flags into register */5.23 OP_ENTER, // Block start - immediate operand is a bitmask of target registers used5.24 - OP_BRREL,5.25 - OP_BR,5.26 OP_CALL0, // Call function with no arguments or return value5.27 OP_OCBI,5.28 OP_OCBP,5.29 @@ -159,6 +160,10 @@5.30 OP_CMP,5.31 OP_DIV, /* Unsigned division */5.32 OP_DIVS, /* Unsigned divison and update flags */5.33 + OP_MAX,5.34 + OP_MAXQ,5.35 + OP_MIN,5.36 + OP_MINQ,5.37 OP_MUL,5.38 OP_MULS,5.39 OP_MULQ,5.40 @@ -204,6 +209,12 @@5.41 OP_DIVD,5.42 OP_DIVF,5.43 OP_DIVV,5.44 + OP_MAXD,5.45 + OP_MAXF,5.46 + OP_MAXV,5.47 + OP_MIND,5.48 + OP_MINF,5.49 + OP_MINV,5.50 OP_MULD,5.51 OP_MULF,5.52 OP_MULV,5.53 @@ -241,8 +252,6 @@5.54 OP_STOREQ,5.55 OP_STORELCA,5.57 - OP_BRCOND,5.58 - OP_BRCONDDEL, // Delayed branch - sets newpc rather than pc (and is not a terminator)5.59 OP_RAISEME, // imm mask in, reg in - branch to exception if (reg & mask) == 05.60 OP_RAISEMNE, // imm mask in, reg in - branch to exception if (reg & mask) != 05.62 @@ -251,6 +260,7 @@5.63 OP_CALLLUT, // Call indirect through base pointer (reg) + displacement5.64 OP_CALL1, // Call function with single argument and no return value5.65 OP_CALLR, // Call function with no arguments and a single return value5.66 + OP_LOADPTRW, // Load 16-bit word from pointer and sign extend to 32-bits5.67 OP_LOADPTRL,5.68 OP_LOADPTRQ,5.69 OP_XLAT,5.70 @@ -278,14 +288,13 @@5.71 * ADDSAT48 Rm, Rn - 64-bit Add Rm to Rn, saturating to 48-bits if S==1 (per SH4 MAC.L)5.72 *5.73 * if R_S == 0 ->5.74 - * Rn += Rm5.75 + * ADDQ Rm, Rn5.76 * else ->5.77 - * if( Rm + Rn > 0x00007FFFFFFFFFFF ) ->5.78 - * Rn = 0x00007FFFFFFFFFFF5.79 - * else if( Rm + Rn < 0x0000800000000000 ) ->5.80 - * Rn = 0x00008000000000005.81 + * ADDQ Rm, Rn5.82 + * if overflow ->5.83 * else ->5.84 - * Rn += Rm5.85 + * MINQ 0x00007FFFFFFFFFFF, Rn5.86 + * MAXQ 0xFFFF800000000000, Rn5.87 */5.88 OP_ADDQSAT48,5.90 @@ -545,6 +554,7 @@5.91 #define XOP1T( op, arg0 ) xir_append_op2(xbb, op, TEMP_OPERAND, arg0, NO_OPERAND, 0)5.92 #define XOP1TCC( op, cc, arg0 ) xir_append_op2cc(xbb, op, cc, TEMP_OPERAND, arg0, NO_OPERAND, 0)5.93 #define XOP2IS( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, SOURCE_OPERAND, arg1)5.94 +#define XOP2ISCC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, IMMEDIATE_OPERAND, arg0, SOURCE_OPERAND, arg1)5.95 #define XOP2IT( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, TEMP_OPERAND, arg1)5.96 #define XOP2II( op, arg0, arg1 ) xir_append_op2(xbb, op, IMMEDIATE_OPERAND, arg0, IMMEDIATE_OPERAND, arg1)5.97 #define XOP2IICC( op, cc, arg0, arg1 ) xir_append_op2cc(xbb, op, cc, IMMEDIATE_OPERAND, arg0, IMMEDIATE_OPERAND, arg1)
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