lxdream 0.9.1revision 547:d6e00ffc4adc
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raw | bz2 | zip | gz | changeset | 547:d6e00ffc4adc |
| parent | 546:7d01e597a066 |
| child | 548:cd1720e7b8a7 |
| author | nkeynes |
| date | Thu Dec 06 10:37:55 2007 +0000 (16 years ago) |
Fix stack alignment on x86-64
 | src/sh4/ia64abi.h | view | annotate | diff | log | |
| src/sh4/sh4x86.c | view | annotate | diff | log | |
| src/sh4/sh4x86.in | view | annotate | diff | log | |
| src/sh4/x86op.h | view | annotate | diff | log |
1.1 --- a/src/sh4/ia64abi.h Thu Dec 06 09:25:24 2007 +00001.2 +++ b/src/sh4/ia64abi.h Thu Dec 06 10:37:55 2007 +00001.3 @@ -66,13 +66,14 @@1.4 call_func2(sh4_write_long, addr, arg2b);1.5 }1.7 -#define MEM_READ_DOUBLE_SIZE 351.8 +#define MEM_READ_DOUBLE_SIZE 431.9 /**1.10 * Read a double (64-bit) value from memory, writing the first word into arg2a1.11 * and the second into arg2b. The addr must not be in EAX1.12 */1.13 static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )1.14 {1.15 + REXW(); SUB_imm8s_r32( 8, R_ESP );1.16 PUSH_r32(addr);1.17 call_func1(sh4_read_long, addr);1.18 POP_r32(R_EDI);1.19 @@ -81,6 +82,7 @@1.20 call_func0(sh4_read_long);1.21 MOV_r32_r32(R_EAX, arg2b);1.22 POP_r32(arg2a);1.23 + REXW(); ADD_imm8s_r32( 8, R_ESP );1.24 }1.27 @@ -101,7 +103,6 @@1.28 sh4_x86.backpatch_posn = 0;1.29 sh4_x86.block_start_pc = pc;1.30 sh4_x86.tstate = TSTATE_NONE;1.31 - sh4_x86.stack_posn = 0;1.32 }1.34 /**1.35 @@ -182,4 +183,4 @@1.36 }1.37 }1.39 -#endif1.40 \ No newline at end of file1.41 +#endif
2.1 --- a/src/sh4/sh4x86.c Thu Dec 06 09:25:24 2007 +00002.2 +++ b/src/sh4/sh4x86.c Thu Dec 06 10:37:55 2007 +00002.3 @@ -45,7 +45,7 @@2.4 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */2.5 gboolean branch_taken; /* true if we branched unconditionally */2.6 uint32_t block_start_pc;2.7 - uint32_t stack_posn; /* Trace stack height for alignment purposes */2.8 + uint32_t stack_posn; /* Trace stack height for alignment purposes */2.9 int tstate;2.11 /* Allocated memory for the (block-wide) back-patch list */2.12 @@ -832,11 +832,11 @@2.13 check_ralign32( R_ECX );2.14 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );2.15 MEM_READ_LONG( R_ECX, R_EAX );2.16 - PUSH_r32( R_EAX );2.17 + PUSH_realigned_r32( R_EAX );2.18 load_reg( R_ECX, Rm );2.19 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );2.20 MEM_READ_LONG( R_ECX, R_EAX );2.21 - POP_r32( R_ECX );2.22 + POP_realigned_r32( R_ECX );2.23 IMUL_r32( R_ECX );2.24 ADD_r32_sh4r( R_EAX, R_MACL );2.25 ADC_r32_sh4r( R_EDX, R_MACH );2.26 @@ -2095,11 +2095,11 @@2.27 check_ralign16( R_ECX );2.28 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );2.29 MEM_READ_WORD( R_ECX, R_EAX );2.30 - PUSH_r32( R_EAX );2.31 + PUSH_realigned_r32( R_EAX );2.32 load_reg( R_ECX, Rm );2.33 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );2.34 MEM_READ_WORD( R_ECX, R_EAX );2.35 - POP_r32( R_ECX );2.36 + POP_realigned_r32( R_ECX );2.37 IMUL_r32( R_ECX );2.39 load_spreg( R_ECX, R_S );2.40 @@ -2639,9 +2639,9 @@2.41 load_reg( R_EAX, 0 );2.42 load_spreg( R_ECX, R_GBR );2.43 ADD_r32_r32( R_EAX, R_ECX );2.44 - PUSH_r32(R_ECX);2.45 + PUSH_realigned_r32(R_ECX);2.46 MEM_READ_BYTE( R_ECX, R_EAX );2.47 - POP_r32(R_ECX);2.48 + POP_realigned_r32(R_ECX);2.49 AND_imm32_r32(imm, R_EAX );2.50 MEM_WRITE_BYTE( R_ECX, R_EAX );2.51 sh4_x86.tstate = TSTATE_NONE;2.52 @@ -2653,9 +2653,9 @@2.53 load_reg( R_EAX, 0 );2.54 load_spreg( R_ECX, R_GBR );2.55 ADD_r32_r32( R_EAX, R_ECX );2.56 - PUSH_r32(R_ECX);2.57 + PUSH_realigned_r32(R_ECX);2.58 MEM_READ_BYTE(R_ECX, R_EAX);2.59 - POP_r32(R_ECX);2.60 + POP_realigned_r32(R_ECX);2.61 XOR_imm32_r32( imm, R_EAX );2.62 MEM_WRITE_BYTE( R_ECX, R_EAX );2.63 sh4_x86.tstate = TSTATE_NONE;2.64 @@ -2667,9 +2667,9 @@2.65 load_reg( R_EAX, 0 );2.66 load_spreg( R_ECX, R_GBR );2.67 ADD_r32_r32( R_EAX, R_ECX );2.68 - PUSH_r32(R_ECX);2.69 + PUSH_realigned_r32(R_ECX);2.70 MEM_READ_BYTE( R_ECX, R_EAX );2.71 - POP_r32(R_ECX);2.72 + POP_realigned_r32(R_ECX);2.73 OR_imm32_r32(imm, R_EAX );2.74 MEM_WRITE_BYTE( R_ECX, R_EAX );2.75 sh4_x86.tstate = TSTATE_NONE;
3.1 --- a/src/sh4/sh4x86.in Thu Dec 06 09:25:24 2007 +00003.2 +++ b/src/sh4/sh4x86.in Thu Dec 06 10:37:55 2007 +00003.3 @@ -45,7 +45,7 @@3.4 gboolean fpuen_checked; /* true if we've already checked fpu enabled. */3.5 gboolean branch_taken; /* true if we branched unconditionally */3.6 uint32_t block_start_pc;3.7 - uint32_t stack_posn; /* Trace stack height for alignment purposes */3.8 + uint32_t stack_posn; /* Trace stack height for alignment purposes */3.9 int tstate;3.11 /* Allocated memory for the (block-wide) back-patch list */3.12 @@ -453,9 +453,9 @@3.13 load_reg( R_EAX, 0 );3.14 load_spreg( R_ECX, R_GBR );3.15 ADD_r32_r32( R_EAX, R_ECX );3.16 - PUSH_r32(R_ECX);3.17 + PUSH_realigned_r32(R_ECX);3.18 MEM_READ_BYTE( R_ECX, R_EAX );3.19 - POP_r32(R_ECX);3.20 + POP_realigned_r32(R_ECX);3.21 AND_imm32_r32(imm, R_EAX );3.22 MEM_WRITE_BYTE( R_ECX, R_EAX );3.23 sh4_x86.tstate = TSTATE_NONE;3.24 @@ -625,11 +625,11 @@3.25 check_ralign32( R_ECX );3.26 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );3.27 MEM_READ_LONG( R_ECX, R_EAX );3.28 - PUSH_r32( R_EAX );3.29 + PUSH_realigned_r32( R_EAX );3.30 load_reg( R_ECX, Rm );3.31 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );3.32 MEM_READ_LONG( R_ECX, R_EAX );3.33 - POP_r32( R_ECX );3.34 + POP_realigned_r32( R_ECX );3.35 IMUL_r32( R_ECX );3.36 ADD_r32_sh4r( R_EAX, R_MACL );3.37 ADC_r32_sh4r( R_EDX, R_MACH );3.38 @@ -649,11 +649,11 @@3.39 check_ralign16( R_ECX );3.40 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );3.41 MEM_READ_WORD( R_ECX, R_EAX );3.42 - PUSH_r32( R_EAX );3.43 + PUSH_realigned_r32( R_EAX );3.44 load_reg( R_ECX, Rm );3.45 ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );3.46 MEM_READ_WORD( R_ECX, R_EAX );3.47 - POP_r32( R_ECX );3.48 + POP_realigned_r32( R_ECX );3.49 IMUL_r32( R_ECX );3.51 load_spreg( R_ECX, R_S );3.52 @@ -745,9 +745,9 @@3.53 load_reg( R_EAX, 0 );3.54 load_spreg( R_ECX, R_GBR );3.55 ADD_r32_r32( R_EAX, R_ECX );3.56 - PUSH_r32(R_ECX);3.57 + PUSH_realigned_r32(R_ECX);3.58 MEM_READ_BYTE( R_ECX, R_EAX );3.59 - POP_r32(R_ECX);3.60 + POP_realigned_r32(R_ECX);3.61 OR_imm32_r32(imm, R_EAX );3.62 MEM_WRITE_BYTE( R_ECX, R_EAX );3.63 sh4_x86.tstate = TSTATE_NONE;3.64 @@ -988,9 +988,9 @@3.65 load_reg( R_EAX, 0 );3.66 load_spreg( R_ECX, R_GBR );3.67 ADD_r32_r32( R_EAX, R_ECX );3.68 - PUSH_r32(R_ECX);3.69 + PUSH_realigned_r32(R_ECX);3.70 MEM_READ_BYTE(R_ECX, R_EAX);3.71 - POP_r32(R_ECX);3.72 + POP_realigned_r32(R_ECX);3.73 XOR_imm32_r32( imm, R_EAX );3.74 MEM_WRITE_BYTE( R_ECX, R_EAX );3.75 sh4_x86.tstate = TSTATE_NONE;
4.1 --- a/src/sh4/x86op.h Thu Dec 06 09:25:24 2007 +00004.2 +++ b/src/sh4/x86op.h Thu Dec 06 10:37:55 2007 +00004.3 @@ -56,12 +56,16 @@4.4 #if SH4_TRANSLATOR == TARGET_X86_644.5 #define OPPTR(x) OP64((uint64_t)(x))4.6 #define STACK_ALIGN 164.7 -#define POP_r32(r1) OP(0x58 + r1); sh4_x86.stack_posn -= 8;4.8 -#define PUSH_r32(r1) OP(0x50 + r1); sh4_x86.stack_posn += 8;4.9 -#define PUSH_imm32(imm) OP(0x68); OP32(imm); sh4_x86.stack_posn += 4;4.10 -#define PUSH_imm64(imm) REXW(); OP(0x68); OP64(imm); sh4_x86.stack_posn += 8;4.11 +#define POP_r32(r1) OP(0x58 + r1);4.12 +#define POP_realigned_r32(r1) OP(0x58 + r1); REXW(); ADD_imm8s_r32(8,R_ESP)4.13 +#define PUSH_r32(r1) OP(0x50 + r1);4.14 +#define PUSH_realigned_r32(r1) REXW(); SUB_imm8s_r32(8, R_ESP); OP(0x50 + r1)4.15 +#define PUSH_imm32(imm) OP(0x68); OP32(imm);4.16 +#define PUSH_imm64(imm) REXW(); OP(0x68); OP64(imm);4.17 #else4.18 #define OPPTR(x) OP32((uint32_t)(x))4.19 +#define POP_realigned_r32(r1) POP_r32(r1)4.20 +#define PUSH_realigned_r32(r1) PUSH_r32(r1)4.21 #ifdef APPLE_BUILD4.22 #define STACK_ALIGN 164.23 #define POP_r32(r1) OP(0x58 + r1); sh4_x86.stack_posn -= 4;
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