filename | src/aica/armcore.h |
changeset | 86:f151e63f9754 |
prev | 73:0bb57e51ac9e |
next | 431:248dd77a9e44 |
author | nkeynes |
date | Tue May 02 14:09:11 2006 +0000 (18 years ago) |
permissions | -rw-r--r-- |
last change | Add packet.h Implement read toc, request sense, test ready commands. Fix failure to clear error status on new command |
file | annotate | diff | log | raw |
nkeynes@30 | 1 | /** |
nkeynes@86 | 2 | * $Id: armcore.h,v 1.14 2006-01-22 22:40:05 nkeynes Exp $ |
nkeynes@30 | 3 | * |
nkeynes@30 | 4 | * Interface definitions for the ARM CPU emulation core proper. |
nkeynes@30 | 5 | * |
nkeynes@30 | 6 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@30 | 7 | * |
nkeynes@30 | 8 | * This program is free software; you can redistribute it and/or modify |
nkeynes@30 | 9 | * it under the terms of the GNU General Public License as published by |
nkeynes@30 | 10 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@30 | 11 | * (at your option) any later version. |
nkeynes@30 | 12 | * |
nkeynes@30 | 13 | * This program is distributed in the hope that it will be useful, |
nkeynes@30 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@30 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@30 | 16 | * GNU General Public License for more details. |
nkeynes@30 | 17 | */ |
nkeynes@2 | 18 | |
nkeynes@2 | 19 | #ifndef dream_armcore_H |
nkeynes@2 | 20 | #define dream_armcore_H 1 |
nkeynes@2 | 21 | |
nkeynes@2 | 22 | #include "dream.h" |
nkeynes@2 | 23 | #include <stdint.h> |
nkeynes@35 | 24 | #include <stdio.h> |
nkeynes@35 | 25 | |
nkeynes@73 | 26 | #define ARM_BASE_RATE 2 /* MHZ */ |
nkeynes@35 | 27 | extern uint32_t arm_cpu_freq; |
nkeynes@35 | 28 | extern uint32_t arm_cpu_period; |
nkeynes@2 | 29 | |
nkeynes@7 | 30 | #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) ) |
nkeynes@2 | 31 | |
nkeynes@2 | 32 | struct arm_registers { |
nkeynes@11 | 33 | uint32_t r[16]; /* Current register bank */ |
nkeynes@11 | 34 | |
nkeynes@11 | 35 | uint32_t cpsr; |
nkeynes@11 | 36 | uint32_t spsr; |
nkeynes@11 | 37 | |
nkeynes@35 | 38 | /* Various banked versions of the registers. Note that these are used |
nkeynes@35 | 39 | * to save the registers for the named bank when leaving the mode, they're |
nkeynes@35 | 40 | * not actually used actively. |
nkeynes@35 | 41 | **/ |
nkeynes@11 | 42 | uint32_t user_r[7]; /* User/System bank 8..14 */ |
nkeynes@35 | 43 | uint32_t svc_r[3]; /* SVC bank 13..14, SPSR */ |
nkeynes@35 | 44 | uint32_t abt_r[3]; /* ABT bank 13..14, SPSR */ |
nkeynes@35 | 45 | uint32_t und_r[3]; /* UND bank 13..14, SPSR */ |
nkeynes@35 | 46 | uint32_t irq_r[3]; /* IRQ bank 13..14, SPSR */ |
nkeynes@35 | 47 | uint32_t fiq_r[8]; /* FIQ bank 8..14, SPSR */ |
nkeynes@11 | 48 | |
nkeynes@11 | 49 | uint32_t c,n,z,v,t; |
nkeynes@11 | 50 | |
nkeynes@11 | 51 | /* "fake" registers */ |
nkeynes@51 | 52 | uint32_t int_pending; /* Mask of CPSR_I and CPSR_F */ |
nkeynes@11 | 53 | uint32_t shift_c; /* used for temporary storage of shifter results */ |
nkeynes@11 | 54 | uint32_t icount; /* Instruction counter */ |
nkeynes@86 | 55 | gboolean running; /* Indicates that the ARM is operational, as opposed to |
nkeynes@86 | 56 | * halted */ |
nkeynes@2 | 57 | }; |
nkeynes@2 | 58 | |
nkeynes@2 | 59 | #define CPSR_N 0x80000000 /* Negative flag */ |
nkeynes@2 | 60 | #define CPSR_Z 0x40000000 /* Zero flag */ |
nkeynes@2 | 61 | #define CPSR_C 0x20000000 /* Carry flag */ |
nkeynes@2 | 62 | #define CPSR_V 0x10000000 /* Overflow flag */ |
nkeynes@2 | 63 | #define CPSR_I 0x00000080 /* Interrupt disable bit */ |
nkeynes@2 | 64 | #define CPSR_F 0x00000040 /* Fast interrupt disable bit */ |
nkeynes@2 | 65 | #define CPSR_T 0x00000020 /* Thumb mode */ |
nkeynes@2 | 66 | #define CPSR_MODE 0x0000001F /* Current execution mode */ |
nkeynes@37 | 67 | #define CPSR_COMPACT_MASK 0x0FFFFFDF /* Mask excluding all separated flags */ |
nkeynes@2 | 68 | |
nkeynes@35 | 69 | #define MODE_USER 0x10 /* User mode */ |
nkeynes@35 | 70 | #define MODE_FIQ 0x11 /* Fast IRQ mode */ |
nkeynes@35 | 71 | #define MODE_IRQ 0x12 /* IRQ mode */ |
nkeynes@35 | 72 | #define MODE_SVC 0x13 /* Supervisor mode */ |
nkeynes@35 | 73 | #define MODE_ABT 0x17 /* Abort mode */ |
nkeynes@35 | 74 | #define MODE_UND 0x1B /* Undefined mode */ |
nkeynes@35 | 75 | #define MODE_SYS 0x1F /* System mode */ |
nkeynes@2 | 76 | |
nkeynes@37 | 77 | #define IS_PRIVILEGED_MODE() ((armr.cpsr & CPSR_MODE) != MODE_USER) |
nkeynes@37 | 78 | #define IS_EXCEPTION_MODE() (IS_PRIVILEGED_MODE() && (armr.cpsr & CPSR_MODE) != MODE_SYS) |
nkeynes@46 | 79 | #define IS_FIQ_MODE() ((armr.cpsr & CPSR_MODE) == MODE_FIQ) |
nkeynes@37 | 80 | |
nkeynes@2 | 81 | extern struct arm_registers armr; |
nkeynes@2 | 82 | |
nkeynes@5 | 83 | #define CARRY_FLAG (armr.cpsr&CPSR_C) |
nkeynes@2 | 84 | |
nkeynes@35 | 85 | /* ARM core functions */ |
nkeynes@35 | 86 | void arm_reset( void ); |
nkeynes@35 | 87 | uint32_t arm_run_slice( uint32_t nanosecs ); |
nkeynes@35 | 88 | void arm_save_state( FILE *f ); |
nkeynes@35 | 89 | int arm_load_state( FILE *f ); |
nkeynes@35 | 90 | gboolean arm_execute_instruction( void ); |
nkeynes@43 | 91 | void arm_set_breakpoint( uint32_t pc, int type ); |
nkeynes@43 | 92 | gboolean arm_clear_breakpoint( uint32_t pc, int type ); |
nkeynes@43 | 93 | int arm_get_breakpoint( uint32_t pc ); |
nkeynes@35 | 94 | |
nkeynes@11 | 95 | /* ARM Memory */ |
nkeynes@37 | 96 | uint32_t arm_read_long( uint32_t addr ); |
nkeynes@37 | 97 | uint32_t arm_read_word( uint32_t addr ); |
nkeynes@37 | 98 | uint32_t arm_read_byte( uint32_t addr ); |
nkeynes@37 | 99 | uint32_t arm_read_long_user( uint32_t addr ); |
nkeynes@37 | 100 | uint32_t arm_read_byte_user( uint32_t addr ); |
nkeynes@11 | 101 | void arm_write_long( uint32_t addr, uint32_t val ); |
nkeynes@11 | 102 | void arm_write_word( uint32_t addr, uint32_t val ); |
nkeynes@11 | 103 | void arm_write_byte( uint32_t addr, uint32_t val ); |
nkeynes@37 | 104 | void arm_write_long_user( uint32_t addr, uint32_t val ); |
nkeynes@37 | 105 | void arm_write_byte_user( uint32_t addr, uint32_t val ); |
nkeynes@11 | 106 | int32_t arm_read_phys_word( uint32_t addr ); |
nkeynes@14 | 107 | int arm_has_page( uint32_t addr ); |
nkeynes@11 | 108 | |
nkeynes@2 | 109 | #endif /* !dream_armcore_H */ |
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