nkeynes@378 | 1 | /**
|
nkeynes@586 | 2 | * $Id$
|
nkeynes@378 | 3 | *
|
nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral
|
nkeynes@378 | 5 | * modules.
|
nkeynes@378 | 6 | *
|
nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes.
|
nkeynes@378 | 8 | *
|
nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by
|
nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@378 | 12 | * (at your option) any later version.
|
nkeynes@378 | 13 | *
|
nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful,
|
nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@378 | 17 | * GNU General Public License for more details.
|
nkeynes@378 | 18 | */
|
nkeynes@378 | 19 |
|
nkeynes@378 | 20 | #define MODULE sh4_module
|
nkeynes@378 | 21 | #include <math.h>
|
nkeynes@617 | 22 | #include <assert.h>
|
nkeynes@671 | 23 | #include "lxdream.h"
|
nkeynes@422 | 24 | #include "dreamcast.h"
|
nkeynes@669 | 25 | #include "mem.h"
|
nkeynes@669 | 26 | #include "clock.h"
|
nkeynes@669 | 27 | #include "eventq.h"
|
nkeynes@669 | 28 | #include "syscall.h"
|
nkeynes@669 | 29 | #include "sh4/intc.h"
|
nkeynes@378 | 30 | #include "sh4/sh4core.h"
|
nkeynes@378 | 31 | #include "sh4/sh4mmio.h"
|
nkeynes@422 | 32 | #include "sh4/sh4stat.h"
|
nkeynes@617 | 33 | #include "sh4/sh4trans.h"
|
nkeynes@669 | 34 | #include "sh4/xltcache.h"
|
nkeynes@378 | 35 |
|
nkeynes@378 | 36 | void sh4_init( void );
|
nkeynes@526 | 37 | void sh4_xlat_init( void );
|
nkeynes@378 | 38 | void sh4_reset( void );
|
nkeynes@378 | 39 | void sh4_start( void );
|
nkeynes@378 | 40 | void sh4_stop( void );
|
nkeynes@378 | 41 | void sh4_save_state( FILE *f );
|
nkeynes@378 | 42 | int sh4_load_state( FILE *f );
|
nkeynes@378 | 43 |
|
nkeynes@378 | 44 | uint32_t sh4_run_slice( uint32_t );
|
nkeynes@378 | 45 | uint32_t sh4_xlat_run_slice( uint32_t );
|
nkeynes@378 | 46 |
|
nkeynes@378 | 47 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
|
nkeynes@591 | 48 | sh4_start, sh4_run_slice, sh4_stop,
|
nkeynes@378 | 49 | sh4_save_state, sh4_load_state };
|
nkeynes@378 | 50 |
|
nkeynes@378 | 51 | struct sh4_registers sh4r;
|
nkeynes@378 | 52 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
|
nkeynes@378 | 53 | int sh4_breakpoint_count = 0;
|
nkeynes@586 | 54 | sh4ptr_t sh4_main_ram;
|
nkeynes@591 | 55 | gboolean sh4_starting = FALSE;
|
nkeynes@526 | 56 | static gboolean sh4_use_translator = FALSE;
|
nkeynes@586 | 57 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
|
nkeynes@378 | 58 |
|
nkeynes@378 | 59 | void sh4_set_use_xlat( gboolean use )
|
nkeynes@378 | 60 | {
|
nkeynes@526 | 61 | // No-op if the translator was not built
|
nkeynes@526 | 62 | #ifdef SH4_TRANSLATOR
|
nkeynes@378 | 63 | if( use ) {
|
nkeynes@378 | 64 | xlat_cache_init();
|
nkeynes@669 | 65 | sh4_translate_init();
|
nkeynes@378 | 66 | sh4_module.run_time_slice = sh4_xlat_run_slice;
|
nkeynes@378 | 67 | } else {
|
nkeynes@378 | 68 | sh4_module.run_time_slice = sh4_run_slice;
|
nkeynes@378 | 69 | }
|
nkeynes@526 | 70 | sh4_use_translator = use;
|
nkeynes@526 | 71 | #endif
|
nkeynes@378 | 72 | }
|
nkeynes@378 | 73 |
|
nkeynes@586 | 74 | gboolean sh4_is_using_xlat()
|
nkeynes@586 | 75 | {
|
nkeynes@586 | 76 | return sh4_use_translator;
|
nkeynes@586 | 77 | }
|
nkeynes@586 | 78 |
|
nkeynes@378 | 79 | void sh4_init(void)
|
nkeynes@378 | 80 | {
|
nkeynes@378 | 81 | register_io_regions( mmio_list_sh4mmio );
|
nkeynes@418 | 82 | sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
|
nkeynes@378 | 83 | MMU_init();
|
nkeynes@619 | 84 | TMU_init();
|
nkeynes@378 | 85 | sh4_reset();
|
nkeynes@671 | 86 | #ifdef ENABLE_SH4STATS
|
nkeynes@671 | 87 | sh4_stats_reset();
|
nkeynes@671 | 88 | #endif
|
nkeynes@378 | 89 | }
|
nkeynes@378 | 90 |
|
nkeynes@591 | 91 | void sh4_start(void)
|
nkeynes@591 | 92 | {
|
nkeynes@591 | 93 | sh4_starting = TRUE;
|
nkeynes@591 | 94 | }
|
nkeynes@591 | 95 |
|
nkeynes@378 | 96 | void sh4_reset(void)
|
nkeynes@378 | 97 | {
|
nkeynes@526 | 98 | if( sh4_use_translator ) {
|
nkeynes@472 | 99 | xlat_flush_cache();
|
nkeynes@472 | 100 | }
|
nkeynes@472 | 101 |
|
nkeynes@378 | 102 | /* zero everything out, for the sake of having a consistent state. */
|
nkeynes@378 | 103 | memset( &sh4r, 0, sizeof(sh4r) );
|
nkeynes@378 | 104 |
|
nkeynes@378 | 105 | /* Resume running if we were halted */
|
nkeynes@378 | 106 | sh4r.sh4_state = SH4_STATE_RUNNING;
|
nkeynes@378 | 107 |
|
nkeynes@378 | 108 | sh4r.pc = 0xA0000000;
|
nkeynes@378 | 109 | sh4r.new_pc= 0xA0000002;
|
nkeynes@378 | 110 | sh4r.vbr = 0x00000000;
|
nkeynes@378 | 111 | sh4r.fpscr = 0x00040001;
|
nkeynes@378 | 112 | sh4r.sr = 0x700000F0;
|
nkeynes@378 | 113 |
|
nkeynes@378 | 114 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */
|
nkeynes@378 | 115 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
|
nkeynes@378 | 116 |
|
nkeynes@378 | 117 | /* Peripheral modules */
|
nkeynes@378 | 118 | CPG_reset();
|
nkeynes@378 | 119 | INTC_reset();
|
nkeynes@378 | 120 | MMU_reset();
|
nkeynes@378 | 121 | TMU_reset();
|
nkeynes@378 | 122 | SCIF_reset();
|
nkeynes@671 | 123 |
|
nkeynes@671 | 124 | #ifdef ENABLE_SH4STATS
|
nkeynes@401 | 125 | sh4_stats_reset();
|
nkeynes@671 | 126 | #endif
|
nkeynes@378 | 127 | }
|
nkeynes@378 | 128 |
|
nkeynes@378 | 129 | void sh4_stop(void)
|
nkeynes@378 | 130 | {
|
nkeynes@526 | 131 | if( sh4_use_translator ) {
|
nkeynes@502 | 132 | /* If we were running with the translator, update new_pc and in_delay_slot */
|
nkeynes@502 | 133 | sh4r.new_pc = sh4r.pc+2;
|
nkeynes@502 | 134 | sh4r.in_delay_slot = FALSE;
|
nkeynes@502 | 135 | }
|
nkeynes@378 | 136 |
|
nkeynes@378 | 137 | }
|
nkeynes@378 | 138 |
|
nkeynes@378 | 139 | void sh4_save_state( FILE *f )
|
nkeynes@378 | 140 | {
|
nkeynes@526 | 141 | if( sh4_use_translator ) {
|
nkeynes@401 | 142 | /* If we were running with the translator, update new_pc and in_delay_slot */
|
nkeynes@401 | 143 | sh4r.new_pc = sh4r.pc+2;
|
nkeynes@401 | 144 | sh4r.in_delay_slot = FALSE;
|
nkeynes@401 | 145 | }
|
nkeynes@401 | 146 |
|
nkeynes@378 | 147 | fwrite( &sh4r, sizeof(sh4r), 1, f );
|
nkeynes@378 | 148 | MMU_save_state( f );
|
nkeynes@378 | 149 | INTC_save_state( f );
|
nkeynes@378 | 150 | TMU_save_state( f );
|
nkeynes@378 | 151 | SCIF_save_state( f );
|
nkeynes@378 | 152 | }
|
nkeynes@378 | 153 |
|
nkeynes@378 | 154 | int sh4_load_state( FILE * f )
|
nkeynes@378 | 155 | {
|
nkeynes@526 | 156 | if( sh4_use_translator ) {
|
nkeynes@472 | 157 | xlat_flush_cache();
|
nkeynes@472 | 158 | }
|
nkeynes@378 | 159 | fread( &sh4r, sizeof(sh4r), 1, f );
|
nkeynes@378 | 160 | MMU_load_state( f );
|
nkeynes@378 | 161 | INTC_load_state( f );
|
nkeynes@378 | 162 | TMU_load_state( f );
|
nkeynes@378 | 163 | return SCIF_load_state( f );
|
nkeynes@378 | 164 | }
|
nkeynes@378 | 165 |
|
nkeynes@378 | 166 |
|
nkeynes@586 | 167 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
|
nkeynes@378 | 168 | {
|
nkeynes@378 | 169 | sh4_breakpoints[sh4_breakpoint_count].address = pc;
|
nkeynes@378 | 170 | sh4_breakpoints[sh4_breakpoint_count].type = type;
|
nkeynes@586 | 171 | if( sh4_use_translator ) {
|
nkeynes@586 | 172 | xlat_invalidate_word( pc );
|
nkeynes@586 | 173 | }
|
nkeynes@378 | 174 | sh4_breakpoint_count++;
|
nkeynes@378 | 175 | }
|
nkeynes@378 | 176 |
|
nkeynes@586 | 177 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
|
nkeynes@378 | 178 | {
|
nkeynes@378 | 179 | int i;
|
nkeynes@378 | 180 |
|
nkeynes@378 | 181 | for( i=0; i<sh4_breakpoint_count; i++ ) {
|
nkeynes@378 | 182 | if( sh4_breakpoints[i].address == pc &&
|
nkeynes@378 | 183 | sh4_breakpoints[i].type == type ) {
|
nkeynes@378 | 184 | while( ++i < sh4_breakpoint_count ) {
|
nkeynes@378 | 185 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
|
nkeynes@378 | 186 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
|
nkeynes@378 | 187 | }
|
nkeynes@586 | 188 | if( sh4_use_translator ) {
|
nkeynes@586 | 189 | xlat_invalidate_word( pc );
|
nkeynes@586 | 190 | }
|
nkeynes@378 | 191 | sh4_breakpoint_count--;
|
nkeynes@378 | 192 | return TRUE;
|
nkeynes@378 | 193 | }
|
nkeynes@378 | 194 | }
|
nkeynes@378 | 195 | return FALSE;
|
nkeynes@378 | 196 | }
|
nkeynes@378 | 197 |
|
nkeynes@378 | 198 | int sh4_get_breakpoint( uint32_t pc )
|
nkeynes@378 | 199 | {
|
nkeynes@378 | 200 | int i;
|
nkeynes@378 | 201 | for( i=0; i<sh4_breakpoint_count; i++ ) {
|
nkeynes@378 | 202 | if( sh4_breakpoints[i].address == pc )
|
nkeynes@378 | 203 | return sh4_breakpoints[i].type;
|
nkeynes@378 | 204 | }
|
nkeynes@378 | 205 | return 0;
|
nkeynes@378 | 206 | }
|
nkeynes@378 | 207 |
|
nkeynes@401 | 208 | void sh4_set_pc( int pc )
|
nkeynes@401 | 209 | {
|
nkeynes@401 | 210 | sh4r.pc = pc;
|
nkeynes@401 | 211 | sh4r.new_pc = pc+2;
|
nkeynes@401 | 212 | }
|
nkeynes@401 | 213 |
|
nkeynes@401 | 214 |
|
nkeynes@401 | 215 | /******************************* Support methods ***************************/
|
nkeynes@401 | 216 |
|
nkeynes@401 | 217 | static void sh4_switch_banks( )
|
nkeynes@401 | 218 | {
|
nkeynes@401 | 219 | uint32_t tmp[8];
|
nkeynes@401 | 220 |
|
nkeynes@401 | 221 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
|
nkeynes@401 | 222 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
|
nkeynes@401 | 223 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
|
nkeynes@401 | 224 | }
|
nkeynes@401 | 225 |
|
nkeynes@669 | 226 | void sh4_switch_fr_banks()
|
nkeynes@669 | 227 | {
|
nkeynes@669 | 228 | int i;
|
nkeynes@669 | 229 | for( i=0; i<16; i++ ) {
|
nkeynes@669 | 230 | float tmp = sh4r.fr[0][i];
|
nkeynes@669 | 231 | sh4r.fr[0][i] = sh4r.fr[1][i];
|
nkeynes@669 | 232 | sh4r.fr[1][i] = tmp;
|
nkeynes@669 | 233 | }
|
nkeynes@669 | 234 | }
|
nkeynes@669 | 235 |
|
nkeynes@401 | 236 | void sh4_write_sr( uint32_t newval )
|
nkeynes@401 | 237 | {
|
nkeynes@586 | 238 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
|
nkeynes@586 | 239 | int newbank = (newval&SR_MDRB) == SR_MDRB;
|
nkeynes@586 | 240 | if( oldbank != newbank )
|
nkeynes@401 | 241 | sh4_switch_banks();
|
nkeynes@401 | 242 | sh4r.sr = newval;
|
nkeynes@401 | 243 | sh4r.t = (newval&SR_T) ? 1 : 0;
|
nkeynes@401 | 244 | sh4r.s = (newval&SR_S) ? 1 : 0;
|
nkeynes@401 | 245 | sh4r.m = (newval&SR_M) ? 1 : 0;
|
nkeynes@401 | 246 | sh4r.q = (newval&SR_Q) ? 1 : 0;
|
nkeynes@401 | 247 | intc_mask_changed();
|
nkeynes@401 | 248 | }
|
nkeynes@401 | 249 |
|
nkeynes@669 | 250 | void sh4_write_fpscr( uint32_t newval )
|
nkeynes@669 | 251 | {
|
nkeynes@669 | 252 | if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
|
nkeynes@669 | 253 | sh4_switch_fr_banks();
|
nkeynes@669 | 254 | }
|
nkeynes@669 | 255 | sh4r.fpscr = newval;
|
nkeynes@669 | 256 | }
|
nkeynes@669 | 257 |
|
nkeynes@401 | 258 | uint32_t sh4_read_sr( void )
|
nkeynes@401 | 259 | {
|
nkeynes@401 | 260 | /* synchronize sh4r.sr with the various bitflags */
|
nkeynes@401 | 261 | sh4r.sr &= SR_MQSTMASK;
|
nkeynes@401 | 262 | if( sh4r.t ) sh4r.sr |= SR_T;
|
nkeynes@401 | 263 | if( sh4r.s ) sh4r.sr |= SR_S;
|
nkeynes@401 | 264 | if( sh4r.m ) sh4r.sr |= SR_M;
|
nkeynes@401 | 265 | if( sh4r.q ) sh4r.sr |= SR_Q;
|
nkeynes@401 | 266 | return sh4r.sr;
|
nkeynes@401 | 267 | }
|
nkeynes@401 | 268 |
|
nkeynes@401 | 269 |
|
nkeynes@401 | 270 |
|
nkeynes@401 | 271 | #define RAISE( x, v ) do{ \
|
nkeynes@401 | 272 | if( sh4r.vbr == 0 ) { \
|
nkeynes@401 | 273 | ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
|
nkeynes@401 | 274 | dreamcast_stop(); return FALSE; \
|
nkeynes@401 | 275 | } else { \
|
nkeynes@401 | 276 | sh4r.spc = sh4r.pc; \
|
nkeynes@401 | 277 | sh4r.ssr = sh4_read_sr(); \
|
nkeynes@401 | 278 | sh4r.sgr = sh4r.r[15]; \
|
nkeynes@401 | 279 | MMIO_WRITE(MMU,EXPEVT,x); \
|
nkeynes@401 | 280 | sh4r.pc = sh4r.vbr + v; \
|
nkeynes@401 | 281 | sh4r.new_pc = sh4r.pc + 2; \
|
nkeynes@401 | 282 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
|
nkeynes@401 | 283 | if( sh4r.in_delay_slot ) { \
|
nkeynes@401 | 284 | sh4r.in_delay_slot = 0; \
|
nkeynes@401 | 285 | sh4r.spc -= 2; \
|
nkeynes@401 | 286 | } \
|
nkeynes@401 | 287 | } \
|
nkeynes@401 | 288 | return TRUE; } while(0)
|
nkeynes@401 | 289 |
|
nkeynes@401 | 290 | /**
|
nkeynes@401 | 291 | * Raise a general CPU exception for the specified exception code.
|
nkeynes@401 | 292 | * (NOT for TRAPA or TLB exceptions)
|
nkeynes@401 | 293 | */
|
nkeynes@401 | 294 | gboolean sh4_raise_exception( int code )
|
nkeynes@401 | 295 | {
|
nkeynes@401 | 296 | RAISE( code, EXV_EXCEPTION );
|
nkeynes@401 | 297 | }
|
nkeynes@401 | 298 |
|
nkeynes@586 | 299 | /**
|
nkeynes@586 | 300 | * Raise a CPU reset exception with the specified exception code.
|
nkeynes@586 | 301 | */
|
nkeynes@586 | 302 | gboolean sh4_raise_reset( int code )
|
nkeynes@586 | 303 | {
|
nkeynes@586 | 304 | // FIXME: reset modules as per "manual reset"
|
nkeynes@586 | 305 | sh4_reset();
|
nkeynes@586 | 306 | MMIO_WRITE(MMU,EXPEVT,code);
|
nkeynes@586 | 307 | sh4r.vbr = 0;
|
nkeynes@586 | 308 | sh4r.pc = 0xA0000000;
|
nkeynes@586 | 309 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@586 | 310 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
|
nkeynes@586 | 311 | &(~SR_FD) );
|
nkeynes@669 | 312 | return TRUE;
|
nkeynes@586 | 313 | }
|
nkeynes@586 | 314 |
|
nkeynes@401 | 315 | gboolean sh4_raise_trap( int trap )
|
nkeynes@401 | 316 | {
|
nkeynes@401 | 317 | MMIO_WRITE( MMU, TRA, trap<<2 );
|
nkeynes@586 | 318 | RAISE( EXC_TRAP, EXV_EXCEPTION );
|
nkeynes@401 | 319 | }
|
nkeynes@401 | 320 |
|
nkeynes@401 | 321 | gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
|
nkeynes@401 | 322 | if( sh4r.in_delay_slot ) {
|
nkeynes@401 | 323 | return sh4_raise_exception(slot_code);
|
nkeynes@401 | 324 | } else {
|
nkeynes@401 | 325 | return sh4_raise_exception(normal_code);
|
nkeynes@401 | 326 | }
|
nkeynes@401 | 327 | }
|
nkeynes@401 | 328 |
|
nkeynes@401 | 329 | gboolean sh4_raise_tlb_exception( int code )
|
nkeynes@401 | 330 | {
|
nkeynes@401 | 331 | RAISE( code, EXV_TLBMISS );
|
nkeynes@401 | 332 | }
|
nkeynes@401 | 333 |
|
nkeynes@401 | 334 | void sh4_accept_interrupt( void )
|
nkeynes@401 | 335 | {
|
nkeynes@401 | 336 | uint32_t code = intc_accept_interrupt();
|
nkeynes@401 | 337 | sh4r.ssr = sh4_read_sr();
|
nkeynes@401 | 338 | sh4r.spc = sh4r.pc;
|
nkeynes@401 | 339 | sh4r.sgr = sh4r.r[15];
|
nkeynes@401 | 340 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
|
nkeynes@401 | 341 | MMIO_WRITE( MMU, INTEVT, code );
|
nkeynes@401 | 342 | sh4r.pc = sh4r.vbr + 0x600;
|
nkeynes@401 | 343 | sh4r.new_pc = sh4r.pc + 2;
|
nkeynes@401 | 344 | // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
|
nkeynes@401 | 345 | }
|
nkeynes@401 | 346 |
|
nkeynes@401 | 347 | void signsat48( void )
|
nkeynes@401 | 348 | {
|
nkeynes@401 | 349 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
|
nkeynes@401 | 350 | sh4r.mac = 0xFFFF800000000000LL;
|
nkeynes@401 | 351 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
|
nkeynes@401 | 352 | sh4r.mac = 0x00007FFFFFFFFFFFLL;
|
nkeynes@401 | 353 | }
|
nkeynes@401 | 354 |
|
nkeynes@401 | 355 | void sh4_fsca( uint32_t anglei, float *fr )
|
nkeynes@401 | 356 | {
|
nkeynes@401 | 357 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
|
nkeynes@401 | 358 | *fr++ = cosf(angle);
|
nkeynes@401 | 359 | *fr = sinf(angle);
|
nkeynes@401 | 360 | }
|
nkeynes@401 | 361 |
|
nkeynes@617 | 362 | /**
|
nkeynes@617 | 363 | * Enter sleep mode (eg by executing a SLEEP instruction).
|
nkeynes@617 | 364 | * Sets sh4_state appropriately and ensures any stopping peripheral modules
|
nkeynes@617 | 365 | * are up to date.
|
nkeynes@617 | 366 | */
|
nkeynes@401 | 367 | void sh4_sleep(void)
|
nkeynes@401 | 368 | {
|
nkeynes@401 | 369 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
|
nkeynes@401 | 370 | sh4r.sh4_state = SH4_STATE_STANDBY;
|
nkeynes@617 | 371 | /* Bring all running peripheral modules up to date, and then halt them. */
|
nkeynes@617 | 372 | TMU_run_slice( sh4r.slice_cycle );
|
nkeynes@617 | 373 | SCIF_run_slice( sh4r.slice_cycle );
|
nkeynes@401 | 374 | } else {
|
nkeynes@617 | 375 | if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
|
nkeynes@617 | 376 | sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
|
nkeynes@617 | 377 | /* Halt DMAC but other peripherals still running */
|
nkeynes@617 | 378 |
|
nkeynes@617 | 379 | } else {
|
nkeynes@617 | 380 | sh4r.sh4_state = SH4_STATE_SLEEP;
|
nkeynes@617 | 381 | }
|
nkeynes@617 | 382 | }
|
nkeynes@617 | 383 | if( sh4_xlat_is_running() ) {
|
nkeynes@617 | 384 | sh4_translate_exit( XLAT_EXIT_SLEEP );
|
nkeynes@401 | 385 | }
|
nkeynes@401 | 386 | }
|
nkeynes@401 | 387 |
|
nkeynes@401 | 388 | /**
|
nkeynes@617 | 389 | * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
|
nkeynes@617 | 390 | * and restarts any peripheral devices that were stopped.
|
nkeynes@617 | 391 | */
|
nkeynes@617 | 392 | void sh4_wakeup(void)
|
nkeynes@617 | 393 | {
|
nkeynes@617 | 394 | switch( sh4r.sh4_state ) {
|
nkeynes@617 | 395 | case SH4_STATE_STANDBY:
|
nkeynes@617 | 396 | break;
|
nkeynes@617 | 397 | case SH4_STATE_DEEP_SLEEP:
|
nkeynes@617 | 398 | break;
|
nkeynes@617 | 399 | case SH4_STATE_SLEEP:
|
nkeynes@617 | 400 | break;
|
nkeynes@617 | 401 | }
|
nkeynes@617 | 402 | sh4r.sh4_state = SH4_STATE_RUNNING;
|
nkeynes@617 | 403 | }
|
nkeynes@617 | 404 |
|
nkeynes@617 | 405 | /**
|
nkeynes@617 | 406 | * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
|
nkeynes@617 | 407 | * Returns when either the SH4 wakes up (interrupt received) or the end of
|
nkeynes@617 | 408 | * the slice is reached. Updates sh4.slice_cycle with the exit time and
|
nkeynes@617 | 409 | * returns the same value.
|
nkeynes@617 | 410 | */
|
nkeynes@617 | 411 | uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
|
nkeynes@617 | 412 | {
|
nkeynes@617 | 413 | int sleep_state = sh4r.sh4_state;
|
nkeynes@617 | 414 | assert( sleep_state != SH4_STATE_RUNNING );
|
nkeynes@638 | 415 |
|
nkeynes@617 | 416 | while( sh4r.event_pending < nanosecs ) {
|
nkeynes@617 | 417 | sh4r.slice_cycle = sh4r.event_pending;
|
nkeynes@617 | 418 | if( sh4r.event_types & PENDING_EVENT ) {
|
nkeynes@617 | 419 | event_execute();
|
nkeynes@617 | 420 | }
|
nkeynes@617 | 421 | if( sh4r.event_types & PENDING_IRQ ) {
|
nkeynes@617 | 422 | sh4_wakeup();
|
nkeynes@638 | 423 | return sh4r.slice_cycle;
|
nkeynes@617 | 424 | }
|
nkeynes@617 | 425 | }
|
nkeynes@617 | 426 | sh4r.slice_cycle = nanosecs;
|
nkeynes@617 | 427 | return sh4r.slice_cycle;
|
nkeynes@617 | 428 | }
|
nkeynes@617 | 429 |
|
nkeynes@617 | 430 |
|
nkeynes@617 | 431 | /**
|
nkeynes@401 | 432 | * Compute the matrix tranform of fv given the matrix xf.
|
nkeynes@401 | 433 | * Both fv and xf are word-swapped as per the sh4r.fr banks
|
nkeynes@401 | 434 | */
|
nkeynes@669 | 435 | void sh4_ftrv( float *target )
|
nkeynes@401 | 436 | {
|
nkeynes@401 | 437 | float fv[4] = { target[1], target[0], target[3], target[2] };
|
nkeynes@669 | 438 | target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
|
nkeynes@669 | 439 | sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
|
nkeynes@669 | 440 | target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
|
nkeynes@669 | 441 | sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
|
nkeynes@669 | 442 | target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
|
nkeynes@669 | 443 | sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
|
nkeynes@669 | 444 | target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
|
nkeynes@669 | 445 | sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
|
nkeynes@401 | 446 | }
|
nkeynes@401 | 447 |
|
nkeynes@597 | 448 | gboolean sh4_has_page( sh4vma_t vma )
|
nkeynes@597 | 449 | {
|
nkeynes@597 | 450 | sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
|
nkeynes@597 | 451 | return addr != MMU_VMA_ERROR && mem_has_page(addr);
|
nkeynes@597 | 452 | }
|