| nkeynes@231 | 1 | .section .text
|
| nkeynes@231 | 2 | .include "sh4/inc.s"
|
| nkeynes@231 | 3 | !
|
| nkeynes@231 | 4 | ! Test for all cases that raise a slot-illegal exception (according to the SH4
|
| nkeynes@231 | 5 | ! manual). See Page 103 of the Hitachi manual
|
| nkeynes@231 | 6 |
|
| nkeynes@231 | 7 | .global _test_slot_illegal
|
| nkeynes@231 | 8 | _test_slot_illegal:
|
| nkeynes@231 | 9 | start_test
|
| nkeynes@231 | 10 |
|
| nkeynes@231 | 11 | ! First the easy ones - instructions not permitted in delay slots at any
|
| nkeynes@231 | 12 | ! time:
|
| nkeynes@231 | 13 | ! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
|
| nkeynes@231 | 14 | ! LDC (to SR), MOV pcrel, MOVA
|
| nkeynes@231 | 15 | !
|
| nkeynes@231 | 16 | ! Note that the tests use BSR as the branch instruction, and assume it
|
| nkeynes@231 | 17 | ! functions correctly.
|
| nkeynes@231 | 18 |
|
| nkeynes@231 | 19 | test_slot_1: !JMP
|
| nkeynes@231 | 20 | add #1, r12
|
| nkeynes@231 | 21 | expect_exc 0x000001A0
|
| nkeynes@231 | 22 | test_slot_1_pc:
|
| nkeynes@231 | 23 | bsr test_slot_fail
|
| nkeynes@231 | 24 | jmp @r3
|
| nkeynes@231 | 25 | assert_exc_caught test_slot_str_k1 test_slot_1_pc
|
| nkeynes@231 | 26 |
|
| nkeynes@231 | 27 | test_slot_2: ! JSR
|
| nkeynes@231 | 28 | add #1, r12
|
| nkeynes@231 | 29 | expect_exc 0x000001A0
|
| nkeynes@231 | 30 | test_slot_2_pc:
|
| nkeynes@231 | 31 | bsr test_slot_fail
|
| nkeynes@231 | 32 | jsr @r3
|
| nkeynes@231 | 33 | assert_exc_caught test_slot_str_k1 test_slot_2_pc
|
| nkeynes@231 | 34 |
|
| nkeynes@231 | 35 | test_slot_3: ! BRA
|
| nkeynes@231 | 36 | add #1, r12
|
| nkeynes@231 | 37 | expect_exc 0x000001A0
|
| nkeynes@231 | 38 | test_slot_3_pc:
|
| nkeynes@231 | 39 | bsr test_slot_fail
|
| nkeynes@231 | 40 | bra test_slot_fail
|
| nkeynes@233 | 41 | assert_exc_caught test_slot_str_k1 test_slot_3_pc
|
| nkeynes@231 | 42 |
|
| nkeynes@231 | 43 | test_slot_4: ! BRAF
|
| nkeynes@231 | 44 | add #1, r12
|
| nkeynes@231 | 45 | expect_exc 0x000001A0
|
| nkeynes@231 | 46 | test_slot_4_pc:
|
| nkeynes@231 | 47 | bsr test_slot_fail
|
| nkeynes@231 | 48 | braf r3
|
| nkeynes@231 | 49 | assert_exc_caught test_slot_str_k test_slot_4_pc
|
| nkeynes@231 | 50 |
|
| nkeynes@231 | 51 | test_slot_5: ! BSR
|
| nkeynes@231 | 52 | add #1, r12
|
| nkeynes@231 | 53 | expect_exc 0x000001A0
|
| nkeynes@231 | 54 | test_slot_5_pc:
|
| nkeynes@231 | 55 | bsr test_slot_fail
|
| nkeynes@231 | 56 | bsr test_slot_fail
|
| nkeynes@231 | 57 | assert_exc_caught test_slot_str_k test_slot_5_pc
|
| nkeynes@231 | 58 |
|
| nkeynes@231 | 59 | test_slot_6: ! BSRF
|
| nkeynes@231 | 60 | add #1, r12
|
| nkeynes@231 | 61 | expect_exc 0x000001A0
|
| nkeynes@231 | 62 | test_slot_6_pc:
|
| nkeynes@231 | 63 | bsr test_slot_fail
|
| nkeynes@231 | 64 | bsrf r3
|
| nkeynes@231 | 65 | assert_exc_caught test_slot_str_k test_slot_6_pc
|
| nkeynes@231 | 66 |
|
| nkeynes@231 | 67 | test_slot_7: ! BF
|
| nkeynes@231 | 68 | add #1, r12
|
| nkeynes@231 | 69 | expect_exc 0x000001A0
|
| nkeynes@231 | 70 | test_slot_7_pc:
|
| nkeynes@231 | 71 | bsr test_slot_fail
|
| nkeynes@231 | 72 | bf test_slot_7_fail
|
| nkeynes@231 | 73 | test_slot_7_fail:
|
| nkeynes@231 | 74 | assert_exc_caught test_slot_str_k test_slot_7_pc
|
| nkeynes@231 | 75 |
|
| nkeynes@231 | 76 | test_slot_8: ! BT
|
| nkeynes@231 | 77 | add #1, r12
|
| nkeynes@231 | 78 | expect_exc 0x000001A0
|
| nkeynes@231 | 79 | test_slot_8_pc:
|
| nkeynes@231 | 80 | bsr test_slot_fail
|
| nkeynes@231 | 81 | bt test_slot_8_fail
|
| nkeynes@231 | 82 | test_slot_8_fail:
|
| nkeynes@231 | 83 | assert_exc_caught test_slot_str_k test_slot_8_pc
|
| nkeynes@231 | 84 |
|
| nkeynes@231 | 85 | test_slot_9: ! BF/S
|
| nkeynes@231 | 86 | add #1, r12
|
| nkeynes@231 | 87 | expect_exc 0x000001A0
|
| nkeynes@231 | 88 | test_slot_9_pc:
|
| nkeynes@231 | 89 | bsr test_slot_fail
|
| nkeynes@231 | 90 | bf/s test_slot_9_fail
|
| nkeynes@231 | 91 | test_slot_9_fail:
|
| nkeynes@231 | 92 | assert_exc_caught test_slot_str_k test_slot_9_pc
|
| nkeynes@231 | 93 |
|
| nkeynes@231 | 94 | test_slot_10: ! BT/S
|
| nkeynes@231 | 95 | add #1, r12
|
| nkeynes@231 | 96 | expect_exc 0x000001A0
|
| nkeynes@231 | 97 | test_slot_10_pc:
|
| nkeynes@231 | 98 | bsr test_slot_fail
|
| nkeynes@231 | 99 | bt/s test_slot_10_fail
|
| nkeynes@231 | 100 | test_slot_10_fail:
|
| nkeynes@231 | 101 | assert_exc_caught test_slot_str_k test_slot_10_pc
|
| nkeynes@233 | 102 | bra test_slot_11
|
| nkeynes@233 | 103 | nop
|
| nkeynes@233 | 104 | test_slot_str_k1:
|
| nkeynes@233 | 105 | .long test_slot_str
|
| nkeynes@231 | 106 |
|
| nkeynes@233 | 107 |
|
| nkeynes@231 | 108 | test_slot_11: ! TRAPA
|
| nkeynes@231 | 109 | add #1, r12
|
| nkeynes@231 | 110 | expect_exc 0x000001A0
|
| nkeynes@231 | 111 | test_slot_11_pc:
|
| nkeynes@231 | 112 | bsr test_slot_fail
|
| nkeynes@231 | 113 | trapa #12
|
| nkeynes@231 | 114 | assert_exc_caught test_slot_str_k test_slot_11_pc
|
| nkeynes@231 | 115 |
|
| nkeynes@231 | 116 | test_slot_12: ! LDC r0, sr
|
| nkeynes@231 | 117 | add #1, r12
|
| nkeynes@231 | 118 | expect_exc 0x000001A0
|
| nkeynes@231 | 119 | stc sr, r0
|
| nkeynes@231 | 120 | test_slot_12_pc:
|
| nkeynes@231 | 121 | bsr test_slot_fail
|
| nkeynes@231 | 122 | ldc r0, sr
|
| nkeynes@231 | 123 | assert_exc_caught test_slot_str_k test_slot_12_pc
|
| nkeynes@231 | 124 |
|
| nkeynes@231 | 125 | test_slot_13: ! LDC @r0, sr
|
| nkeynes@231 | 126 | add #1, r12
|
| nkeynes@231 | 127 | expect_exc 0x000001A0
|
| nkeynes@231 | 128 | stc sr, r1
|
| nkeynes@231 | 129 | mova test_slot_13_temp, r0
|
| nkeynes@231 | 130 | mov.l r1, @r0
|
| nkeynes@231 | 131 | test_slot_13_pc:
|
| nkeynes@231 | 132 | bsr test_slot_fail
|
| nkeynes@231 | 133 | ldc.l @r0+, sr
|
| nkeynes@231 | 134 | assert_exc_caught test_slot_str_k test_slot_13_pc
|
| nkeynes@231 | 135 | bra test_slot_14
|
| nkeynes@231 | 136 | nop
|
| nkeynes@231 | 137 | test_slot_13_temp:
|
| nkeynes@231 | 138 | .long 0
|
| nkeynes@231 | 139 |
|
| nkeynes@231 | 140 | test_slot_14: ! MOVA
|
| nkeynes@231 | 141 | add #1, r12
|
| nkeynes@231 | 142 | expect_exc 0x000001A0
|
| nkeynes@231 | 143 | test_slot_14_pc:
|
| nkeynes@231 | 144 | bsr test_slot_fail
|
| nkeynes@231 | 145 | mova test_slot_15, r0
|
| nkeynes@231 | 146 | assert_exc_caught test_slot_str_k test_slot_14_pc
|
| nkeynes@231 | 147 |
|
| nkeynes@231 | 148 | test_slot_15: ! MOV.W pcrel, Rn
|
| nkeynes@231 | 149 | add #1, r12
|
| nkeynes@231 | 150 | expect_exc 0x000001A0
|
| nkeynes@231 | 151 | test_slot_15_pc:
|
| nkeynes@231 | 152 | bsr test_slot_fail
|
| nkeynes@231 | 153 | mov.w test_slot_16, r0
|
| nkeynes@231 | 154 | assert_exc_caught test_slot_str_k test_slot_15_pc
|
| nkeynes@231 | 155 |
|
| nkeynes@231 | 156 | test_slot_16: ! MOV.L pcrel, Rn
|
| nkeynes@231 | 157 | add #1, r12
|
| nkeynes@231 | 158 | expect_exc 0x000001A0
|
| nkeynes@231 | 159 | test_slot_16_pc:
|
| nkeynes@231 | 160 | bsr test_slot_fail
|
| nkeynes@231 | 161 | mov.l test_slot_str_k, r0
|
| nkeynes@231 | 162 | assert_exc_caught test_slot_str_k test_slot_16_pc
|
| nkeynes@231 | 163 |
|
| nkeynes@231 | 164 | test_slot_17: ! "Undefined" 0xFFFD
|
| nkeynes@231 | 165 | add #1, r12
|
| nkeynes@231 | 166 | expect_exc 0x000001A0
|
| nkeynes@231 | 167 | test_slot_17_pc:
|
| nkeynes@231 | 168 | bsr test_slot_fail
|
| nkeynes@231 | 169 | .word 0xFFFD
|
| nkeynes@231 | 170 | assert_exc_caught test_slot_str_k test_slot_17_pc
|
| nkeynes@231 | 171 |
|
| nkeynes@358 | 172 | test_slot_18: ! "Undefined (FPU disabled)" 0xFFFD
|
| nkeynes@358 | 173 | add #1, r12
|
| nkeynes@358 | 174 | stc sr, r0
|
| nkeynes@358 | 175 | xor r1, r1
|
| nkeynes@358 | 176 | add #32, r1
|
| nkeynes@358 | 177 | shll2 r1
|
| nkeynes@358 | 178 | shll8 r1
|
| nkeynes@358 | 179 | or r0, r1
|
| nkeynes@358 | 180 | ldc r1, sr
|
| nkeynes@358 | 181 | expect_exc 0x000001A0
|
| nkeynes@358 | 182 | test_slot_18_pc:
|
| nkeynes@358 | 183 | bsr test_slot_fail
|
| nkeynes@358 | 184 | .word 0xFFFD
|
| nkeynes@358 | 185 | assert_exc_caught test_slot_str_k test_slot_18_pc
|
| nkeynes@358 | 186 | stc sr, r0
|
| nkeynes@358 | 187 | xor r1, r1
|
| nkeynes@358 | 188 | add #32, r1
|
| nkeynes@358 | 189 | shll2 r1
|
| nkeynes@358 | 190 | shll8 r1
|
| nkeynes@358 | 191 | not r1, r1
|
| nkeynes@358 | 192 | and r0, r1
|
| nkeynes@358 | 193 | ldc r1, sr
|
| nkeynes@358 | 194 |
|
| nkeynes@231 | 195 | !
|
| nkeynes@231 | 196 | ! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
|
| nkeynes@231 | 197 | ! in a delay slot (otherwise it's GENERAL_ILLEGAL)
|
| nkeynes@233 | 198 |
|
| nkeynes@358 | 199 | test_slot_19: ! LDC Rn, SPC in user mode
|
| nkeynes@357 | 200 | ! add #1, r12
|
| nkeynes@357 | 201 | ! expect_exc 0x000001A0
|
| nkeynes@357 | 202 | ! stc spc, r4
|
| nkeynes@357 | 203 | ! usermode
|
| nkeynes@358 | 204 | !test_slot_19_pc:
|
| nkeynes@357 | 205 | ! bsr test_slot_fail
|
| nkeynes@357 | 206 | ! ldc r4, spc
|
| nkeynes@357 | 207 | ! systemmode
|
| nkeynes@357 | 208 | ! assert_exc_caught test_slot_str_k test_slot_18_pc
|
| nkeynes@231 | 209 |
|
| nkeynes@233 | 210 |
|
| nkeynes@231 | 211 | test_slot_end:
|
| nkeynes@231 | 212 | end_test test_slot_str_k
|
| nkeynes@231 | 213 |
|
| nkeynes@231 | 214 | ! Returns after the delay slot, which should hit the "no exception" test
|
| nkeynes@231 | 215 | test_slot_fail:
|
| nkeynes@231 | 216 | rts
|
| nkeynes@231 | 217 | nop
|
| nkeynes@231 | 218 |
|
| nkeynes@231 | 219 | test_slot_str_k:
|
| nkeynes@231 | 220 | .long test_slot_str
|
| nkeynes@231 | 221 | test_slot_str:
|
| nkeynes@231 | 222 | .string "SLOT-ILLEGAL"
|
| nkeynes@231 | 223 |
|
| nkeynes@231 | 224 | |
lxdream 0.9.1