filename | src/sh4/sh4.c |
changeset | 953:f4a156508ad1 |
prev | 905:4c17ebd9ef5e |
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author | nkeynes |
date | Thu Jan 15 04:15:11 2009 +0000 (15 years ago) |
permissions | -rw-r--r-- |
last change | Add support for the Intel ICC compiler (C only, icc doesn't support Obj-C) - Rename Obj-C source to .m - Separate paths.c into paths_unix.c and paths_osx.m - Add configuration detection of ICC, along with specific opt flags |
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nkeynes@378 | 1 | /** |
nkeynes@586 | 2 | * $Id$ |
nkeynes@378 | 3 | * |
nkeynes@378 | 4 | * SH4 parent module for all CPU modes and SH4 peripheral |
nkeynes@378 | 5 | * modules. |
nkeynes@378 | 6 | * |
nkeynes@378 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@378 | 8 | * |
nkeynes@378 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@378 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@378 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@378 | 12 | * (at your option) any later version. |
nkeynes@378 | 13 | * |
nkeynes@378 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@378 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@378 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@378 | 17 | * GNU General Public License for more details. |
nkeynes@378 | 18 | */ |
nkeynes@378 | 19 | |
nkeynes@378 | 20 | #define MODULE sh4_module |
nkeynes@378 | 21 | #include <math.h> |
nkeynes@740 | 22 | #include <setjmp.h> |
nkeynes@617 | 23 | #include <assert.h> |
nkeynes@671 | 24 | #include "lxdream.h" |
nkeynes@422 | 25 | #include "dreamcast.h" |
nkeynes@669 | 26 | #include "mem.h" |
nkeynes@669 | 27 | #include "clock.h" |
nkeynes@669 | 28 | #include "eventq.h" |
nkeynes@669 | 29 | #include "syscall.h" |
nkeynes@669 | 30 | #include "sh4/intc.h" |
nkeynes@378 | 31 | #include "sh4/sh4core.h" |
nkeynes@378 | 32 | #include "sh4/sh4mmio.h" |
nkeynes@422 | 33 | #include "sh4/sh4stat.h" |
nkeynes@617 | 34 | #include "sh4/sh4trans.h" |
nkeynes@669 | 35 | #include "sh4/xltcache.h" |
nkeynes@378 | 36 | |
nkeynes@378 | 37 | void sh4_init( void ); |
nkeynes@526 | 38 | void sh4_xlat_init( void ); |
nkeynes@953 | 39 | void sh4_poweron_reset( void ); |
nkeynes@378 | 40 | void sh4_start( void ); |
nkeynes@378 | 41 | void sh4_stop( void ); |
nkeynes@378 | 42 | void sh4_save_state( FILE *f ); |
nkeynes@378 | 43 | int sh4_load_state( FILE *f ); |
nkeynes@378 | 44 | |
nkeynes@378 | 45 | uint32_t sh4_run_slice( uint32_t ); |
nkeynes@378 | 46 | uint32_t sh4_xlat_run_slice( uint32_t ); |
nkeynes@378 | 47 | |
nkeynes@953 | 48 | struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_poweron_reset, |
nkeynes@736 | 49 | sh4_start, sh4_run_slice, sh4_stop, |
nkeynes@736 | 50 | sh4_save_state, sh4_load_state }; |
nkeynes@378 | 51 | |
nkeynes@903 | 52 | struct sh4_registers sh4r __attribute__((aligned(16))); |
nkeynes@378 | 53 | struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; |
nkeynes@378 | 54 | int sh4_breakpoint_count = 0; |
nkeynes@953 | 55 | |
nkeynes@591 | 56 | gboolean sh4_starting = FALSE; |
nkeynes@526 | 57 | static gboolean sh4_use_translator = FALSE; |
nkeynes@740 | 58 | static jmp_buf sh4_exit_jmp_buf; |
nkeynes@740 | 59 | static gboolean sh4_running = FALSE; |
nkeynes@586 | 60 | struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 }; |
nkeynes@378 | 61 | |
nkeynes@740 | 62 | void sh4_translate_set_enabled( gboolean use ) |
nkeynes@378 | 63 | { |
nkeynes@736 | 64 | // No-op if the translator was not built |
nkeynes@526 | 65 | #ifdef SH4_TRANSLATOR |
nkeynes@378 | 66 | if( use ) { |
nkeynes@736 | 67 | sh4_translate_init(); |
nkeynes@378 | 68 | } |
nkeynes@526 | 69 | sh4_use_translator = use; |
nkeynes@526 | 70 | #endif |
nkeynes@378 | 71 | } |
nkeynes@378 | 72 | |
nkeynes@740 | 73 | gboolean sh4_translate_is_enabled() |
nkeynes@586 | 74 | { |
nkeynes@586 | 75 | return sh4_use_translator; |
nkeynes@586 | 76 | } |
nkeynes@586 | 77 | |
nkeynes@378 | 78 | void sh4_init(void) |
nkeynes@378 | 79 | { |
nkeynes@378 | 80 | register_io_regions( mmio_list_sh4mmio ); |
nkeynes@378 | 81 | MMU_init(); |
nkeynes@619 | 82 | TMU_init(); |
nkeynes@953 | 83 | xlat_cache_init(); |
nkeynes@953 | 84 | sh4_poweron_reset(); |
nkeynes@671 | 85 | #ifdef ENABLE_SH4STATS |
nkeynes@671 | 86 | sh4_stats_reset(); |
nkeynes@671 | 87 | #endif |
nkeynes@378 | 88 | } |
nkeynes@378 | 89 | |
nkeynes@591 | 90 | void sh4_start(void) |
nkeynes@591 | 91 | { |
nkeynes@591 | 92 | sh4_starting = TRUE; |
nkeynes@591 | 93 | } |
nkeynes@591 | 94 | |
nkeynes@953 | 95 | void sh4_poweron_reset(void) |
nkeynes@378 | 96 | { |
nkeynes@953 | 97 | /* zero everything out, for the sake of having a consistent state. */ |
nkeynes@953 | 98 | memset( &sh4r, 0, sizeof(sh4r) ); |
nkeynes@526 | 99 | if( sh4_use_translator ) { |
nkeynes@736 | 100 | xlat_flush_cache(); |
nkeynes@472 | 101 | } |
nkeynes@472 | 102 | |
nkeynes@378 | 103 | /* Resume running if we were halted */ |
nkeynes@378 | 104 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@378 | 105 | |
nkeynes@378 | 106 | sh4r.pc = 0xA0000000; |
nkeynes@378 | 107 | sh4r.new_pc= 0xA0000002; |
nkeynes@378 | 108 | sh4r.vbr = 0x00000000; |
nkeynes@378 | 109 | sh4r.fpscr = 0x00040001; |
nkeynes@953 | 110 | sh4_write_sr(0x700000F0); |
nkeynes@378 | 111 | |
nkeynes@378 | 112 | /* Mem reset will do this, but if we want to reset _just_ the SH4... */ |
nkeynes@378 | 113 | MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); |
nkeynes@378 | 114 | |
nkeynes@378 | 115 | /* Peripheral modules */ |
nkeynes@378 | 116 | CPG_reset(); |
nkeynes@378 | 117 | INTC_reset(); |
nkeynes@841 | 118 | PMM_reset(); |
nkeynes@378 | 119 | TMU_reset(); |
nkeynes@378 | 120 | SCIF_reset(); |
nkeynes@953 | 121 | MMU_reset(); |
nkeynes@378 | 122 | } |
nkeynes@378 | 123 | |
nkeynes@378 | 124 | void sh4_stop(void) |
nkeynes@378 | 125 | { |
nkeynes@526 | 126 | if( sh4_use_translator ) { |
nkeynes@736 | 127 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@736 | 128 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@736 | 129 | sh4r.in_delay_slot = FALSE; |
nkeynes@502 | 130 | } |
nkeynes@378 | 131 | |
nkeynes@378 | 132 | } |
nkeynes@378 | 133 | |
nkeynes@740 | 134 | /** |
nkeynes@740 | 135 | * Execute a timeslice using translated code only (ie translate/execute loop) |
nkeynes@740 | 136 | */ |
nkeynes@740 | 137 | uint32_t sh4_run_slice( uint32_t nanosecs ) |
nkeynes@740 | 138 | { |
nkeynes@740 | 139 | sh4r.slice_cycle = 0; |
nkeynes@740 | 140 | |
nkeynes@740 | 141 | if( sh4r.sh4_state != SH4_STATE_RUNNING ) { |
nkeynes@740 | 142 | sh4_sleep_run_slice(nanosecs); |
nkeynes@740 | 143 | } |
nkeynes@740 | 144 | |
nkeynes@740 | 145 | /* Setup for sudden vm exits */ |
nkeynes@740 | 146 | switch( setjmp(sh4_exit_jmp_buf) ) { |
nkeynes@740 | 147 | case CORE_EXIT_BREAKPOINT: |
nkeynes@740 | 148 | sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT ); |
nkeynes@740 | 149 | /* fallthrough */ |
nkeynes@740 | 150 | case CORE_EXIT_HALT: |
nkeynes@740 | 151 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) { |
nkeynes@740 | 152 | TMU_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 153 | SCIF_run_slice( sh4r.slice_cycle ); |
nkeynes@841 | 154 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 155 | dreamcast_stop(); |
nkeynes@740 | 156 | return sh4r.slice_cycle; |
nkeynes@740 | 157 | } |
nkeynes@740 | 158 | case CORE_EXIT_SYSRESET: |
nkeynes@740 | 159 | dreamcast_reset(); |
nkeynes@740 | 160 | break; |
nkeynes@740 | 161 | case CORE_EXIT_SLEEP: |
nkeynes@740 | 162 | sh4_sleep_run_slice(nanosecs); |
nkeynes@740 | 163 | break; |
nkeynes@740 | 164 | case CORE_EXIT_FLUSH_ICACHE: |
nkeynes@740 | 165 | xlat_flush_cache(); |
nkeynes@740 | 166 | break; |
nkeynes@740 | 167 | } |
nkeynes@740 | 168 | |
nkeynes@740 | 169 | sh4_running = TRUE; |
nkeynes@740 | 170 | |
nkeynes@740 | 171 | /* Execute the core's real slice */ |
nkeynes@740 | 172 | #ifdef SH4_TRANSLATOR |
nkeynes@740 | 173 | if( sh4_use_translator ) { |
nkeynes@740 | 174 | sh4_translate_run_slice(nanosecs); |
nkeynes@740 | 175 | } else { |
nkeynes@740 | 176 | sh4_emulate_run_slice(nanosecs); |
nkeynes@740 | 177 | } |
nkeynes@740 | 178 | #else |
nkeynes@740 | 179 | sh4_emulate_run_slice(nanosecs); |
nkeynes@740 | 180 | #endif |
nkeynes@740 | 181 | |
nkeynes@740 | 182 | /* And finish off the peripherals afterwards */ |
nkeynes@740 | 183 | |
nkeynes@740 | 184 | sh4_running = FALSE; |
nkeynes@740 | 185 | sh4_starting = FALSE; |
nkeynes@740 | 186 | sh4r.slice_cycle = nanosecs; |
nkeynes@740 | 187 | if( sh4r.sh4_state != SH4_STATE_STANDBY ) { |
nkeynes@740 | 188 | TMU_run_slice( nanosecs ); |
nkeynes@740 | 189 | SCIF_run_slice( nanosecs ); |
nkeynes@841 | 190 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@740 | 191 | } |
nkeynes@740 | 192 | return nanosecs; |
nkeynes@740 | 193 | } |
nkeynes@740 | 194 | |
nkeynes@740 | 195 | void sh4_core_exit( int exit_code ) |
nkeynes@740 | 196 | { |
nkeynes@740 | 197 | if( sh4_running ) { |
nkeynes@740 | 198 | #ifdef SH4_TRANSLATOR |
nkeynes@740 | 199 | if( sh4_use_translator ) { |
nkeynes@953 | 200 | if( exit_code == CORE_EXIT_EXCEPTION ) { |
nkeynes@953 | 201 | sh4_translate_exception_exit_recover(); |
nkeynes@953 | 202 | } else { |
nkeynes@953 | 203 | sh4_translate_exit_recover(); |
nkeynes@953 | 204 | } |
nkeynes@740 | 205 | } |
nkeynes@740 | 206 | #endif |
nkeynes@953 | 207 | if( exit_code != CORE_EXIT_EXCEPTION ) { |
nkeynes@953 | 208 | sh4_finalize_instruction(); |
nkeynes@953 | 209 | } |
nkeynes@740 | 210 | // longjmp back into sh4_run_slice |
nkeynes@740 | 211 | sh4_running = FALSE; |
nkeynes@740 | 212 | longjmp(sh4_exit_jmp_buf, exit_code); |
nkeynes@740 | 213 | } |
nkeynes@740 | 214 | } |
nkeynes@740 | 215 | |
nkeynes@378 | 216 | void sh4_save_state( FILE *f ) |
nkeynes@378 | 217 | { |
nkeynes@526 | 218 | if( sh4_use_translator ) { |
nkeynes@736 | 219 | /* If we were running with the translator, update new_pc and in_delay_slot */ |
nkeynes@736 | 220 | sh4r.new_pc = sh4r.pc+2; |
nkeynes@736 | 221 | sh4r.in_delay_slot = FALSE; |
nkeynes@401 | 222 | } |
nkeynes@401 | 223 | |
nkeynes@953 | 224 | fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f ); |
nkeynes@378 | 225 | MMU_save_state( f ); |
nkeynes@953 | 226 | CCN_save_state( f ); |
nkeynes@841 | 227 | PMM_save_state( f ); |
nkeynes@378 | 228 | INTC_save_state( f ); |
nkeynes@378 | 229 | TMU_save_state( f ); |
nkeynes@378 | 230 | SCIF_save_state( f ); |
nkeynes@378 | 231 | } |
nkeynes@378 | 232 | |
nkeynes@378 | 233 | int sh4_load_state( FILE * f ) |
nkeynes@378 | 234 | { |
nkeynes@526 | 235 | if( sh4_use_translator ) { |
nkeynes@736 | 236 | xlat_flush_cache(); |
nkeynes@472 | 237 | } |
nkeynes@953 | 238 | fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f ); |
nkeynes@953 | 239 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@378 | 240 | MMU_load_state( f ); |
nkeynes@953 | 241 | CCN_load_state( f ); |
nkeynes@841 | 242 | PMM_load_state( f ); |
nkeynes@378 | 243 | INTC_load_state( f ); |
nkeynes@378 | 244 | TMU_load_state( f ); |
nkeynes@378 | 245 | return SCIF_load_state( f ); |
nkeynes@378 | 246 | } |
nkeynes@378 | 247 | |
nkeynes@586 | 248 | void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 249 | { |
nkeynes@378 | 250 | sh4_breakpoints[sh4_breakpoint_count].address = pc; |
nkeynes@378 | 251 | sh4_breakpoints[sh4_breakpoint_count].type = type; |
nkeynes@586 | 252 | if( sh4_use_translator ) { |
nkeynes@736 | 253 | xlat_invalidate_word( pc ); |
nkeynes@586 | 254 | } |
nkeynes@378 | 255 | sh4_breakpoint_count++; |
nkeynes@378 | 256 | } |
nkeynes@378 | 257 | |
nkeynes@586 | 258 | gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type ) |
nkeynes@378 | 259 | { |
nkeynes@378 | 260 | int i; |
nkeynes@378 | 261 | |
nkeynes@378 | 262 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@736 | 263 | if( sh4_breakpoints[i].address == pc && |
nkeynes@736 | 264 | sh4_breakpoints[i].type == type ) { |
nkeynes@736 | 265 | while( ++i < sh4_breakpoint_count ) { |
nkeynes@736 | 266 | sh4_breakpoints[i-1].address = sh4_breakpoints[i].address; |
nkeynes@736 | 267 | sh4_breakpoints[i-1].type = sh4_breakpoints[i].type; |
nkeynes@736 | 268 | } |
nkeynes@736 | 269 | if( sh4_use_translator ) { |
nkeynes@736 | 270 | xlat_invalidate_word( pc ); |
nkeynes@736 | 271 | } |
nkeynes@736 | 272 | sh4_breakpoint_count--; |
nkeynes@736 | 273 | return TRUE; |
nkeynes@736 | 274 | } |
nkeynes@378 | 275 | } |
nkeynes@378 | 276 | return FALSE; |
nkeynes@378 | 277 | } |
nkeynes@378 | 278 | |
nkeynes@378 | 279 | int sh4_get_breakpoint( uint32_t pc ) |
nkeynes@378 | 280 | { |
nkeynes@378 | 281 | int i; |
nkeynes@378 | 282 | for( i=0; i<sh4_breakpoint_count; i++ ) { |
nkeynes@736 | 283 | if( sh4_breakpoints[i].address == pc ) |
nkeynes@736 | 284 | return sh4_breakpoints[i].type; |
nkeynes@378 | 285 | } |
nkeynes@378 | 286 | return 0; |
nkeynes@378 | 287 | } |
nkeynes@378 | 288 | |
nkeynes@401 | 289 | void sh4_set_pc( int pc ) |
nkeynes@401 | 290 | { |
nkeynes@401 | 291 | sh4r.pc = pc; |
nkeynes@401 | 292 | sh4r.new_pc = pc+2; |
nkeynes@401 | 293 | } |
nkeynes@401 | 294 | |
nkeynes@401 | 295 | |
nkeynes@401 | 296 | /******************************* Support methods ***************************/ |
nkeynes@401 | 297 | |
nkeynes@401 | 298 | static void sh4_switch_banks( ) |
nkeynes@401 | 299 | { |
nkeynes@401 | 300 | uint32_t tmp[8]; |
nkeynes@401 | 301 | |
nkeynes@401 | 302 | memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); |
nkeynes@401 | 303 | memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); |
nkeynes@401 | 304 | memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); |
nkeynes@401 | 305 | } |
nkeynes@401 | 306 | |
nkeynes@905 | 307 | void FASTCALL sh4_switch_fr_banks() |
nkeynes@669 | 308 | { |
nkeynes@669 | 309 | int i; |
nkeynes@669 | 310 | for( i=0; i<16; i++ ) { |
nkeynes@736 | 311 | float tmp = sh4r.fr[0][i]; |
nkeynes@736 | 312 | sh4r.fr[0][i] = sh4r.fr[1][i]; |
nkeynes@736 | 313 | sh4r.fr[1][i] = tmp; |
nkeynes@669 | 314 | } |
nkeynes@669 | 315 | } |
nkeynes@669 | 316 | |
nkeynes@905 | 317 | void FASTCALL sh4_write_sr( uint32_t newval ) |
nkeynes@401 | 318 | { |
nkeynes@586 | 319 | int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 320 | int newbank = (newval&SR_MDRB) == SR_MDRB; |
nkeynes@586 | 321 | if( oldbank != newbank ) |
nkeynes@401 | 322 | sh4_switch_banks(); |
nkeynes@822 | 323 | sh4r.sr = newval & SR_MASK; |
nkeynes@401 | 324 | sh4r.t = (newval&SR_T) ? 1 : 0; |
nkeynes@401 | 325 | sh4r.s = (newval&SR_S) ? 1 : 0; |
nkeynes@401 | 326 | sh4r.m = (newval&SR_M) ? 1 : 0; |
nkeynes@401 | 327 | sh4r.q = (newval&SR_Q) ? 1 : 0; |
nkeynes@953 | 328 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@401 | 329 | intc_mask_changed(); |
nkeynes@401 | 330 | } |
nkeynes@401 | 331 | |
nkeynes@905 | 332 | void FASTCALL sh4_write_fpscr( uint32_t newval ) |
nkeynes@669 | 333 | { |
nkeynes@669 | 334 | if( (sh4r.fpscr ^ newval) & FPSCR_FR ) { |
nkeynes@736 | 335 | sh4_switch_fr_banks(); |
nkeynes@669 | 336 | } |
nkeynes@823 | 337 | sh4r.fpscr = newval & FPSCR_MASK; |
nkeynes@953 | 338 | sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR)); |
nkeynes@669 | 339 | } |
nkeynes@669 | 340 | |
nkeynes@905 | 341 | uint32_t FASTCALL sh4_read_sr( void ) |
nkeynes@401 | 342 | { |
nkeynes@401 | 343 | /* synchronize sh4r.sr with the various bitflags */ |
nkeynes@401 | 344 | sh4r.sr &= SR_MQSTMASK; |
nkeynes@401 | 345 | if( sh4r.t ) sh4r.sr |= SR_T; |
nkeynes@401 | 346 | if( sh4r.s ) sh4r.sr |= SR_S; |
nkeynes@401 | 347 | if( sh4r.m ) sh4r.sr |= SR_M; |
nkeynes@401 | 348 | if( sh4r.q ) sh4r.sr |= SR_Q; |
nkeynes@401 | 349 | return sh4r.sr; |
nkeynes@401 | 350 | } |
nkeynes@401 | 351 | |
nkeynes@953 | 352 | /** |
nkeynes@953 | 353 | * Raise a CPU reset exception with the specified exception code. |
nkeynes@953 | 354 | */ |
nkeynes@953 | 355 | void FASTCALL sh4_raise_reset( int code ) |
nkeynes@953 | 356 | { |
nkeynes@953 | 357 | MMIO_WRITE(MMU,EXPEVT,code); |
nkeynes@953 | 358 | sh4r.vbr = 0x00000000; |
nkeynes@953 | 359 | sh4r.pc = 0xA0000000; |
nkeynes@953 | 360 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@953 | 361 | sh4r.in_delay_slot = 0; |
nkeynes@953 | 362 | sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)&(~SR_FD) ); |
nkeynes@953 | 363 | |
nkeynes@953 | 364 | /* Peripheral manual reset (FIXME: incomplete) */ |
nkeynes@953 | 365 | INTC_reset(); |
nkeynes@953 | 366 | SCIF_reset(); |
nkeynes@953 | 367 | MMU_reset(); |
nkeynes@953 | 368 | } |
nkeynes@401 | 369 | |
nkeynes@953 | 370 | void FASTCALL sh4_raise_tlb_multihit( sh4vma_t vpn ) |
nkeynes@953 | 371 | { |
nkeynes@953 | 372 | MMIO_WRITE( MMU, TEA, vpn ); |
nkeynes@953 | 373 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) ); |
nkeynes@953 | 374 | sh4_raise_reset( EXC_TLB_MULTI_HIT ); |
nkeynes@953 | 375 | } |
nkeynes@401 | 376 | |
nkeynes@401 | 377 | /** |
nkeynes@401 | 378 | * Raise a general CPU exception for the specified exception code. |
nkeynes@401 | 379 | * (NOT for TRAPA or TLB exceptions) |
nkeynes@401 | 380 | */ |
nkeynes@953 | 381 | void FASTCALL sh4_raise_exception( int code ) |
nkeynes@401 | 382 | { |
nkeynes@953 | 383 | if( sh4r.sr & SR_BL ) { |
nkeynes@953 | 384 | sh4_raise_reset( EXC_MANUAL_RESET ); |
nkeynes@401 | 385 | } else { |
nkeynes@953 | 386 | sh4r.spc = sh4r.pc; |
nkeynes@953 | 387 | sh4r.ssr = sh4_read_sr(); |
nkeynes@953 | 388 | sh4r.sgr = sh4r.r[15]; |
nkeynes@953 | 389 | MMIO_WRITE(MMU,EXPEVT, code); |
nkeynes@953 | 390 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION; |
nkeynes@953 | 391 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@953 | 392 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@953 | 393 | sh4r.in_delay_slot = 0; |
nkeynes@401 | 394 | } |
nkeynes@401 | 395 | } |
nkeynes@401 | 396 | |
nkeynes@953 | 397 | void FASTCALL sh4_raise_trap( int trap ) |
nkeynes@401 | 398 | { |
nkeynes@953 | 399 | MMIO_WRITE( MMU, TRA, trap<<2 ); |
nkeynes@953 | 400 | MMIO_WRITE( MMU, EXPEVT, EXC_TRAP ); |
nkeynes@953 | 401 | sh4r.spc = sh4r.pc; |
nkeynes@953 | 402 | sh4r.ssr = sh4_read_sr(); |
nkeynes@953 | 403 | sh4r.sgr = sh4r.r[15]; |
nkeynes@953 | 404 | sh4r.pc = sh4r.vbr + EXV_EXCEPTION; |
nkeynes@953 | 405 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@953 | 406 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@953 | 407 | sh4r.in_delay_slot = 0; |
nkeynes@953 | 408 | } |
nkeynes@953 | 409 | |
nkeynes@953 | 410 | void FASTCALL sh4_raise_tlb_exception( int code, sh4vma_t vpn ) |
nkeynes@953 | 411 | { |
nkeynes@953 | 412 | MMIO_WRITE( MMU, TEA, vpn ); |
nkeynes@953 | 413 | MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) ); |
nkeynes@953 | 414 | MMIO_WRITE( MMU, EXPEVT, code ); |
nkeynes@953 | 415 | sh4r.spc = sh4r.pc; |
nkeynes@953 | 416 | sh4r.ssr = sh4_read_sr(); |
nkeynes@953 | 417 | sh4r.sgr = sh4r.r[15]; |
nkeynes@953 | 418 | sh4r.pc = sh4r.vbr + EXV_TLBMISS; |
nkeynes@953 | 419 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@953 | 420 | sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); |
nkeynes@953 | 421 | sh4r.in_delay_slot = 0; |
nkeynes@401 | 422 | } |
nkeynes@401 | 423 | |
nkeynes@905 | 424 | void FASTCALL sh4_accept_interrupt( void ) |
nkeynes@401 | 425 | { |
nkeynes@401 | 426 | uint32_t code = intc_accept_interrupt(); |
nkeynes@953 | 427 | MMIO_WRITE( MMU, INTEVT, code ); |
nkeynes@401 | 428 | sh4r.ssr = sh4_read_sr(); |
nkeynes@401 | 429 | sh4r.spc = sh4r.pc; |
nkeynes@401 | 430 | sh4r.sgr = sh4r.r[15]; |
nkeynes@401 | 431 | sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); |
nkeynes@401 | 432 | sh4r.pc = sh4r.vbr + 0x600; |
nkeynes@401 | 433 | sh4r.new_pc = sh4r.pc + 2; |
nkeynes@401 | 434 | } |
nkeynes@401 | 435 | |
nkeynes@905 | 436 | void FASTCALL signsat48( void ) |
nkeynes@401 | 437 | { |
nkeynes@401 | 438 | if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL ) |
nkeynes@736 | 439 | sh4r.mac = 0xFFFF800000000000LL; |
nkeynes@401 | 440 | else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL ) |
nkeynes@736 | 441 | sh4r.mac = 0x00007FFFFFFFFFFFLL; |
nkeynes@401 | 442 | } |
nkeynes@401 | 443 | |
nkeynes@905 | 444 | void FASTCALL sh4_fsca( uint32_t anglei, float *fr ) |
nkeynes@401 | 445 | { |
nkeynes@401 | 446 | float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI; |
nkeynes@401 | 447 | *fr++ = cosf(angle); |
nkeynes@401 | 448 | *fr = sinf(angle); |
nkeynes@401 | 449 | } |
nkeynes@401 | 450 | |
nkeynes@617 | 451 | /** |
nkeynes@617 | 452 | * Enter sleep mode (eg by executing a SLEEP instruction). |
nkeynes@617 | 453 | * Sets sh4_state appropriately and ensures any stopping peripheral modules |
nkeynes@617 | 454 | * are up to date. |
nkeynes@617 | 455 | */ |
nkeynes@905 | 456 | void FASTCALL sh4_sleep(void) |
nkeynes@401 | 457 | { |
nkeynes@401 | 458 | if( MMIO_READ( CPG, STBCR ) & 0x80 ) { |
nkeynes@736 | 459 | sh4r.sh4_state = SH4_STATE_STANDBY; |
nkeynes@736 | 460 | /* Bring all running peripheral modules up to date, and then halt them. */ |
nkeynes@736 | 461 | TMU_run_slice( sh4r.slice_cycle ); |
nkeynes@736 | 462 | SCIF_run_slice( sh4r.slice_cycle ); |
nkeynes@841 | 463 | PMM_run_slice( sh4r.slice_cycle ); |
nkeynes@401 | 464 | } else { |
nkeynes@736 | 465 | if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) { |
nkeynes@736 | 466 | sh4r.sh4_state = SH4_STATE_DEEP_SLEEP; |
nkeynes@736 | 467 | /* Halt DMAC but other peripherals still running */ |
nkeynes@736 | 468 | |
nkeynes@736 | 469 | } else { |
nkeynes@736 | 470 | sh4r.sh4_state = SH4_STATE_SLEEP; |
nkeynes@736 | 471 | } |
nkeynes@617 | 472 | } |
nkeynes@740 | 473 | sh4_core_exit( CORE_EXIT_SLEEP ); |
nkeynes@401 | 474 | } |
nkeynes@401 | 475 | |
nkeynes@401 | 476 | /** |
nkeynes@617 | 477 | * Wakeup following sleep mode (IRQ or reset). Sets state back to running, |
nkeynes@617 | 478 | * and restarts any peripheral devices that were stopped. |
nkeynes@617 | 479 | */ |
nkeynes@617 | 480 | void sh4_wakeup(void) |
nkeynes@617 | 481 | { |
nkeynes@617 | 482 | switch( sh4r.sh4_state ) { |
nkeynes@617 | 483 | case SH4_STATE_STANDBY: |
nkeynes@736 | 484 | break; |
nkeynes@617 | 485 | case SH4_STATE_DEEP_SLEEP: |
nkeynes@736 | 486 | break; |
nkeynes@617 | 487 | case SH4_STATE_SLEEP: |
nkeynes@736 | 488 | break; |
nkeynes@617 | 489 | } |
nkeynes@617 | 490 | sh4r.sh4_state = SH4_STATE_RUNNING; |
nkeynes@617 | 491 | } |
nkeynes@617 | 492 | |
nkeynes@617 | 493 | /** |
nkeynes@617 | 494 | * Run a time slice (or portion of a timeslice) while the SH4 is sleeping. |
nkeynes@617 | 495 | * Returns when either the SH4 wakes up (interrupt received) or the end of |
nkeynes@617 | 496 | * the slice is reached. Updates sh4.slice_cycle with the exit time and |
nkeynes@617 | 497 | * returns the same value. |
nkeynes@617 | 498 | */ |
nkeynes@617 | 499 | uint32_t sh4_sleep_run_slice( uint32_t nanosecs ) |
nkeynes@617 | 500 | { |
nkeynes@617 | 501 | int sleep_state = sh4r.sh4_state; |
nkeynes@617 | 502 | assert( sleep_state != SH4_STATE_RUNNING ); |
nkeynes@736 | 503 | |
nkeynes@617 | 504 | while( sh4r.event_pending < nanosecs ) { |
nkeynes@736 | 505 | sh4r.slice_cycle = sh4r.event_pending; |
nkeynes@736 | 506 | if( sh4r.event_types & PENDING_EVENT ) { |
nkeynes@736 | 507 | event_execute(); |
nkeynes@736 | 508 | } |
nkeynes@736 | 509 | if( sh4r.event_types & PENDING_IRQ ) { |
nkeynes@736 | 510 | sh4_wakeup(); |
nkeynes@736 | 511 | return sh4r.slice_cycle; |
nkeynes@736 | 512 | } |
nkeynes@617 | 513 | } |
nkeynes@617 | 514 | sh4r.slice_cycle = nanosecs; |
nkeynes@617 | 515 | return sh4r.slice_cycle; |
nkeynes@617 | 516 | } |
nkeynes@617 | 517 | |
nkeynes@617 | 518 | |
nkeynes@617 | 519 | /** |
nkeynes@401 | 520 | * Compute the matrix tranform of fv given the matrix xf. |
nkeynes@401 | 521 | * Both fv and xf are word-swapped as per the sh4r.fr banks |
nkeynes@401 | 522 | */ |
nkeynes@905 | 523 | void FASTCALL sh4_ftrv( float *target ) |
nkeynes@401 | 524 | { |
nkeynes@401 | 525 | float fv[4] = { target[1], target[0], target[3], target[2] }; |
nkeynes@669 | 526 | target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] + |
nkeynes@736 | 527 | sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3]; |
nkeynes@669 | 528 | target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] + |
nkeynes@736 | 529 | sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3]; |
nkeynes@669 | 530 | target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] + |
nkeynes@736 | 531 | sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3]; |
nkeynes@669 | 532 | target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] + |
nkeynes@736 | 533 | sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3]; |
nkeynes@401 | 534 | } |
nkeynes@401 | 535 | |
nkeynes@597 | 536 | gboolean sh4_has_page( sh4vma_t vma ) |
nkeynes@597 | 537 | { |
nkeynes@597 | 538 | sh4addr_t addr = mmu_vma_to_phys_disasm(vma); |
nkeynes@597 | 539 | return addr != MMU_VMA_ERROR && mem_has_page(addr); |
nkeynes@597 | 540 | } |
.