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lxdream.org :: lxdream/test/testregs.c
lxdream 0.9.1
released Jun 29
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filename test/testregs.c
changeset 826:69f2c9f1e608
prev818:2e08d8237d33
author nkeynes
date Sat Dec 27 02:59:35 2008 +0000 (15 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode,
which tracks the field of the same name in sh4r - actually a little faster this way.
Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR
flag yet).

Also fixed the failure to check the flags in the common case (code address returned
by previous block) which took away the performance benefits, but oh well.
file annotate diff log raw
nkeynes@190
     1
/**
nkeynes@561
     2
 * $Id$
nkeynes@190
     3
 * 
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     4
 * Register mask tests. These are simple "write value to register and check
nkeynes@190
     5
 * that we read back what we expect" tests.
nkeynes@190
     6
 *
nkeynes@190
     7
 * Copyright (c) 2006 Nathan Keynes.
nkeynes@190
     8
 *
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     9
 * This program is free software; you can redistribute it and/or modify
nkeynes@190
    10
 * it under the terms of the GNU General Public License as published by
nkeynes@190
    11
 * the Free Software Foundation; either version 2 of the License, or
nkeynes@190
    12
 * (at your option) any later version.
nkeynes@190
    13
 *
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    14
 * This program is distributed in the hope that it will be useful,
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    15
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@190
    16
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    17
 * GNU General Public License for more details.
nkeynes@190
    18
 */
nkeynes@190
    19
nkeynes@190
    20
#include "lib.h"
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    21
#include <stdio.h>
nkeynes@190
    22
nkeynes@190
    23
/**
nkeynes@190
    24
 * Constant to mean "same as previous value". Can't be used otherwise.
nkeynes@190
    25
 */
nkeynes@190
    26
#define UNCHANGED 0xDEADBEEF
nkeynes@190
    27
nkeynes@190
    28
struct test {
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    29
    unsigned int reg;
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    30
    unsigned int write;
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    31
    unsigned int expect;
nkeynes@190
    32
};
nkeynes@190
    33
nkeynes@190
    34
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    35
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    36
struct test test_cases[] = {
nkeynes@332
    37
    { 0xA05F6800, 0xFFFFFFFF, 0x13FFFFE0 },
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    38
    { 0xA05F6800, 0x00000000, 0x10000000 },
nkeynes@332
    39
    { 0xA05F6804, 0xFFFFFFFF, 0x00FFFFE0 },
nkeynes@549
    40
//    { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },
nkeynes@549
    41
//    { 0xA05F6808, 0x00000000, 0x00000000 },  // DMA start
nkeynes@549
    42
//    { 0xA05F680C, 0xFFFFFFFF, 0x00000000 },  // Not a register afaik
nkeynes@728
    43
    { 0xA05F6810, 0x00000000, 0x08000000 },
nkeynes@728
    44
    { 0xA05F6810, 0xFFFFFFFF, 0x0FFFFFE0 },    
nkeynes@728
    45
    { 0xA05F6814, 0x00000000, 0x08000000 },
nkeynes@728
    46
    { 0xA05F6814, 0xFFFFFFFF, 0x0FFFFFE0 },
nkeynes@728
    47
    { 0xA05F6818, 0xFFFFFFFF, 0x00000001 },
nkeynes@728
    48
    { 0xA05F681C, 0xFFFFFFFF, 0x00000001 },
nkeynes@549
    49
//    { 0xA05F7400, 0xFFFFFFFF, 0x00000000 },  // Not a register
nkeynes@332
    50
    { 0xA05F7404, 0xFFFFFFFF, 0x1FFFFFE0 },
nkeynes@332
    51
    { 0xA05F7404, 0x00000000, 0x00000000 },
nkeynes@332
    52
    { 0xA05F7408, 0xFFFFFFFF, 0x01FFFFFE },
nkeynes@332
    53
    { 0xA05F740C, 0xFFFFFFFF, 0x00000001 },
nkeynes@549
    54
//    { 0xA05F7410, 0xFFFFFFFF, 0x00000000 },  // Not a register
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    55
    { 0xA05F7414, 0xFFFFFFFF, 0x00000001 },
nkeynes@549
    56
//    { 0xA05F7418, 0xFFFFFFFF, 0x00000001 },  // DMA start
nkeynes@549
    57
//    { 0xA05F741C, 0xFFFFFFFF, 0x00000000 },  // Not a register
nkeynes@332
    58
    { 0xA05F7800, 0xFFFFFFFF, 0x9FFFFFE0 },
nkeynes@332
    59
    { 0xA05F7800, 0x00000000, 0x00000000 },
nkeynes@332
    60
    { 0xA05F7804, 0xFFFFFFFF, 0x9FFFFFE0 },
nkeynes@332
    61
    { 0xA05F7808, 0xFFFFFFFF, 0x9FFFFFE0 },
nkeynes@549
    62
    { 0xA05F780C, 0xFFFFFFFF, 0x00000001 }, 
nkeynes@332
    63
    { 0xA05F7810, 0xFFFFFFFF, 0x00000007 },
nkeynes@332
    64
    { 0xA05F7814, 0xFFFFFFFF, 0x00000001 },
nkeynes@549
    65
//    { 0xA05F7818, 0xFFFFFFFF, 0x00000000 },  // DMA start
nkeynes@332
    66
    { 0xA05F781C, 0xFFFFFFFF, 0x00000037 },
nkeynes@190
    67
    { 0xA05F8000, 0xFFFFFFFF, 0x17FD11DB }, /* PVRID read-only */
nkeynes@190
    68
    { 0xA05F8004, 0xFFFFFFFF, 0x00000011 }, /* PVRVER read-only */
nkeynes@196
    69
    { 0xA05F8008, 0xFFFFFFFF, 0x00000007 }, /* Reset */
nkeynes@196
    70
    { 0xA05F8010, 0xFFFFFFFF, 0 },
nkeynes@190
    71
    //    { 0xA05F8014, 0xFFFFFFFF, 0x00000000 }, /* Render start */
nkeynes@190
    72
    { 0xA05F8018, 0xFFFFFFFF, 0x000007FF }, /* ??? */   
nkeynes@190
    73
    { 0xA05F801C, 0xFFFFFFFF, 0x00000000 }, /* ??? */   
nkeynes@190
    74
    { 0xA05F8020, 0xFFFFFFFF, 0x00F00000 }, /* Render poly buffer address ??? */
nkeynes@190
    75
    { 0xA05F8024, 0xFFFFFFFF, 0x00000000 }, /* ??? */
nkeynes@190
    76
    { 0xA05F8028, 0xFFFFFFFF, 0x00000000 }, /* ??? */   
nkeynes@190
    77
    { 0xA05F802C, 0xFFFFFFFF, 0x00FFFFFC }, /* Render Tile buffer address */
nkeynes@190
    78
    { 0xA05F8030, 0xFFFFFFFF, 0x00010101 }, /* Render TSP cache? */   
nkeynes@196
    79
    { 0xA05F8034, 0xFFFFFFFF, 0 },
nkeynes@196
    80
    { 0xA05F8038, 0xFFFFFFFF, 0 },
nkeynes@196
    81
    { 0xA05F803C, 0xFFFFFFFF, 0 },
nkeynes@190
    82
    { 0xA05F8040, 0xFFFFFFFF, 0x01FFFFFF }, /* Display border colour */   
nkeynes@190
    83
    { 0xA05F8044, 0xFFFFFFFF, 0x00FFFF7F }, /* Display config */   
nkeynes@190
    84
    { 0xA05F8048, 0xFFFFFFFF, 0x00FFFF0F }, /* Render config */
nkeynes@190
    85
    { 0xA05F804C, 0xFFFFFFFF, 0x000001FF }, /* Render size */
nkeynes@190
    86
    { 0xA05F8050, 0xFFFFFFFF, 0x00FFFFFC }, /* Display address 1 */ 
nkeynes@190
    87
    { 0xA05F8054, 0xFFFFFFFF, 0x00FFFFFC }, /* Display address 2 */
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    88
    { 0xA05F8058, 0xFFFFFFFF, 0x00000000 }, /* ??? */
nkeynes@190
    89
    { 0xA05F805C, 0xFFFFFFFF, 0x3FFFFFFF }, /* Display size */
nkeynes@190
    90
    { 0xA05F8060, 0xFFFFFFFF, 0x01FFFFFC }, /* Render address 1 */
nkeynes@190
    91
    { 0xA05F8064, 0xFFFFFFFF, 0x01FFFFFC }, /* Render address 2 */
nkeynes@190
    92
    { 0xA05F8068, 0xFFFFFFFF, 0x07FF07FF }, /* Render horizontal clip */
nkeynes@190
    93
    { 0xA05F806C, 0xFFFFFFFF, 0x03FF03FF }, /* Render vertical clip */
nkeynes@196
    94
    { 0xA05F8070, 0xFFFFFFFF, 0 },
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    95
    { 0xA05F8074, 0xFFFFFFFF, 0x000001FF }, /* Render shadow mode */
nkeynes@196
    96
    { 0xA05F8078, 0xFFFFFFFF, 0x7FFFFFFF }, /* Near z clip */
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    97
    { 0xA05F807C, 0xFFFFFFFF, 0x003FFFFF }, /* Render object config */
nkeynes@196
    98
    { 0xA05F8080, 0xFFFFFFFF, 0x00000007 }, /* ??? */
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    99
    { 0xA05F8084, 0xFFFFFFFF, 0x7FFFFFFF }, /* Render tsp clip */
nkeynes@196
   100
    { 0xA05F8088, 0xFFFFFFFF, 0xFFFFFFF0 }, /* Far z clip */
nkeynes@190
   101
    { 0xA05F808C, 0xFFFFFFFF, 0x1FFFFFFF }, /* Render background plane config */
nkeynes@196
   102
    { 0xA05F8090, 0xFFFFFFFF, 0 },
nkeynes@196
   103
    { 0xA05F8094, 0xFFFFFFFF, 0 },
nkeynes@190
   104
    { 0xA05F8098, 0xFFFFFFFF, 0x00FFFFF9 }, /* ISP config? */
nkeynes@196
   105
    { 0xA05F809C, 0xFFFFFFFF, 0 },
nkeynes@196
   106
    { 0xA05F80A0, 0xFFFFFFFF, 0x000000FF }, /* Vram cfg1? */
nkeynes@196
   107
    { 0xA05F80A4, 0xFFFFFFFF, 0x003FFFFF },
nkeynes@196
   108
    { 0xA05F80A8, 0xFFFFFFFF, 0x1FFFFFFF },
nkeynes@196
   109
    { 0xA05F80AC, 0xFFFFFFFF, 0 },
nkeynes@196
   110
    { 0xA05F80B0, 0xFFFFFFFF, 0x00FFFFFF },
nkeynes@196
   111
    { 0xA05F80B4, 0xFFFFFFFF, 0x00FFFFFF },
nkeynes@196
   112
    { 0xA05F80B8, 0xFFFFFFFF, 0x0000FFFF },
nkeynes@196
   113
    { 0xA05F80BC, 0xFFFFFFFF, 0xFFFFFFFF },
nkeynes@196
   114
    { 0xA05F80C0, 0xFFFFFFFF, 0xFFFFFFFF },
nkeynes@190
   115
    { 0xA05F80C4, 0xFFFFFFFF, UNCHANGED },  /* Gun pos */
nkeynes@190
   116
    { 0xA05F80C8, 0xFFFFFFFF, 0x03FF33FF }, /* Horizontal scanline irq */
nkeynes@190
   117
    { 0xA05F80CC, 0xFFFFFFFF, 0x03FF03FF }, /* Vertical scanline irq */
nkeynes@196
   118
    { 0xA05F80D0, 0xFFFFFFFF, 0x000003FF },
nkeynes@196
   119
    { 0xA05F80D4, 0xFFFFFFFF, 0x03FF03FF },
nkeynes@196
   120
    { 0xA05F80D8, 0xFFFFFFFF, 0x03FF03FF },
nkeynes@196
   121
    { 0xA05F80DC, 0xFFFFFFFF, 0x03FF03FF },
nkeynes@196
   122
    { 0xA05F80E0, 0xFFFFFFFF, 0xFFFFFF7F },
nkeynes@196
   123
    { 0xA05F80E4, 0xFFFFFFFF, 0x00031F1F },
nkeynes@196
   124
    { 0xA05F80E8, 0xFFFFFFFF, 0x003F01FF },
nkeynes@196
   125
    { 0xA05F80EC, 0xFFFFFFFF, 0x000003FF },
nkeynes@196
   126
    { 0xA05F80F0, 0xFFFFFFFF, 0x03FF03FF },
nkeynes@196
   127
    { 0xA05F80F4, 0xFFFFFFFF, 0x0007FFFF },
nkeynes@196
   128
    { 0xA05F80F8, 0xFFFFFFFF, 0 },
nkeynes@196
   129
    { 0xA05F80FC, 0xFFFFFFFF, 0 },
nkeynes@196
   130
    { 0xA05F8100, 0xFFFFFFFF, 0 },
nkeynes@196
   131
    { 0xA05F8104, 0xFFFFFFFF, 0 },
nkeynes@196
   132
    { 0xA05F8108, 0xFFFFFFFF, 0x00000003 },
nkeynes@196
   133
    { 0xA05F810C, 0xFFFFFFFF, UNCHANGED },
nkeynes@196
   134
    { 0xA05F8110, 0xFFFFFFFF, 0x000FFF3F },
nkeynes@196
   135
    { 0xA05F8114, 0xFFFFFFFF, UNCHANGED },
nkeynes@196
   136
    { 0xA05F8118, 0xFFFFFFFF, 0x0000FFFF },
nkeynes@196
   137
    { 0xA05F811C, 0xFFFFFFFF, 0x000000FF },
nkeynes@196
   138
    { 0xA05F8120, 0xFFFFFFFF, 0 },
nkeynes@190
   139
    { 0xA05F8124, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile matrix base */
nkeynes@190
   140
    { 0xA05F8128, 0xFFFFFFFF, 0x00FFFFFC }, /* TA Polygon base */
nkeynes@190
   141
    { 0xA05F812C, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile matrix end */
nkeynes@190
   142
    { 0xA05F8130, 0xFFFFFFFF, 0x00FFFFFC }, /* TA Polygon end */
nkeynes@190
   143
    { 0xA05F8134, 0xFFFFFFFF, UNCHANGED  }, /* TA Tilelist posn */
nkeynes@190
   144
    { 0xA05F8138, 0xFFFFFFFF, UNCHANGED  }, /* TA polygon posn */
nkeynes@190
   145
    { 0xA05F813C, 0xFFFFFFFF, 0x000F003F }, /* TA tile matrix size */
nkeynes@190
   146
    { 0xA05F8140, 0xFFFFFFFF, 0x00133333 }, /* TA object config */
nkeynes@190
   147
    { 0xA05F8144, 0xFFFFFFFF, 0x00000000 }, /* TA initialize */
nkeynes@196
   148
    { 0xA05F8148, 0xFFFFFFFF, 0x00FFFFF8 },
nkeynes@196
   149
    { 0xA05F814C, 0xFFFFFFFF, 0x01013F3F },
nkeynes@196
   150
    { 0xA05F8150, 0xFFFFFFFF, 0 },
nkeynes@196
   151
    { 0xA05F8154, 0xFFFFFFFF, 0 },
nkeynes@196
   152
    { 0xA05F8158, 0xFFFFFFFF, 0 },
nkeynes@196
   153
    { 0xA05F815C, 0xFFFFFFFF, 0 },
nkeynes@196
   154
    { 0xA05F8160, 0xFFFFFFFF, 0 },
nkeynes@190
   155
    { 0xA05F8164, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile list start */
nkeynes@196
   156
    { 0xA05F8168, 0xFFFFFFFF, 0 },
nkeynes@196
   157
    { 0xA05F816C, 0xFFFFFFFF, 0 },
nkeynes@196
   158
    { 0xA05F8170, 0xFFFFFFFF, 0 },
nkeynes@196
   159
    { 0xA05F8174, 0xFFFFFFFF, 0 },
nkeynes@196
   160
    { 0xA05F8178, 0xFFFFFFFF, 0 },
nkeynes@196
   161
    { 0xA05F817C, 0xFFFFFFFF, 0 },
nkeynes@196
   162
    { 0xA05F8180, 0xFFFFFFFF, 0 },
nkeynes@196
   163
    { 0xA05F8184, 0xFFFFFFFF, 0 },
nkeynes@196
   164
    { 0xA05F8188, 0xFFFFFFFF, 0 },
nkeynes@196
   165
    { 0xA05F818C, 0xFFFFFFFF, 0 },
nkeynes@196
   166
    { 0xA05F8190, 0xFFFFFFFF, 0 },
nkeynes@196
   167
    { 0xA05F8194, 0xFFFFFFFF, 0 },
nkeynes@196
   168
    { 0xA05F8198, 0xFFFFFFFF, 0 },
nkeynes@196
   169
    { 0xA05F819C, 0xFFFFFFFF, 0 },
nkeynes@196
   170
    { 0xA05F81A0, 0xFFFFFFFF, 0 },
nkeynes@196
   171
    { 0xA05F81A4, 0xFFFFFFFF, 0 },
nkeynes@196
   172
    { 0xA05F81A8, 0xFFFFFFFF, 0x00000001 },
nkeynes@196
   173
    { 0xA05F81A8, 0x00000000, 0x00000000 },    	
nkeynes@728
   174
    { 0xA05F81AC, 0xFFFFFFFF, 0x0300FFFF },
nkeynes@196
   175
    { 0xA05F81B0, 0xFFFFFFFF, 0 },
nkeynes@196
   176
    { 0xA05F81B4, 0xFFFFFFFF, 0 },
nkeynes@196
   177
    { 0xA05F81B8, 0xFFFFFFFF, 0 },
nkeynes@196
   178
    { 0xA05F81BC, 0xFFFFFFFF, 0 },
nkeynes@196
   179
    { 0xA05F81C0, 0xFFFFFFFF, 0 },
nkeynes@196
   180
    { 0xA05F81C4, 0xFFFFFFFF, 0 },
nkeynes@196
   181
    { 0xA05F81C8, 0xFFFFFFFF, 0 },
nkeynes@196
   182
    { 0xA05F81CC, 0xFFFFFFFF, 0 },
nkeynes@196
   183
    { 0xA05F81D0, 0xFFFFFFFF, 0 },
nkeynes@196
   184
    { 0xA05F81D4, 0xFFFFFFFF, 0 },
nkeynes@196
   185
    { 0xA05F81D8, 0xFFFFFFFF, 0 },
nkeynes@196
   186
    { 0xA05F81DC, 0xFFFFFFFF, 0 },
nkeynes@196
   187
    { 0xA05F81E0, 0xFFFFFFFF, 0 },
nkeynes@196
   188
    { 0xA05F81E4, 0xFFFFFFFF, 0 },
nkeynes@196
   189
    { 0xA05F81E8, 0xFFFFFFFF, 0 },
nkeynes@196
   190
    { 0xA05F81EC, 0xFFFFFFFF, 0 },
nkeynes@196
   191
    { 0xA05F81F0, 0xFFFFFFFF, 0 },
nkeynes@196
   192
    { 0xA05F81F4, 0xFFFFFFFF, 0 },
nkeynes@196
   193
    { 0xA05F81F8, 0xFFFFFFFF, 0 },
nkeynes@196
   194
    { 0xA05F81FC, 0xFFFFFFFF, 0 },
nkeynes@826
   195
    /* SH4 control regs */
nkeynes@826
   196
    { 0xFF000000, 0xFFFFFFFF, 0xFFFFFCFF },
nkeynes@826
   197
    { 0xFF000004, 0xFFFFFFFF, 0x1FFFFDFF },
nkeynes@826
   198
    { 0xFF000008, 0xFFFFFFFF, 0xFFFFFFFF },
nkeynes@826
   199
    { 0xFF00000C, 0xFFFFFFFF, 0xFFFFFFFF },
nkeynes@826
   200
    { 0xFF000010, 0xFFFFFFFF, 0xFCFCFF01 },
nkeynes@826
   201
    { 0xFF000010, 0, 0 },
nkeynes@817
   202
    { 0xFF00001C, 0xFFFFFFFF, 0x000081A7 },
nkeynes@826
   203
    { 0xFF000020, 0xFFFFFFFF, 0x000003FC },    
nkeynes@826
   204
    { 0xFF000024, 0xFFFFFFFF, 0x00000FFF },    
nkeynes@826
   205
    { 0xFF000028, 0xFFFFFFFF, 0x00000FFF },    
nkeynes@826
   206
    { 0xFF00002C, 0x7FFFFFFF, 0x00010007 },    
nkeynes@818
   207
    { 0xFF000030, 0xFFFFFFFF, 0x040205C1 },
nkeynes@818
   208
    { 0xFF000030, 0, 0x040205C1 },
nkeynes@826
   209
    { 0xFF000034, 0xFFFFFFFF, 0x0000000F },    
nkeynes@826
   210
    { 0xFF000038, 0xFFFFFFFF, 0x0000001C },    
nkeynes@826
   211
    { 0xFF00003C, 0xFFFFFFFF, 0x0000001C },    
nkeynes@190
   212
    { 0, 0, 0 } };
nkeynes@190
   213
    
nkeynes@190
   214
int main( int argc, char *argv[] )
nkeynes@190
   215
{
nkeynes@190
   216
    int i;
nkeynes@190
   217
    int failures = 0;
nkeynes@190
   218
    int tests = 0;
nkeynes@343
   219
nkeynes@343
   220
    ide_init();
nkeynes@190
   221
    
nkeynes@190
   222
    for( i=0; test_cases[i].reg != 0; i++ ) {
nkeynes@190
   223
    	unsigned int oldval = long_read( test_cases[i].reg );
nkeynes@190
   224
    	unsigned int newval;
nkeynes@190
   225
	long_write( test_cases[i].reg, test_cases[i].write );
nkeynes@190
   226
	newval = long_read( test_cases[i].reg );
nkeynes@190
   227
	if( test_cases[i].expect == UNCHANGED ) {
nkeynes@190
   228
	    if( newval != oldval ) {
nkeynes@190
   229
		fprintf( stderr, "Test %d (%08X) failed. Expected %08X but was %08X\n",
nkeynes@190
   230
		  	 i+1, test_cases[i].reg, oldval, newval );
nkeynes@190
   231
		failures++;
nkeynes@190
   232
	    }
nkeynes@190
   233
	} else {
nkeynes@190
   234
	    if( newval != test_cases[i].expect ) {
nkeynes@190
   235
		fprintf( stderr, "Test %d (%08X) failed. Expected %08X but was %08X\n",
nkeynes@190
   236
		  	 i+1, test_cases[i].reg, test_cases[i].expect, newval );
nkeynes@190
   237
		failures++;
nkeynes@190
   238
	    }
nkeynes@190
   239
	}
nkeynes@190
   240
	long_write( test_cases[i].reg, oldval );
nkeynes@190
   241
	tests++;
nkeynes@190
   242
    }
nkeynes@190
   243
nkeynes@190
   244
    fprintf( stdout, "%d/%d test cases passed successfully\n", (tests-failures), tests );
nkeynes@190
   245
    return failures;
nkeynes@190
   246
}
.