4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
24 #include "dreamcast.h"
29 #include "sh4/sh4core.h"
30 #include "sh4/sh4mmio.h"
33 #define SH4_CALLTRACE 1
35 #define MAX_INT 0x7FFFFFFF
36 #define MIN_INT 0x80000000
37 #define MAX_INTF 2147483647.0
38 #define MIN_INTF -2147483648.0
40 /********************** SH4 Module Definition ****************************/
42 uint32_t sh4_run_slice( uint32_t nanosecs )
47 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
48 sh4_sleep_run_slice(nanosecs);
51 if( sh4_breakpoint_count == 0 ) {
52 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
53 if( SH4_EVENT_PENDING() ) {
54 if( sh4r.event_types & PENDING_EVENT ) {
57 /* Eventq execute may (quite likely) deliver an immediate IRQ */
58 if( sh4r.event_types & PENDING_IRQ ) {
59 sh4_accept_interrupt();
62 if( !sh4_execute_instruction() ) {
67 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
68 if( SH4_EVENT_PENDING() ) {
69 if( sh4r.event_types & PENDING_EVENT ) {
72 /* Eventq execute may (quite likely) deliver an immediate IRQ */
73 if( sh4r.event_types & PENDING_IRQ ) {
74 sh4_accept_interrupt();
78 if( !sh4_execute_instruction() )
80 #ifdef ENABLE_DEBUG_MODE
81 for( i=0; i<sh4_breakpoint_count; i++ ) {
82 if( sh4_breakpoints[i].address == sh4r.pc ) {
86 if( i != sh4_breakpoint_count ) {
88 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
89 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
96 /* If we aborted early, but the cpu is still technically running,
97 * we're doing a hard abort - cut the timeslice back to what we
100 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
101 nanosecs = sh4r.slice_cycle;
103 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
104 TMU_run_slice( nanosecs );
105 SCIF_run_slice( nanosecs );
110 /********************** SH4 emulation core ****************************/
112 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
113 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
115 #if(SH4_CALLTRACE == 1)
116 #define MAX_CALLSTACK 32
117 static struct call_stack {
119 sh4addr_t target_addr;
120 sh4addr_t stack_pointer;
121 } call_stack[MAX_CALLSTACK];
123 static int call_stack_depth = 0;
124 int sh4_call_trace_on = 0;
126 static inline void trace_call( sh4addr_t source, sh4addr_t dest )
128 if( call_stack_depth < MAX_CALLSTACK ) {
129 call_stack[call_stack_depth].call_addr = source;
130 call_stack[call_stack_depth].target_addr = dest;
131 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
136 static inline void trace_return( sh4addr_t source, sh4addr_t dest )
138 if( call_stack_depth > 0 ) {
143 void fprint_stack_trace( FILE *f )
145 int i = call_stack_depth -1;
146 if( i >= MAX_CALLSTACK )
147 i = MAX_CALLSTACK - 1;
148 for( ; i >= 0; i-- ) {
149 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
150 (call_stack_depth - i), call_stack[i].call_addr,
151 call_stack[i].target_addr, call_stack[i].stack_pointer );
155 #define TRACE_CALL( source, dest ) trace_call(source, dest)
156 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
158 #define TRACE_CALL( dest, rts )
159 #define TRACE_RETURN( source, dest )
162 #define MEM_READ_BYTE( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_byte(memtmp); }
163 #define MEM_READ_WORD( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_word(memtmp); }
164 #define MEM_READ_LONG( addr, val ) memtmp = mmu_vma_to_phys_read(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { val = sh4_read_long(memtmp); }
165 #define MEM_WRITE_BYTE( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_byte(memtmp, val); }
166 #define MEM_WRITE_WORD( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_word(memtmp, val); }
167 #define MEM_WRITE_LONG( addr, val ) memtmp = mmu_vma_to_phys_write(addr); if( memtmp == MMU_VMA_ERROR ) { return TRUE; } else { sh4_write_long(memtmp, val); }
169 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
171 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
172 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
174 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
175 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
176 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
177 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
178 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
180 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
181 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
182 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
184 static void sh4_write_float( uint32_t addr, int reg )
186 if( IS_FPU_DOUBLESIZE() ) {
188 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
189 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
191 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
192 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
195 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
199 static void sh4_read_float( uint32_t addr, int reg )
201 if( IS_FPU_DOUBLESIZE() ) {
203 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
204 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
206 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
207 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
210 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
214 gboolean sh4_execute_instruction( void )
221 int64_t memtmp; // temporary holder for memory reads
225 if( pc > 0xFFFFFF00 ) {
227 syscall_invoke( pc );
228 sh4r.in_delay_slot = 0;
229 pc = sh4r.pc = sh4r.pr;
230 sh4r.new_pc = sh4r.pc + 2;
234 /* Read instruction */
235 if( !IS_IN_ICACHE(pc) ) {
236 if( !mmu_update_icache(pc) ) {
237 // Fault - look for the fault handler
238 if( !mmu_update_icache(sh4r.pc) ) {
239 // double fault - halt
240 ERROR( "Double fault - halting" );
247 assert( IS_IN_ICACHE(pc) );
248 ir = *(uint16_t *)GET_ICACHE_PTR(sh4r.pc);
249 switch( (ir&0xF000) >> 12 ) {
253 switch( (ir&0x80) >> 7 ) {
255 switch( (ir&0x70) >> 4 ) {
258 uint32_t Rn = ((ir>>8)&0xF);
260 sh4r.r[Rn] = sh4_read_sr();
265 uint32_t Rn = ((ir>>8)&0xF);
266 sh4r.r[Rn] = sh4r.gbr;
271 uint32_t Rn = ((ir>>8)&0xF);
273 sh4r.r[Rn] = sh4r.vbr;
278 uint32_t Rn = ((ir>>8)&0xF);
280 sh4r.r[Rn] = sh4r.ssr;
285 uint32_t Rn = ((ir>>8)&0xF);
287 sh4r.r[Rn] = sh4r.spc;
296 { /* STC Rm_BANK, Rn */
297 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
299 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
305 switch( (ir&0xF0) >> 4 ) {
308 uint32_t Rn = ((ir>>8)&0xF);
310 CHECKDEST( pc + 4 + sh4r.r[Rn] );
311 sh4r.in_delay_slot = 1;
312 sh4r.pr = sh4r.pc + 4;
313 sh4r.pc = sh4r.new_pc;
314 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
315 TRACE_CALL( pc, sh4r.new_pc );
321 uint32_t Rn = ((ir>>8)&0xF);
323 CHECKDEST( pc + 4 + sh4r.r[Rn] );
324 sh4r.in_delay_slot = 1;
325 sh4r.pc = sh4r.new_pc;
326 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
332 uint32_t Rn = ((ir>>8)&0xF);
334 if( (tmp & 0xFC000000) == 0xE0000000 ) {
335 sh4_flush_store_queue(tmp);
341 uint32_t Rn = ((ir>>8)&0xF);
346 uint32_t Rn = ((ir>>8)&0xF);
351 uint32_t Rn = ((ir>>8)&0xF);
355 { /* MOVCA.L R0, @Rn */
356 uint32_t Rn = ((ir>>8)&0xF);
359 MEM_WRITE_LONG( tmp, R0 );
368 { /* MOV.B Rm, @(R0, Rn) */
369 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
370 MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
374 { /* MOV.W Rm, @(R0, Rn) */
375 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
376 CHECKWALIGN16( R0 + sh4r.r[Rn] );
377 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
381 { /* MOV.L Rm, @(R0, Rn) */
382 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
383 CHECKWALIGN32( R0 + sh4r.r[Rn] );
384 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
389 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
390 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
391 (sh4r.r[Rm] * sh4r.r[Rn]);
395 switch( (ir&0xFF0) >> 4 ) {
432 switch( (ir&0xF0) >> 4 ) {
440 sh4r.m = sh4r.q = sh4r.t = 0;
445 uint32_t Rn = ((ir>>8)&0xF);
455 switch( (ir&0xF0) >> 4 ) {
458 uint32_t Rn = ((ir>>8)&0xF);
459 sh4r.r[Rn] = (sh4r.mac>>32);
464 uint32_t Rn = ((ir>>8)&0xF);
465 sh4r.r[Rn] = (uint32_t)sh4r.mac;
470 uint32_t Rn = ((ir>>8)&0xF);
471 sh4r.r[Rn] = sh4r.pr;
476 uint32_t Rn = ((ir>>8)&0xF);
478 sh4r.r[Rn] = sh4r.sgr;
483 uint32_t Rn = ((ir>>8)&0xF);
485 sh4r.r[Rn] = sh4r.fpul;
489 { /* STS FPSCR, Rn */
490 uint32_t Rn = ((ir>>8)&0xF);
492 sh4r.r[Rn] = sh4r.fpscr;
497 uint32_t Rn = ((ir>>8)&0xF);
498 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
507 switch( (ir&0xFF0) >> 4 ) {
511 CHECKDEST( sh4r.pr );
512 sh4r.in_delay_slot = 1;
513 sh4r.pc = sh4r.new_pc;
514 sh4r.new_pc = sh4r.pr;
515 TRACE_RETURN( pc, sh4r.new_pc );
521 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
522 sh4r.sh4_state = SH4_STATE_STANDBY;
524 sh4r.sh4_state = SH4_STATE_SLEEP;
526 return FALSE; /* Halt CPU */
532 CHECKDEST( sh4r.spc );
534 sh4r.in_delay_slot = 1;
535 sh4r.pc = sh4r.new_pc;
536 sh4r.new_pc = sh4r.spc;
537 sh4_write_sr( sh4r.ssr );
547 { /* MOV.B @(R0, Rm), Rn */
548 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
549 MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );
553 { /* MOV.W @(R0, Rm), Rn */
554 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
555 CHECKRALIGN16( R0 + sh4r.r[Rm] );
556 MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );
560 { /* MOV.L @(R0, Rm), Rn */
561 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
562 CHECKRALIGN32( R0 + sh4r.r[Rm] );
563 MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );
567 { /* MAC.L @Rm+, @Rn+ */
568 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
571 CHECKRALIGN32( sh4r.r[Rn] );
572 MEM_READ_LONG(sh4r.r[Rn], tmp);
573 tmpl = SIGNEXT32(tmp);
574 MEM_READ_LONG(sh4r.r[Rn]+4, tmp);
575 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
578 CHECKRALIGN32( sh4r.r[Rm] );
579 CHECKRALIGN32( sh4r.r[Rn] );
580 MEM_READ_LONG(sh4r.r[Rn], tmp);
581 tmpl = SIGNEXT32(tmp);
582 MEM_READ_LONG(sh4r.r[Rm], tmp);
583 tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;
588 /* 48-bit Saturation. Yuch */
589 if( tmpl < (int64_t)0xFFFF800000000000LL )
590 tmpl = 0xFFFF800000000000LL;
591 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
592 tmpl = 0x00007FFFFFFFFFFFLL;
603 { /* MOV.L Rm, @(disp, Rn) */
604 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
605 tmp = sh4r.r[Rn] + disp;
606 CHECKWALIGN32( tmp );
607 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
613 { /* MOV.B Rm, @Rn */
614 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
615 MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
619 { /* MOV.W Rm, @Rn */
620 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
621 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
625 { /* MOV.L Rm, @Rn */
626 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
627 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
631 { /* MOV.B Rm, @-Rn */
632 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
633 MEM_WRITE_BYTE( sh4r.r[Rn]-1, sh4r.r[Rm] ); sh4r.r[Rn]--;
637 { /* MOV.W Rm, @-Rn */
638 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
639 CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn]-2, sh4r.r[Rm] ); sh4r.r[Rn] -= 2;
643 { /* MOV.L Rm, @-Rn */
644 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
645 CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r[Rm] ); sh4r.r[Rn] -= 4;
650 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
651 sh4r.q = sh4r.r[Rn]>>31;
652 sh4r.m = sh4r.r[Rm]>>31;
653 sh4r.t = sh4r.q ^ sh4r.m;
658 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
659 sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
664 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
665 sh4r.r[Rn] &= sh4r.r[Rm];
670 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
671 sh4r.r[Rn] ^= sh4r.r[Rm];
676 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
677 sh4r.r[Rn] |= sh4r.r[Rm];
681 { /* CMP/STR Rm, Rn */
682 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
683 /* set T = 1 if any byte in RM & RN is the same */
684 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
685 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
686 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
691 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
692 sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
696 { /* MULU.W Rm, Rn */
697 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
698 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
699 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
703 { /* MULS.W Rm, Rn */
704 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
705 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
706 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
717 { /* CMP/EQ Rm, Rn */
718 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
719 sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
723 { /* CMP/HS Rm, Rn */
724 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
725 sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
729 { /* CMP/GE Rm, Rn */
730 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
731 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
736 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
737 /* This is derived from the sh4 manual with some simplifications */
738 uint32_t tmp0, tmp1, tmp2, dir;
740 dir = sh4r.q ^ sh4r.m;
741 sh4r.q = (sh4r.r[Rn] >> 31);
743 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
747 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
750 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
752 sh4r.q ^= sh4r.m ^ tmp1;
753 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
757 { /* DMULU.L Rm, Rn */
758 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
759 sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
763 { /* CMP/HI Rm, Rn */
764 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
765 sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
769 { /* CMP/GT Rm, Rn */
770 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
771 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
776 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
777 sh4r.r[Rn] -= sh4r.r[Rm];
782 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
784 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
785 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
789 UNIMP(ir); /* SUBV Rm, Rn */
793 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
794 sh4r.r[Rn] += sh4r.r[Rm];
798 { /* DMULS.L Rm, Rn */
799 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
800 sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
805 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
807 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
808 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
813 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
814 tmp = sh4r.r[Rn] + sh4r.r[Rm];
815 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
827 switch( (ir&0xF0) >> 4 ) {
830 uint32_t Rn = ((ir>>8)&0xF);
831 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
836 uint32_t Rn = ((ir>>8)&0xF);
838 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
843 uint32_t Rn = ((ir>>8)&0xF);
844 sh4r.t = sh4r.r[Rn] >> 31;
854 switch( (ir&0xF0) >> 4 ) {
857 uint32_t Rn = ((ir>>8)&0xF);
858 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
863 uint32_t Rn = ((ir>>8)&0xF);
864 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
869 uint32_t Rn = ((ir>>8)&0xF);
870 sh4r.t = sh4r.r[Rn] & 0x00000001;
871 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
880 switch( (ir&0xF0) >> 4 ) {
882 { /* STS.L MACH, @-Rn */
883 uint32_t Rn = ((ir>>8)&0xF);
884 CHECKWALIGN32( sh4r.r[Rn] );
885 MEM_WRITE_LONG( sh4r.r[Rn]-4, (sh4r.mac>>32) );
890 { /* STS.L MACL, @-Rn */
891 uint32_t Rn = ((ir>>8)&0xF);
892 CHECKWALIGN32( sh4r.r[Rn] );
893 MEM_WRITE_LONG( sh4r.r[Rn]-4, (uint32_t)sh4r.mac );
898 { /* STS.L PR, @-Rn */
899 uint32_t Rn = ((ir>>8)&0xF);
900 CHECKWALIGN32( sh4r.r[Rn] );
901 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.pr );
906 { /* STC.L SGR, @-Rn */
907 uint32_t Rn = ((ir>>8)&0xF);
909 CHECKWALIGN32( sh4r.r[Rn] );
910 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.sgr );
915 { /* STS.L FPUL, @-Rn */
916 uint32_t Rn = ((ir>>8)&0xF);
918 CHECKWALIGN32( sh4r.r[Rn] );
919 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
924 { /* STS.L FPSCR, @-Rn */
925 uint32_t Rn = ((ir>>8)&0xF);
927 CHECKWALIGN32( sh4r.r[Rn] );
928 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
933 { /* STC.L DBR, @-Rn */
934 uint32_t Rn = ((ir>>8)&0xF);
936 CHECKWALIGN32( sh4r.r[Rn] );
937 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.dbr );
947 switch( (ir&0x80) >> 7 ) {
949 switch( (ir&0x70) >> 4 ) {
951 { /* STC.L SR, @-Rn */
952 uint32_t Rn = ((ir>>8)&0xF);
954 CHECKWALIGN32( sh4r.r[Rn] );
955 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4_read_sr() );
960 { /* STC.L GBR, @-Rn */
961 uint32_t Rn = ((ir>>8)&0xF);
962 CHECKWALIGN32( sh4r.r[Rn] );
963 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.gbr );
968 { /* STC.L VBR, @-Rn */
969 uint32_t Rn = ((ir>>8)&0xF);
971 CHECKWALIGN32( sh4r.r[Rn] );
972 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.vbr );
977 { /* STC.L SSR, @-Rn */
978 uint32_t Rn = ((ir>>8)&0xF);
980 CHECKWALIGN32( sh4r.r[Rn] );
981 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.ssr );
986 { /* STC.L SPC, @-Rn */
987 uint32_t Rn = ((ir>>8)&0xF);
989 CHECKWALIGN32( sh4r.r[Rn] );
990 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.spc );
1000 { /* STC.L Rm_BANK, @-Rn */
1001 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
1003 CHECKWALIGN32( sh4r.r[Rn] );
1004 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.r_bank[Rm_BANK] );
1011 switch( (ir&0xF0) >> 4 ) {
1014 uint32_t Rn = ((ir>>8)&0xF);
1015 sh4r.t = sh4r.r[Rn] >> 31;
1017 sh4r.r[Rn] |= sh4r.t;
1022 uint32_t Rn = ((ir>>8)&0xF);
1023 tmp = sh4r.r[Rn] >> 31;
1025 sh4r.r[Rn] |= sh4r.t;
1035 switch( (ir&0xF0) >> 4 ) {
1038 uint32_t Rn = ((ir>>8)&0xF);
1039 sh4r.t = sh4r.r[Rn] & 0x00000001;
1041 sh4r.r[Rn] |= (sh4r.t << 31);
1046 uint32_t Rn = ((ir>>8)&0xF);
1047 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
1052 uint32_t Rn = ((ir>>8)&0xF);
1053 tmp = sh4r.r[Rn] & 0x00000001;
1055 sh4r.r[Rn] |= (sh4r.t << 31 );
1065 switch( (ir&0xF0) >> 4 ) {
1067 { /* LDS.L @Rm+, MACH */
1068 uint32_t Rm = ((ir>>8)&0xF);
1069 CHECKRALIGN32( sh4r.r[Rm] );
1070 MEM_READ_LONG(sh4r.r[Rm], tmp);
1071 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1072 (((uint64_t)tmp)<<32);
1077 { /* LDS.L @Rm+, MACL */
1078 uint32_t Rm = ((ir>>8)&0xF);
1079 CHECKRALIGN32( sh4r.r[Rm] );
1080 MEM_READ_LONG(sh4r.r[Rm], tmp);
1081 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1082 (uint64_t)((uint32_t)tmp);
1087 { /* LDS.L @Rm+, PR */
1088 uint32_t Rm = ((ir>>8)&0xF);
1089 CHECKRALIGN32( sh4r.r[Rm] );
1090 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );
1095 { /* LDC.L @Rm+, SGR */
1096 uint32_t Rm = ((ir>>8)&0xF);
1098 CHECKRALIGN32( sh4r.r[Rm] );
1099 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);
1104 { /* LDS.L @Rm+, FPUL */
1105 uint32_t Rm = ((ir>>8)&0xF);
1107 CHECKRALIGN32( sh4r.r[Rm] );
1108 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
1113 { /* LDS.L @Rm+, FPSCR */
1114 uint32_t Rm = ((ir>>8)&0xF);
1116 CHECKRALIGN32( sh4r.r[Rm] );
1117 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
1119 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1123 { /* LDC.L @Rm+, DBR */
1124 uint32_t Rm = ((ir>>8)&0xF);
1126 CHECKRALIGN32( sh4r.r[Rm] );
1127 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);
1137 switch( (ir&0x80) >> 7 ) {
1139 switch( (ir&0x70) >> 4 ) {
1141 { /* LDC.L @Rm+, SR */
1142 uint32_t Rm = ((ir>>8)&0xF);
1145 CHECKWALIGN32( sh4r.r[Rm] );
1146 MEM_READ_LONG(sh4r.r[Rm], tmp);
1147 sh4_write_sr( tmp );
1152 { /* LDC.L @Rm+, GBR */
1153 uint32_t Rm = ((ir>>8)&0xF);
1154 CHECKRALIGN32( sh4r.r[Rm] );
1155 MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);
1160 { /* LDC.L @Rm+, VBR */
1161 uint32_t Rm = ((ir>>8)&0xF);
1163 CHECKRALIGN32( sh4r.r[Rm] );
1164 MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);
1169 { /* LDC.L @Rm+, SSR */
1170 uint32_t Rm = ((ir>>8)&0xF);
1172 CHECKRALIGN32( sh4r.r[Rm] );
1173 MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);
1178 { /* LDC.L @Rm+, SPC */
1179 uint32_t Rm = ((ir>>8)&0xF);
1181 CHECKRALIGN32( sh4r.r[Rm] );
1182 MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);
1192 { /* LDC.L @Rm+, Rn_BANK */
1193 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1195 CHECKRALIGN32( sh4r.r[Rm] );
1196 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );
1203 switch( (ir&0xF0) >> 4 ) {
1206 uint32_t Rn = ((ir>>8)&0xF);
1212 uint32_t Rn = ((ir>>8)&0xF);
1218 uint32_t Rn = ((ir>>8)&0xF);
1228 switch( (ir&0xF0) >> 4 ) {
1231 uint32_t Rn = ((ir>>8)&0xF);
1237 uint32_t Rn = ((ir>>8)&0xF);
1243 uint32_t Rn = ((ir>>8)&0xF);
1253 switch( (ir&0xF0) >> 4 ) {
1255 { /* LDS Rm, MACH */
1256 uint32_t Rm = ((ir>>8)&0xF);
1257 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
1258 (((uint64_t)sh4r.r[Rm])<<32);
1262 { /* LDS Rm, MACL */
1263 uint32_t Rm = ((ir>>8)&0xF);
1264 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1265 (uint64_t)((uint32_t)(sh4r.r[Rm]));
1270 uint32_t Rm = ((ir>>8)&0xF);
1271 sh4r.pr = sh4r.r[Rm];
1276 uint32_t Rm = ((ir>>8)&0xF);
1278 sh4r.sgr = sh4r.r[Rm];
1282 { /* LDS Rm, FPUL */
1283 uint32_t Rm = ((ir>>8)&0xF);
1285 sh4r.fpul = sh4r.r[Rm];
1289 { /* LDS Rm, FPSCR */
1290 uint32_t Rm = ((ir>>8)&0xF);
1292 sh4r.fpscr = sh4r.r[Rm];
1293 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1298 uint32_t Rm = ((ir>>8)&0xF);
1300 sh4r.dbr = sh4r.r[Rm];
1309 switch( (ir&0xF0) >> 4 ) {
1312 uint32_t Rn = ((ir>>8)&0xF);
1313 CHECKDEST( sh4r.r[Rn] );
1315 sh4r.in_delay_slot = 1;
1316 sh4r.pc = sh4r.new_pc;
1317 sh4r.new_pc = sh4r.r[Rn];
1319 TRACE_CALL( pc, sh4r.new_pc );
1325 uint32_t Rn = ((ir>>8)&0xF);
1326 MEM_READ_BYTE( sh4r.r[Rn], tmp );
1327 sh4r.t = ( tmp == 0 ? 1 : 0 );
1328 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
1333 uint32_t Rn = ((ir>>8)&0xF);
1334 CHECKDEST( sh4r.r[Rn] );
1336 sh4r.in_delay_slot = 1;
1337 sh4r.pc = sh4r.new_pc;
1338 sh4r.new_pc = sh4r.r[Rn];
1349 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1351 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1352 else if( (tmp & 0x1F) == 0 )
1353 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
1355 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
1360 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1362 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
1363 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
1364 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
1368 switch( (ir&0x80) >> 7 ) {
1370 switch( (ir&0x70) >> 4 ) {
1373 uint32_t Rm = ((ir>>8)&0xF);
1376 sh4_write_sr( sh4r.r[Rm] );
1381 uint32_t Rm = ((ir>>8)&0xF);
1382 sh4r.gbr = sh4r.r[Rm];
1387 uint32_t Rm = ((ir>>8)&0xF);
1389 sh4r.vbr = sh4r.r[Rm];
1394 uint32_t Rm = ((ir>>8)&0xF);
1396 sh4r.ssr = sh4r.r[Rm];
1401 uint32_t Rm = ((ir>>8)&0xF);
1403 sh4r.spc = sh4r.r[Rm];
1412 { /* LDC Rm, Rn_BANK */
1413 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1415 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
1421 { /* MAC.W @Rm+, @Rn+ */
1422 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1425 CHECKRALIGN16(sh4r.r[Rn]);
1426 MEM_READ_WORD( sh4r.r[Rn], tmp );
1427 stmp = SIGNEXT16(tmp);
1428 MEM_READ_WORD( sh4r.r[Rn]+2, tmp );
1429 stmp *= SIGNEXT16(tmp);
1432 CHECKRALIGN16( sh4r.r[Rn] );
1433 CHECKRALIGN16( sh4r.r[Rm] );
1434 MEM_READ_WORD(sh4r.r[Rn], tmp);
1435 stmp = SIGNEXT16(tmp);
1436 MEM_READ_WORD(sh4r.r[Rm], tmp);
1437 stmp = stmp * SIGNEXT16(tmp);
1442 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
1443 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
1444 sh4r.mac = 0x000000017FFFFFFFLL;
1445 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
1446 sh4r.mac = 0x0000000180000000LL;
1448 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
1449 ((uint32_t)(sh4r.mac + stmp));
1452 sh4r.mac += SIGNEXT32(stmp);
1459 { /* MOV.L @(disp, Rm), Rn */
1460 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1461 tmp = sh4r.r[Rm] + disp;
1462 CHECKRALIGN32( tmp );
1463 MEM_READ_LONG( tmp, sh4r.r[Rn] );
1469 { /* MOV.B @Rm, Rn */
1470 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1471 MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );
1475 { /* MOV.W @Rm, Rn */
1476 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1477 CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );
1481 { /* MOV.L @Rm, Rn */
1482 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1483 CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );
1488 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1489 sh4r.r[Rn] = sh4r.r[Rm];
1493 { /* MOV.B @Rm+, Rn */
1494 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1495 MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;
1499 { /* MOV.W @Rm+, Rn */
1500 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1501 CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;
1505 { /* MOV.L @Rm+, Rn */
1506 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1507 CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;
1512 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1513 sh4r.r[Rn] = ~sh4r.r[Rm];
1517 { /* SWAP.B Rm, Rn */
1518 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1519 sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
1523 { /* SWAP.W Rm, Rn */
1524 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1525 sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
1530 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1531 tmp = 0 - sh4r.r[Rm];
1532 sh4r.r[Rn] = tmp - sh4r.t;
1533 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
1538 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1539 sh4r.r[Rn] = 0 - sh4r.r[Rm];
1543 { /* EXTU.B Rm, Rn */
1544 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1545 sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
1549 { /* EXTU.W Rm, Rn */
1550 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1551 sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
1555 { /* EXTS.B Rm, Rn */
1556 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1557 sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
1561 { /* EXTS.W Rm, Rn */
1562 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1563 sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
1569 { /* ADD #imm, Rn */
1570 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1575 switch( (ir&0xF00) >> 8 ) {
1577 { /* MOV.B R0, @(disp, Rn) */
1578 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1579 MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
1583 { /* MOV.W R0, @(disp, Rn) */
1584 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1585 tmp = sh4r.r[Rn] + disp;
1586 CHECKWALIGN16( tmp );
1587 MEM_WRITE_WORD( tmp, R0 );
1591 { /* MOV.B @(disp, Rm), R0 */
1592 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1593 MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );
1597 { /* MOV.W @(disp, Rm), R0 */
1598 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1599 tmp = sh4r.r[Rm] + disp;
1600 CHECKRALIGN16( tmp );
1601 MEM_READ_WORD( tmp, R0 );
1605 { /* CMP/EQ #imm, R0 */
1606 int32_t imm = SIGNEXT8(ir&0xFF);
1607 sh4r.t = ( R0 == imm ? 1 : 0 );
1612 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1615 CHECKDEST( sh4r.pc + disp + 4 )
1616 sh4r.pc += disp + 4;
1617 sh4r.new_pc = sh4r.pc + 2;
1624 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1627 CHECKDEST( sh4r.pc + disp + 4 )
1628 sh4r.pc += disp + 4;
1629 sh4r.new_pc = sh4r.pc + 2;
1636 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1639 CHECKDEST( sh4r.pc + disp + 4 )
1640 sh4r.in_delay_slot = 1;
1641 sh4r.pc = sh4r.new_pc;
1642 sh4r.new_pc = pc + disp + 4;
1643 sh4r.in_delay_slot = 1;
1650 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1653 CHECKDEST( sh4r.pc + disp + 4 )
1654 sh4r.in_delay_slot = 1;
1655 sh4r.pc = sh4r.new_pc;
1656 sh4r.new_pc = pc + disp + 4;
1667 { /* MOV.W @(disp, PC), Rn */
1668 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1670 tmp = pc + 4 + disp;
1671 MEM_READ_WORD( tmp, sh4r.r[Rn] );
1676 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1678 CHECKDEST( sh4r.pc + disp + 4 );
1679 sh4r.in_delay_slot = 1;
1680 sh4r.pc = sh4r.new_pc;
1681 sh4r.new_pc = pc + 4 + disp;
1687 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1688 CHECKDEST( sh4r.pc + disp + 4 );
1690 sh4r.in_delay_slot = 1;
1692 sh4r.pc = sh4r.new_pc;
1693 sh4r.new_pc = pc + 4 + disp;
1694 TRACE_CALL( pc, sh4r.new_pc );
1699 switch( (ir&0xF00) >> 8 ) {
1701 { /* MOV.B R0, @(disp, GBR) */
1702 uint32_t disp = (ir&0xFF);
1703 MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
1707 { /* MOV.W R0, @(disp, GBR) */
1708 uint32_t disp = (ir&0xFF)<<1;
1709 tmp = sh4r.gbr + disp;
1710 CHECKWALIGN16( tmp );
1711 MEM_WRITE_WORD( tmp, R0 );
1715 { /* MOV.L R0, @(disp, GBR) */
1716 uint32_t disp = (ir&0xFF)<<2;
1717 tmp = sh4r.gbr + disp;
1718 CHECKWALIGN32( tmp );
1719 MEM_WRITE_LONG( tmp, R0 );
1724 uint32_t imm = (ir&0xFF);
1727 sh4_raise_trap( imm );
1732 { /* MOV.B @(disp, GBR), R0 */
1733 uint32_t disp = (ir&0xFF);
1734 MEM_READ_BYTE( sh4r.gbr + disp, R0 );
1738 { /* MOV.W @(disp, GBR), R0 */
1739 uint32_t disp = (ir&0xFF)<<1;
1740 tmp = sh4r.gbr + disp;
1741 CHECKRALIGN16( tmp );
1742 MEM_READ_WORD( tmp, R0 );
1746 { /* MOV.L @(disp, GBR), R0 */
1747 uint32_t disp = (ir&0xFF)<<2;
1748 tmp = sh4r.gbr + disp;
1749 CHECKRALIGN32( tmp );
1750 MEM_READ_LONG( tmp, R0 );
1754 { /* MOVA @(disp, PC), R0 */
1755 uint32_t disp = (ir&0xFF)<<2;
1757 R0 = (pc&0xFFFFFFFC) + disp + 4;
1761 { /* TST #imm, R0 */
1762 uint32_t imm = (ir&0xFF);
1763 sh4r.t = (R0 & imm ? 0 : 1);
1767 { /* AND #imm, R0 */
1768 uint32_t imm = (ir&0xFF);
1773 { /* XOR #imm, R0 */
1774 uint32_t imm = (ir&0xFF);
1780 uint32_t imm = (ir&0xFF);
1785 { /* TST.B #imm, @(R0, GBR) */
1786 uint32_t imm = (ir&0xFF);
1787 MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );
1791 { /* AND.B #imm, @(R0, GBR) */
1792 uint32_t imm = (ir&0xFF);
1793 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );
1797 { /* XOR.B #imm, @(R0, GBR) */
1798 uint32_t imm = (ir&0xFF);
1799 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );
1803 { /* OR.B #imm, @(R0, GBR) */
1804 uint32_t imm = (ir&0xFF);
1805 MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );
1811 { /* MOV.L @(disp, PC), Rn */
1812 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1814 tmp = (pc&0xFFFFFFFC) + disp + 4;
1815 MEM_READ_LONG( tmp, sh4r.r[Rn] );
1819 { /* MOV #imm, Rn */
1820 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1827 { /* FADD FRm, FRn */
1828 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1830 if( IS_FPU_DOUBLEPREC() ) {
1838 { /* FSUB FRm, FRn */
1839 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1841 if( IS_FPU_DOUBLEPREC() ) {
1849 { /* FMUL FRm, FRn */
1850 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1852 if( IS_FPU_DOUBLEPREC() ) {
1860 { /* FDIV FRm, FRn */
1861 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1863 if( IS_FPU_DOUBLEPREC() ) {
1871 { /* FCMP/EQ FRm, FRn */
1872 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1874 if( IS_FPU_DOUBLEPREC() ) {
1875 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
1877 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
1882 { /* FCMP/GT FRm, FRn */
1883 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1885 if( IS_FPU_DOUBLEPREC() ) {
1886 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
1888 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
1893 { /* FMOV @(R0, Rm), FRn */
1894 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1895 MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
1899 { /* FMOV FRm, @(R0, Rn) */
1900 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1901 MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
1905 { /* FMOV @Rm, FRn */
1906 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1907 MEM_FP_READ( sh4r.r[Rm], FRn );
1911 { /* FMOV @Rm+, FRn */
1912 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1913 MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
1917 { /* FMOV FRm, @Rn */
1918 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1919 MEM_FP_WRITE( sh4r.r[Rn], FRm );
1923 { /* FMOV FRm, @-Rn */
1924 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1925 MEM_FP_WRITE( sh4r.r[Rn] - FP_WIDTH, FRm ); sh4r.r[Rn] -= FP_WIDTH;
1929 { /* FMOV FRm, FRn */
1930 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1931 if( IS_FPU_DOUBLESIZE() )
1938 switch( (ir&0xF0) >> 4 ) {
1940 { /* FSTS FPUL, FRn */
1941 uint32_t FRn = ((ir>>8)&0xF);
1942 CHECKFPUEN(); FR(FRn) = FPULf;
1946 { /* FLDS FRm, FPUL */
1947 uint32_t FRm = ((ir>>8)&0xF);
1948 CHECKFPUEN(); FPULf = FR(FRm);
1952 { /* FLOAT FPUL, FRn */
1953 uint32_t FRn = ((ir>>8)&0xF);
1955 if( IS_FPU_DOUBLEPREC() ) {
1956 if( FRn&1 ) { // No, really...
1957 dtmp = (double)FPULi;
1958 FR(FRn) = *(((float *)&dtmp)+1);
1960 DRF(FRn>>1) = (double)FPULi;
1963 FR(FRn) = (float)FPULi;
1968 { /* FTRC FRm, FPUL */
1969 uint32_t FRm = ((ir>>8)&0xF);
1971 if( IS_FPU_DOUBLEPREC() ) {
1974 *(((float *)&dtmp)+1) = FR(FRm);
1978 if( dtmp >= MAX_INTF )
1980 else if( dtmp <= MIN_INTF )
1983 FPULi = (int32_t)dtmp;
1986 if( ftmp >= MAX_INTF )
1988 else if( ftmp <= MIN_INTF )
1991 FPULi = (int32_t)ftmp;
1997 uint32_t FRn = ((ir>>8)&0xF);
1999 if( IS_FPU_DOUBLEPREC() ) {
2008 uint32_t FRn = ((ir>>8)&0xF);
2010 if( IS_FPU_DOUBLEPREC() ) {
2011 DR(FRn) = fabs(DR(FRn));
2013 FR(FRn) = fabsf(FR(FRn));
2019 uint32_t FRn = ((ir>>8)&0xF);
2021 if( IS_FPU_DOUBLEPREC() ) {
2022 DR(FRn) = sqrt(DR(FRn));
2024 FR(FRn) = sqrtf(FR(FRn));
2030 uint32_t FRn = ((ir>>8)&0xF);
2032 if( !IS_FPU_DOUBLEPREC() ) {
2033 FR(FRn) = 1.0/sqrtf(FR(FRn));
2039 uint32_t FRn = ((ir>>8)&0xF);
2041 if( IS_FPU_DOUBLEPREC() ) {
2050 uint32_t FRn = ((ir>>8)&0xF);
2052 if( IS_FPU_DOUBLEPREC() ) {
2060 { /* FCNVSD FPUL, FRn */
2061 uint32_t FRn = ((ir>>8)&0xF);
2063 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2064 DR(FRn) = (double)FPULf;
2069 { /* FCNVDS FRm, FPUL */
2070 uint32_t FRm = ((ir>>8)&0xF);
2072 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
2073 FPULf = (float)DR(FRm);
2078 { /* FIPR FVm, FVn */
2079 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
2081 if( !IS_FPU_DOUBLEPREC() ) {
2084 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
2085 FR(tmp+1)*FR(tmp2+1) +
2086 FR(tmp+2)*FR(tmp2+2) +
2087 FR(tmp+3)*FR(tmp2+3);
2092 switch( (ir&0x100) >> 8 ) {
2094 { /* FSCA FPUL, FRn */
2095 uint32_t FRn = ((ir>>9)&0x7)<<1;
2097 if( !IS_FPU_DOUBLEPREC() ) {
2098 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
2100 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
2101 FR(FRn) = sinf(angle);
2102 FR((FRn)+1) = cosf(angle);
2108 switch( (ir&0x200) >> 9 ) {
2110 { /* FTRV XMTRX, FVn */
2111 uint32_t FVn = ((ir>>10)&0x3);
2113 if( !IS_FPU_DOUBLEPREC() ) {
2114 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
2117 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
2118 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
2119 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
2120 xf[9]*fv[2] + xf[13]*fv[3];
2121 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
2122 xf[8]*fv[2] + xf[12]*fv[3];
2123 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
2124 xf[11]*fv[2] + xf[15]*fv[3];
2125 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
2126 xf[10]*fv[2] + xf[14]*fv[3];
2132 switch( (ir&0xC00) >> 10 ) {
2135 CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
2141 sh4r.fpscr ^= FPSCR_FR;
2142 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
2165 { /* FMAC FR0, FRm, FRn */
2166 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
2168 if( IS_FPU_DOUBLEPREC() ) {
2169 DR(FRn) += DR(FRm)*DR(0);
2171 FR(FRn) += FR(FRm)*FR(0);
2182 sh4r.pc = sh4r.new_pc;
2184 sh4r.in_delay_slot = 0;
.