1.1 --- a/src/sh4/mmu.c	Tue Aug 19 08:38:10 2008 +0000
     1.2 +++ b/src/sh4/mmu.c	Tue Aug 19 13:00:46 2008 +0000
     1.3 @@ -138,6 +138,8 @@
     1.4  {
     1.5      uint32_t tmp;
     1.6      switch(reg) {
     1.7 +    case SH4VER:
     1.8 +        return;
     1.9      case PTEH:
    1.10          val &= 0xFFFFFCFF;
    1.11          if( (val & 0xFF) != mmu_asid ) {

     2.1 --- a/src/sh4/sh4mmio.h	Tue Aug 19 08:38:10 2008 +0000
     2.2 +++ b/src/sh4/sh4mmio.h	Tue Aug 19 13:00:46 2008 +0000
     2.3 @@ -46,6 +46,7 @@
     2.4      LONG_PORT( 0x020, TRA,  PORT_MRW, UNDEFINED, "TRAPA exception register" )
     2.5      LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
     2.6      LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
     2.7 +    LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */
     2.8      LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
     2.9      LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
    2.10      LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )

     3.1 --- a/test/testregs.c	Tue Aug 19 08:38:10 2008 +0000
     3.2 +++ b/test/testregs.c	Tue Aug 19 13:00:46 2008 +0000
     3.3 @@ -193,6 +193,8 @@
     3.4      { 0xA05F81F8, 0xFFFFFFFF, 0 },
     3.5      { 0xA05F81FC, 0xFFFFFFFF, 0 },
     3.6      { 0xFF00001C, 0xFFFFFFFF, 0x000081A7 },
     3.7 +    { 0xFF000030, 0xFFFFFFFF, 0x040205C1 },
     3.8 +    { 0xFF000030, 0, 0x040205C1 },
     3.9      { 0, 0, 0 } };
    3.10      
    3.11  int main( int argc, char *argv[] )