nkeynes@31 | 1 | /**
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nkeynes@56 | 2 | * $Id: asic.c,v 1.10 2006-01-01 08:09:42 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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nkeynes@31 | 5 | * and DMA).
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nkeynes@31 | 6 | *
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nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 8 | *
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nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 12 | * (at your option) any later version.
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nkeynes@31 | 13 | *
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nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 17 | * GNU General Public License for more details.
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nkeynes@31 | 18 | */
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nkeynes@35 | 19 |
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nkeynes@35 | 20 | #define MODULE asic_module
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nkeynes@35 | 21 |
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nkeynes@1 | 22 | #include <assert.h>
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nkeynes@1 | 23 | #include "dream.h"
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nkeynes@1 | 24 | #include "mem.h"
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nkeynes@1 | 25 | #include "sh4/intc.h"
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nkeynes@56 | 26 | #include "sh4/dmac.h"
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nkeynes@2 | 27 | #include "dreamcast.h"
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nkeynes@25 | 28 | #include "maple/maple.h"
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nkeynes@25 | 29 | #include "gdrom/ide.h"
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nkeynes@15 | 30 | #include "asic.h"
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nkeynes@1 | 31 | #define MMIO_IMPL
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nkeynes@1 | 32 | #include "asic.h"
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nkeynes@1 | 33 | /*
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nkeynes@1 | 34 | * Open questions:
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nkeynes@1 | 35 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 36 | * interrupt being delivered immediately?
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nkeynes@1 | 37 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 38 | *
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nkeynes@1 | 39 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 40 | * practically nothing is publicly known...
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nkeynes@1 | 41 | */
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nkeynes@1 | 42 |
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nkeynes@15 | 43 | struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
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nkeynes@23 | 44 | NULL, NULL, NULL };
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nkeynes@15 | 45 |
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nkeynes@20 | 46 | void asic_check_cleared_events( void );
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nkeynes@20 | 47 |
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nkeynes@1 | 48 | void asic_init( void )
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nkeynes@1 | 49 | {
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nkeynes@1 | 50 | register_io_region( &mmio_region_ASIC );
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nkeynes@1 | 51 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@1 | 52 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
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nkeynes@1 | 53 | asic_event( EVENT_GDROM_CMD );
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nkeynes@1 | 54 | }
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nkeynes@1 | 55 |
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nkeynes@1 | 56 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 57 | {
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nkeynes@1 | 58 | switch( reg ) {
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nkeynes@56 | 59 | case PIRQ0:
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nkeynes@56 | 60 | case PIRQ1:
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nkeynes@56 | 61 | case PIRQ2:
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nkeynes@56 | 62 | /* Clear any interrupts */
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nkeynes@56 | 63 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@56 | 64 | asic_check_cleared_events();
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nkeynes@56 | 65 | break;
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nkeynes@56 | 66 | case MAPLE_STATE:
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nkeynes@56 | 67 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@56 | 68 | if( val & 1 ) {
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nkeynes@56 | 69 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@56 | 70 | WARN( "Maple request initiated at %08X, halting", maple_addr );
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nkeynes@56 | 71 | maple_handle_buffer( maple_addr );
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nkeynes@56 | 72 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@56 | 73 | }
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nkeynes@56 | 74 | break;
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nkeynes@56 | 75 | case PVRDMACTL: /* Initiate PVR DMA transfer */
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nkeynes@56 | 76 | if( val & 1 ) {
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nkeynes@56 | 77 | uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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nkeynes@56 | 78 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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nkeynes@56 | 79 | char *data = alloca( count );
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nkeynes@56 | 80 | uint32_t rcount = DMAC_get_buffer( 2, data, count );
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nkeynes@56 | 81 | if( rcount != count )
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nkeynes@56 | 82 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
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nkeynes@56 | 83 | if( (dest_addr &0xF0000000) == 0x10000000 ) { /* TA */
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nkeynes@56 | 84 | pvr2ta_write( data, rcount );
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nkeynes@56 | 85 | }
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nkeynes@56 | 86 | asic_event( EVENT_PVR_DMA );
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nkeynes@56 | 87 | }
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nkeynes@56 | 88 | break;
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nkeynes@56 | 89 | default:
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nkeynes@56 | 90 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@56 | 91 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
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nkeynes@56 | 92 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 93 | }
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nkeynes@1 | 94 | }
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nkeynes@1 | 95 |
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nkeynes@1 | 96 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 97 | {
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nkeynes@1 | 98 | int32_t val;
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nkeynes@1 | 99 | switch( reg ) {
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nkeynes@2 | 100 | /*
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nkeynes@2 | 101 | case 0x89C:
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nkeynes@2 | 102 | sh4_stop();
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nkeynes@2 | 103 | return 0x000000B;
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nkeynes@2 | 104 | */
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nkeynes@1 | 105 | case PIRQ0:
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nkeynes@1 | 106 | case PIRQ1:
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nkeynes@1 | 107 | case PIRQ2:
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nkeynes@1 | 108 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 109 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 110 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 111 | return val;
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nkeynes@1 | 112 | case G2STATUS:
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nkeynes@1 | 113 | return 0; /* find out later if there's any cases we actually need to care about */
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nkeynes@1 | 114 | default:
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nkeynes@1 | 115 | val = MMIO_READ(ASIC, reg);
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nkeynes@1 | 116 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
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nkeynes@1 | 117 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
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nkeynes@1 | 118 | return val;
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nkeynes@1 | 119 | }
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nkeynes@1 | 120 |
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nkeynes@1 | 121 | }
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nkeynes@1 | 122 |
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nkeynes@1 | 123 | void asic_event( int event )
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nkeynes@1 | 124 | {
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nkeynes@1 | 125 | int offset = ((event&0x60)>>3);
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nkeynes@1 | 126 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@1 | 127 |
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nkeynes@1 | 128 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@1 | 129 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@1 | 130 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@1 | 131 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@1 | 132 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@1 | 133 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@1 | 134 | }
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nkeynes@1 | 135 |
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nkeynes@20 | 136 | void asic_check_cleared_events( )
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nkeynes@20 | 137 | {
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nkeynes@20 | 138 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@20 | 139 | uint32_t bits;
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nkeynes@20 | 140 | for( i=0; i<3; i++ ) {
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nkeynes@20 | 141 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@20 | 142 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@20 | 143 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@20 | 144 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@20 | 145 | }
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nkeynes@20 | 146 | if( setA == 0 )
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nkeynes@20 | 147 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@20 | 148 | if( setB == 0 )
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nkeynes@20 | 149 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@20 | 150 | if( setC == 0 )
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nkeynes@20 | 151 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@20 | 152 | }
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nkeynes@1 | 153 |
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nkeynes@1 | 154 |
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nkeynes@1 | 155 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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nkeynes@1 | 156 | {
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nkeynes@2 | 157 | switch( reg ) {
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nkeynes@2 | 158 | case IDEALTSTATUS: /* Device control */
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nkeynes@2 | 159 | ide_write_control( val );
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nkeynes@2 | 160 | break;
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nkeynes@2 | 161 | case IDEDATA:
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nkeynes@2 | 162 | ide_write_data_pio( val );
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nkeynes@2 | 163 | break;
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nkeynes@2 | 164 | case IDEFEAT:
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nkeynes@2 | 165 | if( ide_can_write_regs() )
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nkeynes@2 | 166 | idereg.feature = (uint8_t)val;
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nkeynes@2 | 167 | break;
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nkeynes@2 | 168 | case IDECOUNT:
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nkeynes@2 | 169 | if( ide_can_write_regs() )
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nkeynes@2 | 170 | idereg.count = (uint8_t)val;
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nkeynes@2 | 171 | break;
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nkeynes@2 | 172 | case IDELBA0:
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nkeynes@2 | 173 | if( ide_can_write_regs() )
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nkeynes@2 | 174 | idereg.lba0 = (uint8_t)val;
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nkeynes@2 | 175 | break;
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nkeynes@2 | 176 | case IDELBA1:
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nkeynes@2 | 177 | if( ide_can_write_regs() )
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nkeynes@2 | 178 | idereg.lba1 = (uint8_t)val;
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nkeynes@2 | 179 | break;
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nkeynes@2 | 180 | case IDELBA2:
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nkeynes@2 | 181 | if( ide_can_write_regs() )
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nkeynes@2 | 182 | idereg.lba2 = (uint8_t)val;
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nkeynes@2 | 183 | break;
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nkeynes@2 | 184 | case IDEDEV:
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nkeynes@2 | 185 | if( ide_can_write_regs() )
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nkeynes@2 | 186 | idereg.device = (uint8_t)val;
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nkeynes@2 | 187 | break;
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nkeynes@2 | 188 | case IDECMD:
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nkeynes@2 | 189 | if( ide_can_write_regs() ) {
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nkeynes@2 | 190 | ide_clear_interrupt();
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nkeynes@2 | 191 | ide_write_command( (uint8_t)val );
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nkeynes@2 | 192 | }
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nkeynes@2 | 193 | break;
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nkeynes@2 | 194 | default:
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nkeynes@56 | 195 | WARN( "EXTDMA write %08X <= %08X", reg, val );
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nkeynes@56 | 196 |
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nkeynes@2 | 197 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@2 | 198 | }
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nkeynes@1 | 199 | }
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nkeynes@1 | 200 |
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nkeynes@1 | 201 | MMIO_REGION_READ_FN( EXTDMA, reg )
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nkeynes@1 | 202 | {
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nkeynes@56 | 203 | uint32_t val;
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nkeynes@1 | 204 | switch( reg ) {
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nkeynes@2 | 205 | case IDEALTSTATUS: return idereg.status;
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nkeynes@2 | 206 | case IDEDATA: return ide_read_data_pio( );
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nkeynes@2 | 207 | case IDEFEAT: return idereg.error;
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nkeynes@2 | 208 | case IDECOUNT:return idereg.count;
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nkeynes@2 | 209 | case IDELBA0: return idereg.disc;
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nkeynes@2 | 210 | case IDELBA1: return idereg.lba1;
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nkeynes@2 | 211 | case IDELBA2: return idereg.lba2;
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nkeynes@2 | 212 | case IDEDEV: return idereg.device;
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nkeynes@2 | 213 | case IDECMD:
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nkeynes@2 | 214 | ide_clear_interrupt();
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nkeynes@2 | 215 | return idereg.status;
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nkeynes@1 | 216 | default:
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nkeynes@56 | 217 | val = MMIO_READ( EXTDMA, reg );
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nkeynes@56 | 218 | DEBUG( "EXTDMA read %08X => %08X", reg, val );
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nkeynes@56 | 219 | return val;
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nkeynes@1 | 220 | }
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nkeynes@1 | 221 | }
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nkeynes@1 | 222 |
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