nkeynes@10 | 1 | /**
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nkeynes@586 | 2 | * $Id$
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nkeynes@10 | 3 | *
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nkeynes@945 | 4 | * This file defines the internal functions used by the SH4 core,
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nkeynes@10 | 5 | *
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nkeynes@945 | 6 | * Copyright (c) 2005-2008 Nathan Keynes.
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nkeynes@10 | 7 | *
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nkeynes@10 | 8 | * This program is free software; you can redistribute it and/or modify
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nkeynes@10 | 9 | * it under the terms of the GNU General Public License as published by
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nkeynes@10 | 10 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@10 | 11 | * (at your option) any later version.
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nkeynes@10 | 12 | *
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nkeynes@10 | 13 | * This program is distributed in the hope that it will be useful,
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nkeynes@10 | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@10 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@10 | 16 | * GNU General Public License for more details.
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nkeynes@1 | 17 | */
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nkeynes@30 | 18 |
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nkeynes@736 | 19 | #ifndef lxdream_sh4core_H
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nkeynes@736 | 20 | #define lxdream_sh4core_H 1
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nkeynes@1 | 21 |
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nkeynes@27 | 22 | #include <glib/gtypes.h>
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nkeynes@1 | 23 | #include <stdint.h>
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nkeynes@23 | 24 | #include <stdio.h>
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nkeynes@378 | 25 | #include "mem.h"
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nkeynes@586 | 26 | #include "sh4/sh4.h"
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nkeynes@1 | 27 |
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nkeynes@1 | 28 | #ifdef __cplusplus
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nkeynes@1 | 29 | extern "C" {
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nkeynes@1 | 30 | #endif
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nkeynes@1 | 31 |
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nkeynes@586 | 32 | /* Breakpoint data structure */
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nkeynes@586 | 33 | extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
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nkeynes@586 | 34 | extern int sh4_breakpoint_count;
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nkeynes@591 | 35 | extern gboolean sh4_starting;
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nkeynes@1218 | 36 | extern gboolean sh4_profile_blocks;
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nkeynes@27 | 37 |
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nkeynes@27 | 38 | /**
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nkeynes@586 | 39 | * Cached direct pointer to the current instruction page. If AT is on, this
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nkeynes@586 | 40 | * is derived from the ITLB, otherwise this will be the entire memory region.
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nkeynes@586 | 41 | * This is actually a fairly useful optimization, as we can make a lot of
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nkeynes@586 | 42 | * assumptions about the "current page" that we can't make in general for
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nkeynes@586 | 43 | * arbitrary virtual addresses.
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nkeynes@27 | 44 | */
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nkeynes@586 | 45 | struct sh4_icache_struct {
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nkeynes@586 | 46 | sh4ptr_t page; // Page pointer (NULL if no page)
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nkeynes@586 | 47 | sh4vma_t page_vma; // virtual address of the page.
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nkeynes@586 | 48 | sh4addr_t page_ppa; // physical address of the page
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nkeynes@586 | 49 | uint32_t mask; // page mask
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nkeynes@586 | 50 | };
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nkeynes@586 | 51 | extern struct sh4_icache_struct sh4_icache;
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nkeynes@586 | 52 |
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nkeynes@27 | 53 | /**
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nkeynes@586 | 54 | * Test if a given address is contained in the current icache entry
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nkeynes@27 | 55 | */
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nkeynes@586 | 56 | #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
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nkeynes@27 | 57 | /**
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nkeynes@586 | 58 | * Return a pointer for the given vma, under the assumption that it is
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nkeynes@586 | 59 | * actually contained in the current icache entry.
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nkeynes@27 | 60 | */
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nkeynes@586 | 61 | #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
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nkeynes@27 | 62 | /**
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nkeynes@586 | 63 | * Return the physical (external) address for the given vma, assuming that it is
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nkeynes@586 | 64 | * actually contained in the current icache entry.
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nkeynes@27 | 65 | */
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nkeynes@586 | 66 | #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
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nkeynes@27 | 67 |
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nkeynes@589 | 68 | /**
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nkeynes@589 | 69 | * Return the virtual (vma) address for the first address past the end of the
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nkeynes@589 | 70 | * cache entry. Assumes that there is in fact a current icache entry.
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nkeynes@589 | 71 | */
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nkeynes@589 | 72 | #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1)
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nkeynes@589 | 73 |
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nkeynes@740 | 74 |
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nkeynes@740 | 75 | /**
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nkeynes@948 | 76 | * SH4 vm-exit flag - exit the current block but continue normally
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nkeynes@740 | 77 | */
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nkeynes@740 | 78 | #define CORE_EXIT_CONTINUE 1
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nkeynes@740 | 79 |
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nkeynes@740 | 80 | /**
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nkeynes@740 | 81 | * SH4 vm-exit flag - exit the current block and halt immediately (eg fatal error)
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nkeynes@740 | 82 | */
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nkeynes@740 | 83 | #define CORE_EXIT_HALT 2
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nkeynes@740 | 84 |
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nkeynes@740 | 85 | /**
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nkeynes@740 | 86 | * SH4 vm-exit flag - exit the current block and halt immediately for a system
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nkeynes@740 | 87 | * breakpoint.
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nkeynes@740 | 88 | */
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nkeynes@740 | 89 | #define CORE_EXIT_BREAKPOINT 3
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nkeynes@740 | 90 |
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nkeynes@740 | 91 | /**
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nkeynes@740 | 92 | * SH4 vm-exit flag - exit the current block and continue after performing a full
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nkeynes@740 | 93 | * system reset (dreamcast_reset())
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nkeynes@740 | 94 | */
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nkeynes@740 | 95 | #define CORE_EXIT_SYSRESET 4
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nkeynes@740 | 96 |
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nkeynes@740 | 97 | /**
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nkeynes@740 | 98 | * SH4 vm-exit flag - exit the current block and continue after the next IRQ.
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nkeynes@740 | 99 | */
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nkeynes@740 | 100 | #define CORE_EXIT_SLEEP 5
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nkeynes@740 | 101 |
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nkeynes@740 | 102 | /**
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nkeynes@939 | 103 | * SH4 vm-exit flag - exit the current block and flush all instruction caches (ie
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nkeynes@740 | 104 | * if address translation has changed)
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nkeynes@740 | 105 | */
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nkeynes@740 | 106 | #define CORE_EXIT_FLUSH_ICACHE 6
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nkeynes@740 | 107 |
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nkeynes@939 | 108 | /**
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nkeynes@939 | 109 | * SH4 vm-exit flag - exit the current block following a taken exception. sh4r.spc
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nkeynes@939 | 110 | * is fixed up by recovery rather than sh4r.pc.
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nkeynes@939 | 111 | */
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nkeynes@939 | 112 | #define CORE_EXIT_EXCEPTION 7
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nkeynes@939 | 113 |
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nkeynes@740 | 114 | typedef uint32_t (*sh4_run_slice_fn)(uint32_t);
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nkeynes@740 | 115 |
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nkeynes@586 | 116 | /* SH4 module functions */
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nkeynes@1 | 117 | void sh4_init( void );
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nkeynes@1 | 118 | void sh4_reset( void );
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nkeynes@1 | 119 | void sh4_run( void );
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nkeynes@1 | 120 | void sh4_stop( void );
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nkeynes@617 | 121 | uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator
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nkeynes@617 | 122 | uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator
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nkeynes@617 | 123 | uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep
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nkeynes@586 | 124 |
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nkeynes@740 | 125 | /**
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nkeynes@740 | 126 | * Immediately exit from the currently executing instruction with the given
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nkeynes@740 | 127 | * exit code. This method does not return.
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nkeynes@740 | 128 | */
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nkeynes@740 | 129 | void sh4_core_exit( int exit_code );
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nkeynes@740 | 130 |
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nkeynes@740 | 131 | /**
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nkeynes@740 | 132 | * Exit the current block at the end of the current instruction, flush the
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nkeynes@740 | 133 | * translation cache (completely) and return control to sh4_xlat_run_slice.
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nkeynes@740 | 134 | *
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nkeynes@740 | 135 | * As a special case, if the current instruction is actually the last
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nkeynes@740 | 136 | * instruction in the block (ie it's in a delay slot), this function
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nkeynes@740 | 137 | * returns to allow normal completion of the translation block. Otherwise
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nkeynes@740 | 138 | * this function never returns.
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nkeynes@740 | 139 | *
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nkeynes@740 | 140 | * Must only be invoked (indirectly) from within translated code.
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nkeynes@740 | 141 | */
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nkeynes@740 | 142 | void sh4_flush_icache();
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nkeynes@740 | 143 |
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nkeynes@586 | 144 | /* SH4 peripheral module functions */
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nkeynes@586 | 145 | void CPG_reset( void );
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nkeynes@586 | 146 | void DMAC_reset( void );
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nkeynes@586 | 147 | void DMAC_run_slice( uint32_t );
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nkeynes@586 | 148 | void DMAC_save_state( FILE * );
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nkeynes@586 | 149 | int DMAC_load_state( FILE * );
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nkeynes@586 | 150 | void INTC_reset( void );
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nkeynes@586 | 151 | void INTC_save_state( FILE *f );
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nkeynes@586 | 152 | int INTC_load_state( FILE *f );
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nkeynes@564 | 153 | void MMU_init( void );
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nkeynes@586 | 154 | void MMU_reset( void );
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nkeynes@586 | 155 | void MMU_save_state( FILE *f );
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nkeynes@586 | 156 | int MMU_load_state( FILE *f );
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nkeynes@586 | 157 | void MMU_ldtlb();
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nkeynes@986 | 158 | void CCN_reset();
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nkeynes@968 | 159 | void CCN_set_cache_control( int reg );
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nkeynes@931 | 160 | void CCN_save_state( FILE *f );
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nkeynes@931 | 161 | int CCN_load_state( FILE *f );
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nkeynes@586 | 162 | void SCIF_reset( void );
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nkeynes@586 | 163 | void SCIF_run_slice( uint32_t );
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nkeynes@586 | 164 | void SCIF_save_state( FILE *f );
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nkeynes@586 | 165 | int SCIF_load_state( FILE *f );
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nkeynes@586 | 166 | void SCIF_update_line_speed(void);
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nkeynes@669 | 167 | void TMU_init( void );
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nkeynes@586 | 168 | void TMU_reset( void );
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nkeynes@586 | 169 | void TMU_run_slice( uint32_t );
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nkeynes@586 | 170 | void TMU_save_state( FILE * );
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nkeynes@586 | 171 | int TMU_load_state( FILE * );
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nkeynes@586 | 172 | void TMU_update_clocks( void );
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nkeynes@841 | 173 | void PMM_reset( void );
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nkeynes@841 | 174 | void PMM_write_control( int, uint32_t );
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nkeynes@841 | 175 | void PMM_save_state( FILE * );
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nkeynes@841 | 176 | int PMM_load_state( FILE * );
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nkeynes@841 | 177 | uint32_t PMM_run_slice( uint32_t );
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nkeynes@759 | 178 | uint32_t sh4_translate_run_slice(uint32_t);
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nkeynes@759 | 179 | uint32_t sh4_emulate_run_slice(uint32_t);
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nkeynes@586 | 180 |
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nkeynes@586 | 181 | /* SH4 instruction support methods */
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nkeynes@929 | 182 | mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t address );
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nkeynes@929 | 183 | void FASTCALL sh7750_decode_address_copy( sh4addr_t address, mem_region_fn_t result );
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nkeynes@905 | 184 | void FASTCALL sh4_sleep( void );
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nkeynes@905 | 185 | void FASTCALL sh4_fsca( uint32_t angle, float *fr );
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nkeynes@905 | 186 | void FASTCALL sh4_ftrv( float *fv );
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nkeynes@905 | 187 | uint32_t FASTCALL sh4_read_sr(void);
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nkeynes@905 | 188 | void FASTCALL sh4_write_sr(uint32_t val);
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nkeynes@905 | 189 | void FASTCALL sh4_write_fpscr(uint32_t val);
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nkeynes@905 | 190 | void FASTCALL sh4_switch_fr_banks(void);
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nkeynes@905 | 191 | void FASTCALL signsat48(void);
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nkeynes@597 | 192 | gboolean sh4_has_page( sh4vma_t vma );
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nkeynes@378 | 193 |
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nkeynes@586 | 194 | /* SH4 Memory */
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nkeynes@603 | 195 | #define MMU_VMA_ERROR 0x80000000
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nkeynes@586 | 196 | /**
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nkeynes@586 | 197 | * Update the sh4_icache structure to contain the specified vma. If the vma
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nkeynes@586 | 198 | * cannot be resolved, an MMU exception is raised and the function returns
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nkeynes@586 | 199 | * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly.
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nkeynes@586 | 200 | * Note: If the vma resolves to a non-memory area, sh4_icache will be
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nkeynes@586 | 201 | * invalidated, but the function will still return TRUE.
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nkeynes@586 | 202 | * @return FALSE if an MMU exception was raised, otherwise TRUE.
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nkeynes@586 | 203 | */
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nkeynes@905 | 204 | gboolean FASTCALL mmu_update_icache( sh4vma_t addr );
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nkeynes@23 | 205 |
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nkeynes@905 | 206 | int64_t FASTCALL sh4_read_quad( sh4addr_t addr );
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nkeynes@905 | 207 | int32_t FASTCALL sh4_read_long( sh4addr_t addr );
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nkeynes@905 | 208 | int32_t FASTCALL sh4_read_word( sh4addr_t addr );
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nkeynes@905 | 209 | int32_t FASTCALL sh4_read_byte( sh4addr_t addr );
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nkeynes@905 | 210 | void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val );
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nkeynes@905 | 211 | void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val );
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nkeynes@905 | 212 | void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val );
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nkeynes@905 | 213 | void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val );
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nkeynes@527 | 214 | int32_t sh4_read_phys_word( sh4addr_t addr );
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nkeynes@911 | 215 | void FASTCALL sh4_flush_store_queue( sh4addr_t addr );
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nkeynes@939 | 216 | void FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr, void *exc );
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nkeynes@10 | 217 |
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nkeynes@586 | 218 | /* SH4 Exceptions */
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nkeynes@586 | 219 | #define EXC_POWER_RESET 0x000 /* reset vector */
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nkeynes@586 | 220 | #define EXC_MANUAL_RESET 0x020 /* reset vector */
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nkeynes@586 | 221 | #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
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nkeynes@586 | 222 | #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
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nkeynes@586 | 223 | #define EXC_INIT_PAGE_WRITE 0x080
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nkeynes@586 | 224 | #define EXC_TLB_PROT_READ 0x0A0
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nkeynes@586 | 225 | #define EXC_TLB_PROT_WRITE 0x0C0
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nkeynes@586 | 226 | #define EXC_DATA_ADDR_READ 0x0E0
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nkeynes@586 | 227 | #define EXC_DATA_ADDR_WRITE 0x100
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nkeynes@586 | 228 | #define EXC_TLB_MULTI_HIT 0x140
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nkeynes@586 | 229 | #define EXC_SLOT_ILLEGAL 0x1A0
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nkeynes@586 | 230 | #define EXC_ILLEGAL 0x180
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nkeynes@586 | 231 | #define EXC_TRAP 0x160
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nkeynes@586 | 232 | #define EXC_FPU_DISABLED 0x800
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nkeynes@586 | 233 | #define EXC_SLOT_FPU_DISABLED 0x820
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nkeynes@374 | 234 |
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nkeynes@586 | 235 | #define EXV_EXCEPTION 0x100 /* General exception vector */
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nkeynes@586 | 236 | #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
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nkeynes@586 | 237 | #define EXV_INTERRUPT 0x600 /* External interrupt vector */
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nkeynes@586 | 238 |
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nkeynes@951 | 239 | void FASTCALL sh4_raise_exception( int );
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nkeynes@951 | 240 | void FASTCALL sh4_raise_reset( int );
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nkeynes@951 | 241 | void FASTCALL sh4_raise_trap( int );
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nkeynes@951 | 242 | void FASTCALL sh4_raise_tlb_exception( int, sh4vma_t );
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nkeynes@951 | 243 | void FASTCALL sh4_raise_tlb_multihit( sh4vma_t );
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nkeynes@905 | 244 | void FASTCALL sh4_accept_interrupt( void );
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nkeynes@1 | 245 |
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nkeynes@1202 | 246 | #define RAISE_TLB_ERROR(code, vpn) sh4_raise_tlb_exception(code, vpn)
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nkeynes@1202 | 247 | #define RAISE_MEM_ERROR(code, vpn) \
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nkeynes@1202 | 248 | MMIO_WRITE(MMU, TEA, vpn); \
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nkeynes@1202 | 249 | MMIO_WRITE(MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00))); \
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nkeynes@1202 | 250 | sh4_raise_exception(code);
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nkeynes@1202 | 251 | #define RAISE_TLB_MULTIHIT_ERROR(vpn) sh4_raise_tlb_multihit(vpn)
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nkeynes@1202 | 252 |
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nkeynes@1202 | 253 | #ifdef HAVE_FRAME_ADDRESS
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nkeynes@1202 | 254 | #define SH4_EXCEPTION_EXIT() do{ *(((void * volatile *)__builtin_frame_address(0))+1) = exc; } while(0)
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nkeynes@1202 | 255 | #else
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nkeynes@1202 | 256 | #define SH4_EXCEPTION_EXIT() sh4_core_exit(CORE_EXIT_EXCEPTION)
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nkeynes@1202 | 257 | #endif
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nkeynes@1202 | 258 |
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nkeynes@948 | 259 | /**
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nkeynes@1194 | 260 | * Helper method to update the SH4 registers for an exception, without
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nkeynes@1194 | 261 | * touching the MMU registers. Mainly for use in shadow mode.
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nkeynes@1194 | 262 | */
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nkeynes@1194 | 263 | void FASTCALL sh4_reraise_exception( sh4addr_t exception_pc );
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nkeynes@1194 | 264 | /**
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nkeynes@948 | 265 | * Complete the current instruction as part of a core exit. Prevents the
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nkeynes@948 | 266 | * system from being left in an inconsistent state when an exit is
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nkeynes@948 | 267 | * triggered during a memory write.
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nkeynes@948 | 268 | */
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nkeynes@948 | 269 | void sh4_finalize_instruction( void );
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nkeynes@948 | 270 |
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nkeynes@1 | 271 | /* Status Register (SR) bits */
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nkeynes@1 | 272 | #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
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nkeynes@1 | 273 | #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
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nkeynes@1 | 274 | #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
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nkeynes@1 | 275 | #define SR_FD 0x00008000 /* FPU disable */
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nkeynes@1 | 276 | #define SR_M 0x00000200
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nkeynes@1 | 277 | #define SR_Q 0x00000100
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nkeynes@1 | 278 | #define SR_IMASK 0x000000F0 /* Interrupt mask level */
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nkeynes@1 | 279 | #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
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nkeynes@1 | 280 | #define SR_T 0x00000001 /* True/false or carry/borrow */
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nkeynes@1 | 281 | #define SR_MASK 0x700083F3
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nkeynes@1 | 282 | #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
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nkeynes@586 | 283 | #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */
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nkeynes@1 | 284 |
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nkeynes@1 | 285 | #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
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nkeynes@1 | 286 | #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
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nkeynes@265 | 287 | #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
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nkeynes@1 | 288 |
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nkeynes@1 | 289 | #define FPSCR_FR 0x00200000 /* FPU register bank */
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nkeynes@1 | 290 | #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
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nkeynes@1 | 291 | #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
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nkeynes@1 | 292 | #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
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nkeynes@1 | 293 | #define FPSCR_CAUSE 0x0003F000
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nkeynes@1 | 294 | #define FPSCR_ENABLE 0x00000F80
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nkeynes@1 | 295 | #define FPSCR_FLAG 0x0000007C
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nkeynes@1 | 296 | #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
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nkeynes@823 | 297 | #define FPSCR_MASK 0x003FFFFF
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nkeynes@1 | 298 |
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nkeynes@1 | 299 | #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
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nkeynes@1 | 300 | #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
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nkeynes@1 | 301 | #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
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nkeynes@1 | 302 |
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nkeynes@669 | 303 | #define FR(x) sh4r.fr[0][(x)^1]
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nkeynes@669 | 304 | #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1])
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nkeynes@669 | 305 | #define XF(x) sh4r.fr[1][(x)^1]
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nkeynes@669 | 306 | #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1])
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nkeynes@669 | 307 | #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1])
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nkeynes@669 | 308 | #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E])
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nkeynes@669 | 309 | #define FPULf (sh4r.fpul.f)
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nkeynes@669 | 310 | #define FPULi (sh4r.fpul.i)
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nkeynes@359 | 311 |
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nkeynes@939 | 312 | /**************** SH4 internal memory regions *****************/
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nkeynes@939 | 313 | extern struct mem_region_fn p4_region_itlb_addr;
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nkeynes@939 | 314 | extern struct mem_region_fn p4_region_itlb_data;
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nkeynes@939 | 315 | extern struct mem_region_fn p4_region_utlb_addr;
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nkeynes@939 | 316 | extern struct mem_region_fn p4_region_utlb_data;
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nkeynes@939 | 317 | extern struct mem_region_fn p4_region_icache_addr;
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nkeynes@939 | 318 | extern struct mem_region_fn p4_region_icache_data;
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nkeynes@939 | 319 | extern struct mem_region_fn p4_region_ocache_addr;
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nkeynes@939 | 320 | extern struct mem_region_fn p4_region_ocache_data;
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nkeynes@946 | 321 |
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nkeynes@971 | 322 | #define OC_ENABLED 1
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nkeynes@1 | 323 |
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nkeynes@1 | 324 | #ifdef __cplusplus
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nkeynes@1 | 325 | }
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nkeynes@1 | 326 | #endif
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nkeynes@359 | 327 |
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nkeynes@736 | 328 | #endif /* !lxdream_sh4core_H */
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nkeynes@736 | 329 |
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