nkeynes@31 | 1 | /**
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nkeynes@188 | 2 | * $Id: asic.c,v 1.19 2006-08-01 21:56:48 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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nkeynes@31 | 5 | * and DMA).
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nkeynes@31 | 6 | *
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nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 8 | *
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nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 12 | * (at your option) any later version.
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nkeynes@31 | 13 | *
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nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 17 | * GNU General Public License for more details.
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nkeynes@31 | 18 | */
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nkeynes@35 | 19 |
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nkeynes@35 | 20 | #define MODULE asic_module
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nkeynes@35 | 21 |
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nkeynes@1 | 22 | #include <assert.h>
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nkeynes@137 | 23 | #include <stdlib.h>
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nkeynes@1 | 24 | #include "dream.h"
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nkeynes@1 | 25 | #include "mem.h"
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nkeynes@1 | 26 | #include "sh4/intc.h"
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nkeynes@56 | 27 | #include "sh4/dmac.h"
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nkeynes@2 | 28 | #include "dreamcast.h"
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nkeynes@25 | 29 | #include "maple/maple.h"
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nkeynes@25 | 30 | #include "gdrom/ide.h"
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nkeynes@15 | 31 | #include "asic.h"
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nkeynes@1 | 32 | #define MMIO_IMPL
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nkeynes@1 | 33 | #include "asic.h"
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nkeynes@1 | 34 | /*
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nkeynes@1 | 35 | * Open questions:
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nkeynes@1 | 36 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 37 | * interrupt being delivered immediately?
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nkeynes@1 | 38 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 39 | *
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nkeynes@1 | 40 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 41 | * practically nothing is publicly known...
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nkeynes@1 | 42 | */
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nkeynes@1 | 43 |
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nkeynes@155 | 44 | static void asic_check_cleared_events( void );
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nkeynes@155 | 45 | static void asic_init( void );
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nkeynes@155 | 46 | static void asic_reset( void );
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nkeynes@155 | 47 | static void asic_save_state( FILE *f );
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nkeynes@155 | 48 | static int asic_load_state( FILE *f );
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nkeynes@155 | 49 |
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nkeynes@155 | 50 | struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, NULL,
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nkeynes@155 | 51 | NULL, asic_save_state, asic_load_state };
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nkeynes@15 | 52 |
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nkeynes@137 | 53 | #define G2_BIT5_TICKS 8
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nkeynes@137 | 54 | #define G2_BIT4_TICKS 16
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nkeynes@137 | 55 | #define G2_BIT0_ON_TICKS 24
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nkeynes@137 | 56 | #define G2_BIT0_OFF_TICKS 24
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nkeynes@137 | 57 |
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nkeynes@137 | 58 | struct asic_g2_state {
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nkeynes@163 | 59 | unsigned int last_update_time;
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nkeynes@137 | 60 | unsigned int bit5_off_timer;
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nkeynes@137 | 61 | unsigned int bit4_on_timer;
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nkeynes@137 | 62 | unsigned int bit4_off_timer;
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nkeynes@137 | 63 | unsigned int bit0_on_timer;
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nkeynes@137 | 64 | unsigned int bit0_off_timer;
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nkeynes@155 | 65 | };
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nkeynes@155 | 66 |
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nkeynes@155 | 67 | static struct asic_g2_state g2_state;
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nkeynes@155 | 68 |
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nkeynes@155 | 69 | static void asic_init( void )
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nkeynes@155 | 70 | {
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nkeynes@155 | 71 | register_io_region( &mmio_region_ASIC );
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nkeynes@155 | 72 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@155 | 73 | asic_reset();
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nkeynes@155 | 74 | }
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nkeynes@155 | 75 |
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nkeynes@155 | 76 | static void asic_reset( void )
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nkeynes@155 | 77 | {
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nkeynes@155 | 78 | memset( &g2_state, 0, sizeof(g2_state) );
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nkeynes@155 | 79 | }
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nkeynes@155 | 80 |
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nkeynes@155 | 81 | static void asic_save_state( FILE *f )
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nkeynes@155 | 82 | {
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nkeynes@155 | 83 | fwrite( &g2_state, sizeof(g2_state), 1, f );
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nkeynes@155 | 84 | }
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nkeynes@155 | 85 |
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nkeynes@155 | 86 | static int asic_load_state( FILE *f )
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nkeynes@155 | 87 | {
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nkeynes@155 | 88 | if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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nkeynes@155 | 89 | return 1;
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nkeynes@155 | 90 | else
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nkeynes@155 | 91 | return 0;
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nkeynes@155 | 92 | }
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nkeynes@155 | 93 |
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nkeynes@137 | 94 |
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nkeynes@137 | 95 | /* FIXME: Handle rollover */
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nkeynes@137 | 96 | void asic_g2_write_word()
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nkeynes@137 | 97 | {
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nkeynes@163 | 98 | g2_state.last_update_time = sh4r.icount;
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nkeynes@137 | 99 | g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS;
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nkeynes@137 | 100 | if( g2_state.bit4_off_timer < sh4r.icount )
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nkeynes@137 | 101 | g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS;
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nkeynes@137 | 102 | g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS;
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nkeynes@137 | 103 | if( g2_state.bit0_off_timer < sh4r.icount ) {
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nkeynes@137 | 104 | g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS;
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nkeynes@137 | 105 | g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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nkeynes@137 | 106 | } else {
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nkeynes@137 | 107 | g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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nkeynes@137 | 108 | }
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nkeynes@137 | 109 | MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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nkeynes@137 | 110 | }
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nkeynes@137 | 111 |
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nkeynes@137 | 112 | static uint32_t g2_read_status()
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nkeynes@137 | 113 | {
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nkeynes@163 | 114 | if( sh4r.icount < g2_state.last_update_time ) {
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nkeynes@163 | 115 | /* Rollover */
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nkeynes@163 | 116 | if( g2_state.last_update_time < g2_state.bit5_off_timer )
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nkeynes@163 | 117 | g2_state.bit5_off_timer = 0;
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nkeynes@163 | 118 | if( g2_state.last_update_time < g2_state.bit4_off_timer )
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nkeynes@163 | 119 | g2_state.bit4_off_timer = 0;
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nkeynes@163 | 120 | if( g2_state.last_update_time < g2_state.bit4_on_timer )
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nkeynes@163 | 121 | g2_state.bit4_on_timer = 0;
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nkeynes@163 | 122 | if( g2_state.last_update_time < g2_state.bit0_off_timer )
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nkeynes@163 | 123 | g2_state.bit0_off_timer = 0;
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nkeynes@163 | 124 | if( g2_state.last_update_time < g2_state.bit0_on_timer )
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nkeynes@163 | 125 | g2_state.bit0_on_timer = 0;
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nkeynes@163 | 126 | }
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nkeynes@137 | 127 | uint32_t val = MMIO_READ( ASIC, G2STATUS );
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nkeynes@137 | 128 | if( g2_state.bit5_off_timer <= sh4r.icount )
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nkeynes@137 | 129 | val = val & (~0x20);
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nkeynes@163 | 130 | if( g2_state.bit4_off_timer <= sh4r.icount ||
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nkeynes@163 | 131 | (sh4r.icount + G2_BIT5_TICKS) < g2_state.bit4_off_timer )
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nkeynes@137 | 132 | val = val & (~0x10);
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nkeynes@137 | 133 | else if( g2_state.bit4_on_timer <= sh4r.icount )
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nkeynes@137 | 134 | val = val | 0x10;
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nkeynes@137 | 135 | if( g2_state.bit0_off_timer <= sh4r.icount )
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nkeynes@137 | 136 | val = val & (~0x01);
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nkeynes@137 | 137 | else if( g2_state.bit0_on_timer <= sh4r.icount )
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nkeynes@137 | 138 | val = val | 0x01;
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nkeynes@137 | 139 | return val | 0x0E;
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nkeynes@137 | 140 | }
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nkeynes@137 | 141 |
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nkeynes@20 | 142 |
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nkeynes@155 | 143 | void asic_event( int event )
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nkeynes@1 | 144 | {
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nkeynes@155 | 145 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 146 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@155 | 147 |
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nkeynes@155 | 148 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@155 | 149 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@155 | 150 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@155 | 151 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@155 | 152 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@155 | 153 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@1 | 154 | }
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nkeynes@1 | 155 |
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nkeynes@155 | 156 | void asic_clear_event( int event ) {
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nkeynes@155 | 157 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 158 | uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
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nkeynes@155 | 159 | MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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nkeynes@155 | 160 |
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nkeynes@155 | 161 | asic_check_cleared_events();
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nkeynes@155 | 162 | }
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nkeynes@155 | 163 |
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nkeynes@155 | 164 | void asic_check_cleared_events( )
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nkeynes@155 | 165 | {
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nkeynes@155 | 166 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@155 | 167 | uint32_t bits;
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nkeynes@155 | 168 | for( i=0; i<3; i++ ) {
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nkeynes@155 | 169 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@155 | 170 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@155 | 171 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@155 | 172 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@155 | 173 | }
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nkeynes@155 | 174 | if( setA == 0 )
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nkeynes@155 | 175 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@155 | 176 | if( setB == 0 )
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nkeynes@155 | 177 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@155 | 178 | if( setC == 0 )
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nkeynes@155 | 179 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@155 | 180 | }
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nkeynes@155 | 181 |
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nkeynes@155 | 182 |
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nkeynes@155 | 183 | void asic_ide_dma_transfer( )
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nkeynes@155 | 184 | {
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nkeynes@158 | 185 | if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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nkeynes@158 | 186 | if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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nkeynes@158 | 187 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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nkeynes@158 | 188 |
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nkeynes@158 | 189 | uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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nkeynes@158 | 190 | uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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nkeynes@158 | 191 | int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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nkeynes@158 | 192 |
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nkeynes@158 | 193 | uint32_t xfer = ide_read_data_dma( addr, length );
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nkeynes@158 | 194 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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nkeynes@158 | 195 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@158 | 196 | } else { /* 0 */
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nkeynes@158 | 197 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@155 | 198 | }
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nkeynes@155 | 199 | }
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nkeynes@155 | 200 |
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nkeynes@155 | 201 | }
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nkeynes@155 | 202 |
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nkeynes@155 | 203 |
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nkeynes@1 | 204 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 205 | {
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nkeynes@1 | 206 | switch( reg ) {
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nkeynes@125 | 207 | case PIRQ1:
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nkeynes@125 | 208 | val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
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nkeynes@125 | 209 | /* fallthrough */
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nkeynes@56 | 210 | case PIRQ0:
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nkeynes@56 | 211 | case PIRQ2:
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nkeynes@56 | 212 | /* Clear any interrupts */
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nkeynes@56 | 213 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@56 | 214 | asic_check_cleared_events();
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nkeynes@56 | 215 | break;
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nkeynes@56 | 216 | case MAPLE_STATE:
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nkeynes@56 | 217 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@56 | 218 | if( val & 1 ) {
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nkeynes@56 | 219 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@56 | 220 | maple_handle_buffer( maple_addr );
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nkeynes@56 | 221 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@56 | 222 | }
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nkeynes@56 | 223 | break;
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nkeynes@56 | 224 | case PVRDMACTL: /* Initiate PVR DMA transfer */
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nkeynes@94 | 225 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@56 | 226 | if( val & 1 ) {
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nkeynes@56 | 227 | uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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nkeynes@56 | 228 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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nkeynes@56 | 229 | char *data = alloca( count );
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nkeynes@56 | 230 | uint32_t rcount = DMAC_get_buffer( 2, data, count );
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nkeynes@56 | 231 | if( rcount != count )
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nkeynes@56 | 232 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
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nkeynes@100 | 233 | mem_copy_to_sh4( dest_addr, data, rcount );
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nkeynes@56 | 234 | asic_event( EVENT_PVR_DMA );
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nkeynes@186 | 235 | MMIO_WRITE( ASIC, PVRDMACTL, 0 );
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nkeynes@186 | 236 | MMIO_WRITE( ASIC, PVRDMACNT, 0 );
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nkeynes@56 | 237 | }
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nkeynes@56 | 238 | break;
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nkeynes@158 | 239 | case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:
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nkeynes@158 | 240 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@158 | 241 | break;
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nkeynes@56 | 242 | default:
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nkeynes@56 | 243 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 244 | }
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nkeynes@1 | 245 | }
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nkeynes@1 | 246 |
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nkeynes@1 | 247 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 248 | {
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nkeynes@1 | 249 | int32_t val;
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nkeynes@1 | 250 | switch( reg ) {
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nkeynes@2 | 251 | /*
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nkeynes@2 | 252 | case 0x89C:
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nkeynes@2 | 253 | sh4_stop();
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nkeynes@2 | 254 | return 0x000000B;
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nkeynes@2 | 255 | */
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nkeynes@94 | 256 | case PIRQ0:
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nkeynes@94 | 257 | case PIRQ1:
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nkeynes@94 | 258 | case PIRQ2:
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nkeynes@94 | 259 | case IRQA0:
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nkeynes@94 | 260 | case IRQA1:
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nkeynes@94 | 261 | case IRQA2:
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nkeynes@94 | 262 | case IRQB0:
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nkeynes@94 | 263 | case IRQB1:
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nkeynes@94 | 264 | case IRQB2:
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nkeynes@94 | 265 | case IRQC0:
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nkeynes@94 | 266 | case IRQC1:
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nkeynes@94 | 267 | case IRQC2:
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nkeynes@158 | 268 | case MAPLE_STATE:
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nkeynes@94 | 269 | val = MMIO_READ(ASIC, reg);
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nkeynes@94 | 270 | return val;
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nkeynes@94 | 271 | case G2STATUS:
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nkeynes@137 | 272 | return g2_read_status();
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nkeynes@94 | 273 | default:
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nkeynes@94 | 274 | val = MMIO_READ(ASIC, reg);
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nkeynes@94 | 275 | return val;
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nkeynes@1 | 276 | }
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nkeynes@94 | 277 |
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nkeynes@1 | 278 | }
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nkeynes@1 | 279 |
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nkeynes@1 | 280 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
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nkeynes@1 | 281 | {
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nkeynes@2 | 282 | switch( reg ) {
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nkeynes@125 | 283 | case IDEALTSTATUS: /* Device control */
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nkeynes@125 | 284 | ide_write_control( val );
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nkeynes@125 | 285 | break;
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nkeynes@125 | 286 | case IDEDATA:
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nkeynes@125 | 287 | ide_write_data_pio( val );
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nkeynes@125 | 288 | break;
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nkeynes@125 | 289 | case IDEFEAT:
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nkeynes@125 | 290 | if( ide_can_write_regs() )
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nkeynes@125 | 291 | idereg.feature = (uint8_t)val;
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nkeynes@125 | 292 | break;
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nkeynes@125 | 293 | case IDECOUNT:
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nkeynes@125 | 294 | if( ide_can_write_regs() )
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nkeynes@125 | 295 | idereg.count = (uint8_t)val;
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nkeynes@125 | 296 | break;
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nkeynes@125 | 297 | case IDELBA0:
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nkeynes@125 | 298 | if( ide_can_write_regs() )
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nkeynes@125 | 299 | idereg.lba0 = (uint8_t)val;
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nkeynes@125 | 300 | break;
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nkeynes@125 | 301 | case IDELBA1:
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nkeynes@125 | 302 | if( ide_can_write_regs() )
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nkeynes@125 | 303 | idereg.lba1 = (uint8_t)val;
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nkeynes@125 | 304 | break;
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nkeynes@125 | 305 | case IDELBA2:
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nkeynes@125 | 306 | if( ide_can_write_regs() )
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nkeynes@125 | 307 | idereg.lba2 = (uint8_t)val;
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nkeynes@125 | 308 | break;
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nkeynes@125 | 309 | case IDEDEV:
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nkeynes@125 | 310 | if( ide_can_write_regs() )
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nkeynes@125 | 311 | idereg.device = (uint8_t)val;
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nkeynes@125 | 312 | break;
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nkeynes@125 | 313 | case IDECMD:
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nkeynes@125 | 314 | if( ide_can_write_regs() ) {
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nkeynes@125 | 315 | ide_write_command( (uint8_t)val );
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nkeynes@125 | 316 | }
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nkeynes@125 | 317 | break;
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nkeynes@125 | 318 | case IDEDMACTL1:
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nkeynes@155 | 319 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@125 | 320 | case IDEDMACTL2:
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nkeynes@125 | 321 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@155 | 322 | asic_ide_dma_transfer( );
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nkeynes@125 | 323 | break;
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nkeynes@125 | 324 | default:
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nkeynes@2 | 325 | MMIO_WRITE( EXTDMA, reg, val );
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nkeynes@2 | 326 | }
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nkeynes@1 | 327 | }
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nkeynes@1 | 328 |
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nkeynes@1 | 329 | MMIO_REGION_READ_FN( EXTDMA, reg )
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nkeynes@1 | 330 | {
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nkeynes@56 | 331 | uint32_t val;
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nkeynes@1 | 332 | switch( reg ) {
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nkeynes@158 | 333 | case IDEALTSTATUS:
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nkeynes@158 | 334 | val = idereg.status;
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nkeynes@158 | 335 | return val;
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nkeynes@158 | 336 | case IDEDATA: return ide_read_data_pio( );
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nkeynes@158 | 337 | case IDEFEAT: return idereg.error;
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nkeynes@158 | 338 | case IDECOUNT:return idereg.count;
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nkeynes@158 | 339 | case IDELBA0: return idereg.disc;
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nkeynes@158 | 340 | case IDELBA1: return idereg.lba1;
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nkeynes@158 | 341 | case IDELBA2: return idereg.lba2;
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nkeynes@158 | 342 | case IDEDEV: return idereg.device;
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nkeynes@158 | 343 | case IDECMD:
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nkeynes@158 | 344 | val = ide_read_status();
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nkeynes@158 | 345 | return val;
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nkeynes@158 | 346 | default:
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nkeynes@158 | 347 | val = MMIO_READ( EXTDMA, reg );
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nkeynes@158 | 348 | return val;
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nkeynes@1 | 349 | }
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nkeynes@1 | 350 | }
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nkeynes@1 | 351 |
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