filename | src/asic.c |
changeset | 137:41907543d890 |
prev | 125:49bf45f8210a |
next | 155:be61d1a20937 |
author | nkeynes |
date | Tue May 23 13:10:28 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Add texcache invalidates on direct writes to 64-bit vram. Technically we should do it on direct writes to 32-bit vram as well, but noone (sane) is going to try to write a texture there... |
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nkeynes@31 | 1 | /** |
nkeynes@137 | 2 | * $Id: asic.c,v 1.14 2006-04-30 01:50:13 nkeynes Exp $ |
nkeynes@31 | 3 | * |
nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing, |
nkeynes@31 | 5 | * and DMA). |
nkeynes@31 | 6 | * |
nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@31 | 8 | * |
nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@31 | 12 | * (at your option) any later version. |
nkeynes@31 | 13 | * |
nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@31 | 17 | * GNU General Public License for more details. |
nkeynes@31 | 18 | */ |
nkeynes@35 | 19 | |
nkeynes@35 | 20 | #define MODULE asic_module |
nkeynes@35 | 21 | |
nkeynes@1 | 22 | #include <assert.h> |
nkeynes@137 | 23 | #include <stdlib.h> |
nkeynes@1 | 24 | #include "dream.h" |
nkeynes@1 | 25 | #include "mem.h" |
nkeynes@1 | 26 | #include "sh4/intc.h" |
nkeynes@56 | 27 | #include "sh4/dmac.h" |
nkeynes@2 | 28 | #include "dreamcast.h" |
nkeynes@25 | 29 | #include "maple/maple.h" |
nkeynes@25 | 30 | #include "gdrom/ide.h" |
nkeynes@15 | 31 | #include "asic.h" |
nkeynes@1 | 32 | #define MMIO_IMPL |
nkeynes@1 | 33 | #include "asic.h" |
nkeynes@1 | 34 | /* |
nkeynes@1 | 35 | * Open questions: |
nkeynes@1 | 36 | * 1) Does changing the mask after event occurance result in the |
nkeynes@1 | 37 | * interrupt being delivered immediately? |
nkeynes@1 | 38 | * TODO: Logic diagram of ASIC event/interrupt logic. |
nkeynes@1 | 39 | * |
nkeynes@1 | 40 | * ... don't even get me started on the "EXTDMA" page, about which, apparently, |
nkeynes@1 | 41 | * practically nothing is publicly known... |
nkeynes@1 | 42 | */ |
nkeynes@1 | 43 | |
nkeynes@15 | 44 | struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL, |
nkeynes@23 | 45 | NULL, NULL, NULL }; |
nkeynes@15 | 46 | |
nkeynes@137 | 47 | #define G2_BIT5_TICKS 8 |
nkeynes@137 | 48 | #define G2_BIT4_TICKS 16 |
nkeynes@137 | 49 | #define G2_BIT0_ON_TICKS 24 |
nkeynes@137 | 50 | #define G2_BIT0_OFF_TICKS 24 |
nkeynes@137 | 51 | |
nkeynes@137 | 52 | struct asic_g2_state { |
nkeynes@137 | 53 | unsigned int bit5_off_timer; |
nkeynes@137 | 54 | unsigned int bit4_on_timer; |
nkeynes@137 | 55 | unsigned int bit4_off_timer; |
nkeynes@137 | 56 | unsigned int bit0_on_timer; |
nkeynes@137 | 57 | unsigned int bit0_off_timer; |
nkeynes@137 | 58 | } g2_state; |
nkeynes@137 | 59 | |
nkeynes@137 | 60 | /* FIXME: Handle rollover */ |
nkeynes@137 | 61 | void asic_g2_write_word() |
nkeynes@137 | 62 | { |
nkeynes@137 | 63 | g2_state.bit5_off_timer = sh4r.icount + G2_BIT5_TICKS; |
nkeynes@137 | 64 | if( g2_state.bit4_off_timer < sh4r.icount ) |
nkeynes@137 | 65 | g2_state.bit4_on_timer = sh4r.icount + G2_BIT5_TICKS; |
nkeynes@137 | 66 | g2_state.bit4_off_timer = max(sh4r.icount,g2_state.bit4_off_timer) + G2_BIT4_TICKS; |
nkeynes@137 | 67 | if( g2_state.bit0_off_timer < sh4r.icount ) { |
nkeynes@137 | 68 | g2_state.bit0_on_timer = sh4r.icount + G2_BIT0_ON_TICKS; |
nkeynes@137 | 69 | g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS; |
nkeynes@137 | 70 | } else { |
nkeynes@137 | 71 | g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS; |
nkeynes@137 | 72 | } |
nkeynes@137 | 73 | MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 ); |
nkeynes@137 | 74 | } |
nkeynes@137 | 75 | |
nkeynes@137 | 76 | static uint32_t g2_read_status() |
nkeynes@137 | 77 | { |
nkeynes@137 | 78 | uint32_t val = MMIO_READ( ASIC, G2STATUS ); |
nkeynes@137 | 79 | if( g2_state.bit5_off_timer <= sh4r.icount ) |
nkeynes@137 | 80 | val = val & (~0x20); |
nkeynes@137 | 81 | if( g2_state.bit4_off_timer <= sh4r.icount ) |
nkeynes@137 | 82 | val = val & (~0x10); |
nkeynes@137 | 83 | else if( g2_state.bit4_on_timer <= sh4r.icount ) |
nkeynes@137 | 84 | val = val | 0x10; |
nkeynes@137 | 85 | if( g2_state.bit0_off_timer <= sh4r.icount ) |
nkeynes@137 | 86 | val = val & (~0x01); |
nkeynes@137 | 87 | else if( g2_state.bit0_on_timer <= sh4r.icount ) |
nkeynes@137 | 88 | val = val | 0x01; |
nkeynes@137 | 89 | return val | 0x0E; |
nkeynes@137 | 90 | } |
nkeynes@137 | 91 | |
nkeynes@20 | 92 | void asic_check_cleared_events( void ); |
nkeynes@20 | 93 | |
nkeynes@1 | 94 | void asic_init( void ) |
nkeynes@1 | 95 | { |
nkeynes@1 | 96 | register_io_region( &mmio_region_ASIC ); |
nkeynes@1 | 97 | register_io_region( &mmio_region_EXTDMA ); |
nkeynes@1 | 98 | mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */ |
nkeynes@1 | 99 | } |
nkeynes@1 | 100 | |
nkeynes@1 | 101 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 102 | { |
nkeynes@1 | 103 | switch( reg ) { |
nkeynes@125 | 104 | case PIRQ1: |
nkeynes@125 | 105 | val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */ |
nkeynes@125 | 106 | /* fallthrough */ |
nkeynes@56 | 107 | case PIRQ0: |
nkeynes@56 | 108 | case PIRQ2: |
nkeynes@56 | 109 | /* Clear any interrupts */ |
nkeynes@56 | 110 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val ); |
nkeynes@56 | 111 | asic_check_cleared_events(); |
nkeynes@56 | 112 | break; |
nkeynes@56 | 113 | case MAPLE_STATE: |
nkeynes@56 | 114 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@56 | 115 | if( val & 1 ) { |
nkeynes@56 | 116 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0; |
nkeynes@56 | 117 | WARN( "Maple request initiated at %08X, halting", maple_addr ); |
nkeynes@56 | 118 | maple_handle_buffer( maple_addr ); |
nkeynes@56 | 119 | MMIO_WRITE( ASIC, reg, 0 ); |
nkeynes@56 | 120 | } |
nkeynes@56 | 121 | break; |
nkeynes@56 | 122 | case PVRDMACTL: /* Initiate PVR DMA transfer */ |
nkeynes@94 | 123 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@94 | 124 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]", |
nkeynes@94 | 125 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@56 | 126 | if( val & 1 ) { |
nkeynes@56 | 127 | uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0; |
nkeynes@56 | 128 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT ); |
nkeynes@56 | 129 | char *data = alloca( count ); |
nkeynes@56 | 130 | uint32_t rcount = DMAC_get_buffer( 2, data, count ); |
nkeynes@56 | 131 | if( rcount != count ) |
nkeynes@56 | 132 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count ); |
nkeynes@100 | 133 | mem_copy_to_sh4( dest_addr, data, rcount ); |
nkeynes@56 | 134 | asic_event( EVENT_PVR_DMA ); |
nkeynes@56 | 135 | } |
nkeynes@56 | 136 | break; |
nkeynes@56 | 137 | default: |
nkeynes@56 | 138 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@56 | 139 | WARN( "Write to ASIC (%03X <= %08X) [%s: %s]", |
nkeynes@56 | 140 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@1 | 141 | } |
nkeynes@1 | 142 | } |
nkeynes@1 | 143 | |
nkeynes@1 | 144 | int32_t mmio_region_ASIC_read( uint32_t reg ) |
nkeynes@1 | 145 | { |
nkeynes@1 | 146 | int32_t val; |
nkeynes@1 | 147 | switch( reg ) { |
nkeynes@2 | 148 | /* |
nkeynes@2 | 149 | case 0x89C: |
nkeynes@2 | 150 | sh4_stop(); |
nkeynes@2 | 151 | return 0x000000B; |
nkeynes@2 | 152 | */ |
nkeynes@94 | 153 | case PIRQ0: |
nkeynes@94 | 154 | case PIRQ1: |
nkeynes@94 | 155 | case PIRQ2: |
nkeynes@94 | 156 | case IRQA0: |
nkeynes@94 | 157 | case IRQA1: |
nkeynes@94 | 158 | case IRQA2: |
nkeynes@94 | 159 | case IRQB0: |
nkeynes@94 | 160 | case IRQB1: |
nkeynes@94 | 161 | case IRQB2: |
nkeynes@94 | 162 | case IRQC0: |
nkeynes@94 | 163 | case IRQC1: |
nkeynes@94 | 164 | case IRQC2: |
nkeynes@94 | 165 | val = MMIO_READ(ASIC, reg); |
nkeynes@94 | 166 | // WARN( "Read from ASIC (%03X => %08X) [%s: %s]", |
nkeynes@94 | 167 | // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@94 | 168 | return val; |
nkeynes@94 | 169 | case G2STATUS: |
nkeynes@137 | 170 | return g2_read_status(); |
nkeynes@94 | 171 | default: |
nkeynes@94 | 172 | val = MMIO_READ(ASIC, reg); |
nkeynes@94 | 173 | WARN( "Read from ASIC (%03X => %08X) [%s: %s]", |
nkeynes@94 | 174 | reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) ); |
nkeynes@94 | 175 | return val; |
nkeynes@1 | 176 | } |
nkeynes@94 | 177 | |
nkeynes@1 | 178 | } |
nkeynes@1 | 179 | |
nkeynes@1 | 180 | void asic_event( int event ) |
nkeynes@1 | 181 | { |
nkeynes@1 | 182 | int offset = ((event&0x60)>>3); |
nkeynes@1 | 183 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F)); |
nkeynes@1 | 184 | |
nkeynes@1 | 185 | if( result & MMIO_READ(ASIC, IRQA0 + offset) ) |
nkeynes@1 | 186 | intc_raise_interrupt( INT_IRQ13 ); |
nkeynes@1 | 187 | if( result & MMIO_READ(ASIC, IRQB0 + offset) ) |
nkeynes@1 | 188 | intc_raise_interrupt( INT_IRQ11 ); |
nkeynes@1 | 189 | if( result & MMIO_READ(ASIC, IRQC0 + offset) ) |
nkeynes@1 | 190 | intc_raise_interrupt( INT_IRQ9 ); |
nkeynes@1 | 191 | } |
nkeynes@1 | 192 | |
nkeynes@125 | 193 | void asic_clear_event( int event ) { |
nkeynes@125 | 194 | int offset = ((event&0x60)>>3); |
nkeynes@125 | 195 | uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F))); |
nkeynes@125 | 196 | MMIO_WRITE( ASIC, PIRQ0 + offset, result ); |
nkeynes@125 | 197 | |
nkeynes@125 | 198 | asic_check_cleared_events(); |
nkeynes@125 | 199 | } |
nkeynes@125 | 200 | |
nkeynes@20 | 201 | void asic_check_cleared_events( ) |
nkeynes@20 | 202 | { |
nkeynes@20 | 203 | int i, setA = 0, setB = 0, setC = 0; |
nkeynes@20 | 204 | uint32_t bits; |
nkeynes@20 | 205 | for( i=0; i<3; i++ ) { |
nkeynes@20 | 206 | bits = MMIO_READ( ASIC, PIRQ0 + i ); |
nkeynes@20 | 207 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i )); |
nkeynes@20 | 208 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i )); |
nkeynes@20 | 209 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i )); |
nkeynes@20 | 210 | } |
nkeynes@20 | 211 | if( setA == 0 ) |
nkeynes@20 | 212 | intc_clear_interrupt( INT_IRQ13 ); |
nkeynes@20 | 213 | if( setB == 0 ) |
nkeynes@20 | 214 | intc_clear_interrupt( INT_IRQ11 ); |
nkeynes@20 | 215 | if( setC == 0 ) |
nkeynes@20 | 216 | intc_clear_interrupt( INT_IRQ9 ); |
nkeynes@20 | 217 | } |
nkeynes@1 | 218 | |
nkeynes@1 | 219 | |
nkeynes@1 | 220 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val ) |
nkeynes@1 | 221 | { |
nkeynes@125 | 222 | WARN( "EXTDMA write %08X <= %08X", reg, val ); |
nkeynes@125 | 223 | |
nkeynes@2 | 224 | switch( reg ) { |
nkeynes@125 | 225 | case IDEALTSTATUS: /* Device control */ |
nkeynes@125 | 226 | ide_write_control( val ); |
nkeynes@125 | 227 | break; |
nkeynes@125 | 228 | case IDEDATA: |
nkeynes@125 | 229 | ide_write_data_pio( val ); |
nkeynes@125 | 230 | break; |
nkeynes@125 | 231 | case IDEFEAT: |
nkeynes@125 | 232 | if( ide_can_write_regs() ) |
nkeynes@125 | 233 | idereg.feature = (uint8_t)val; |
nkeynes@125 | 234 | break; |
nkeynes@125 | 235 | case IDECOUNT: |
nkeynes@125 | 236 | if( ide_can_write_regs() ) |
nkeynes@125 | 237 | idereg.count = (uint8_t)val; |
nkeynes@125 | 238 | break; |
nkeynes@125 | 239 | case IDELBA0: |
nkeynes@125 | 240 | if( ide_can_write_regs() ) |
nkeynes@125 | 241 | idereg.lba0 = (uint8_t)val; |
nkeynes@125 | 242 | break; |
nkeynes@125 | 243 | case IDELBA1: |
nkeynes@125 | 244 | if( ide_can_write_regs() ) |
nkeynes@125 | 245 | idereg.lba1 = (uint8_t)val; |
nkeynes@125 | 246 | break; |
nkeynes@125 | 247 | case IDELBA2: |
nkeynes@125 | 248 | if( ide_can_write_regs() ) |
nkeynes@125 | 249 | idereg.lba2 = (uint8_t)val; |
nkeynes@125 | 250 | break; |
nkeynes@125 | 251 | case IDEDEV: |
nkeynes@125 | 252 | if( ide_can_write_regs() ) |
nkeynes@125 | 253 | idereg.device = (uint8_t)val; |
nkeynes@125 | 254 | break; |
nkeynes@125 | 255 | case IDECMD: |
nkeynes@125 | 256 | if( ide_can_write_regs() ) { |
nkeynes@125 | 257 | ide_write_command( (uint8_t)val ); |
nkeynes@125 | 258 | } |
nkeynes@125 | 259 | break; |
nkeynes@125 | 260 | case IDEDMACTL1: |
nkeynes@125 | 261 | case IDEDMACTL2: |
nkeynes@125 | 262 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@125 | 263 | if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 && |
nkeynes@125 | 264 | MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) { |
nkeynes@125 | 265 | uint32_t target_addr = MMIO_READ( EXTDMA, IDEDMASH4 ); |
nkeynes@125 | 266 | uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ ); |
nkeynes@125 | 267 | int dir = MMIO_READ( EXTDMA, IDEDMADIR ); |
nkeynes@125 | 268 | } |
nkeynes@125 | 269 | break; |
nkeynes@125 | 270 | default: |
nkeynes@2 | 271 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@2 | 272 | } |
nkeynes@1 | 273 | } |
nkeynes@1 | 274 | |
nkeynes@1 | 275 | MMIO_REGION_READ_FN( EXTDMA, reg ) |
nkeynes@1 | 276 | { |
nkeynes@56 | 277 | uint32_t val; |
nkeynes@1 | 278 | switch( reg ) { |
nkeynes@2 | 279 | case IDEALTSTATUS: return idereg.status; |
nkeynes@2 | 280 | case IDEDATA: return ide_read_data_pio( ); |
nkeynes@2 | 281 | case IDEFEAT: return idereg.error; |
nkeynes@2 | 282 | case IDECOUNT:return idereg.count; |
nkeynes@2 | 283 | case IDELBA0: return idereg.disc; |
nkeynes@2 | 284 | case IDELBA1: return idereg.lba1; |
nkeynes@2 | 285 | case IDELBA2: return idereg.lba2; |
nkeynes@2 | 286 | case IDEDEV: return idereg.device; |
nkeynes@2 | 287 | case IDECMD: |
nkeynes@125 | 288 | return ide_read_status(); |
nkeynes@1 | 289 | default: |
nkeynes@56 | 290 | val = MMIO_READ( EXTDMA, reg ); |
nkeynes@94 | 291 | //DEBUG( "EXTDMA read %08X => %08X", reg, val ); |
nkeynes@56 | 292 | return val; |
nkeynes@1 | 293 | } |
nkeynes@1 | 294 | } |
nkeynes@1 | 295 |
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