/**

 * $Id: sh4core.c,v 1.44 2007-09-11 02:14:46 nkeynes Exp $

 * 

 * SH4 emulation core, and parent module for all the SH4 peripheral

 * modules.

 *

 * Copyright (c) 2005 Nathan Keynes.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#define MODULE sh4_module

#include <math.h>

#include "dream.h"

#include "sh4/sh4core.h"

#include "sh4/sh4mmio.h"

#include "sh4/intc.h"

#include "mem.h"

#include "clock.h"

#include "syscall.h"

#define SH4_CALLTRACE 1

#define MAX_INT 0x7FFFFFFF

#define MIN_INT 0x80000000

#define MAX_INTF 2147483647.0

#define MIN_INTF -2147483648.0

#define EXV_EXCEPTION    0x100  /* General exception vector */

#define EXV_TLBMISS      0x400  /* TLB-miss exception vector */

#define EXV_INTERRUPT    0x600  /* External interrupt vector */

/********************** SH4 Module Definition ****************************/

void sh4_init( void );

void sh4_reset( void );

uint32_t sh4_run_slice( uint32_t );

void sh4_start( void );

void sh4_stop( void );

void sh4_save_state( FILE *f );

int sh4_load_state( FILE *f );

void sh4_accept_interrupt( void );

struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 

				       NULL, sh4_run_slice, sh4_stop,

				       sh4_save_state, sh4_load_state };

struct sh4_registers sh4r;

void sh4_init(void)

{

    register_io_regions( mmio_list_sh4mmio );

    MMU_init();

    sh4_reset();

}

void sh4_reset(void)

{

    /* zero everything out, for the sake of having a consistent state. */

    memset( &sh4r, 0, sizeof(sh4r) );

    /* Resume running if we were halted */

    sh4r.sh4_state = SH4_STATE_RUNNING;

    sh4r.pc    = 0xA0000000;

    sh4r.new_pc= 0xA0000002;

    sh4r.vbr   = 0x00000000;

    sh4r.fpscr = 0x00040001;

    sh4r.sr    = 0x700000F0;

    sh4r.fr_bank = &sh4r.fr[0][0];

    /* Mem reset will do this, but if we want to reset _just_ the SH4... */

    MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );

    /* Peripheral modules */

    CPG_reset();

    INTC_reset();

    MMU_reset();

    TMU_reset();

    SCIF_reset();

}

static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];

static int sh4_breakpoint_count = 0;

static uint16_t *sh4_icache = NULL;

static uint32_t sh4_icache_addr = 0;

void sh4_set_breakpoint( uint32_t pc, int type )

{

    sh4_breakpoints[sh4_breakpoint_count].address = pc;

    sh4_breakpoints[sh4_breakpoint_count].type = type;

    sh4_breakpoint_count++;

}

gboolean sh4_clear_breakpoint( uint32_t pc, int type )

{

    int i;

    for( i=0; i<sh4_breakpoint_count; i++ ) {

	if( sh4_breakpoints[i].address == pc && 

	    sh4_breakpoints[i].type == type ) {

	    while( ++i < sh4_breakpoint_count ) {

		sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;

		sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;

	    }

	    sh4_breakpoint_count--;

	    return TRUE;

	}

    }

    return FALSE;

}

int sh4_get_breakpoint( uint32_t pc )

{

    int i;

    for( i=0; i<sh4_breakpoint_count; i++ ) {

	if( sh4_breakpoints[i].address == pc )

	    return sh4_breakpoints[i].type;

    }

    return 0;

}

uint32_t sh4_run_slice( uint32_t nanosecs ) 

{

    int i;

    sh4r.slice_cycle = 0;

    if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

	if( sh4r.event_pending < nanosecs ) {

	    sh4r.sh4_state = SH4_STATE_RUNNING;

	    sh4r.slice_cycle = sh4r.event_pending;

	}

    }

    if( sh4_breakpoint_count == 0 ) {

	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

	    if( SH4_EVENT_PENDING() ) {

		if( sh4r.event_types & PENDING_EVENT ) {

		    event_execute();

		}

		/* Eventq execute may (quite likely) deliver an immediate IRQ */

		if( sh4r.event_types & PENDING_IRQ ) {

		    sh4_accept_interrupt();

		}

	    }

	    if( !sh4_execute_instruction() ) {

		break;

	    }

	}

    } else {

	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

	    if( SH4_EVENT_PENDING() ) {

		if( sh4r.event_types & PENDING_EVENT ) {

		    event_execute();

		}

		/* Eventq execute may (quite likely) deliver an immediate IRQ */

		if( sh4r.event_types & PENDING_IRQ ) {

		    sh4_accept_interrupt();

		}

	    }

	    if( !sh4_execute_instruction() )

		break;

#ifdef ENABLE_DEBUG_MODE

	    for( i=0; i<sh4_breakpoint_count; i++ ) {

		if( sh4_breakpoints[i].address == sh4r.pc ) {

		    break;

		}

	    }

	    if( i != sh4_breakpoint_count ) {

		dreamcast_stop();

		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

		break;

	    }

#endif	

	}

    }

    /* If we aborted early, but the cpu is still technically running,

     * we're doing a hard abort - cut the timeslice back to what we

     * actually executed

     */

    if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

	nanosecs = sh4r.slice_cycle;

    }

    if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

	TMU_run_slice( nanosecs );

	SCIF_run_slice( nanosecs );

    }

    return nanosecs;

}

void sh4_stop(void)

{

}

void sh4_save_state( FILE *f )

{

    fwrite( &sh4r, sizeof(sh4r), 1, f );

    MMU_save_state( f );

    INTC_save_state( f );

    TMU_save_state( f );

    SCIF_save_state( f );

}

int sh4_load_state( FILE * f )

{

    fread( &sh4r, sizeof(sh4r), 1, f );

    MMU_load_state( f );

    INTC_load_state( f );

    TMU_load_state( f );

    return SCIF_load_state( f );

}

/********************** SH4 emulation core  ****************************/

void sh4_set_pc( int pc )

{

    sh4r.pc = pc;

    sh4r.new_pc = pc+2;

}

#define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

#define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

#if(SH4_CALLTRACE == 1)

#define MAX_CALLSTACK 32

static struct call_stack {

    sh4addr_t call_addr;

    sh4addr_t target_addr;

    sh4addr_t stack_pointer;

} call_stack[MAX_CALLSTACK];

static int call_stack_depth = 0;

int sh4_call_trace_on = 0;

static inline trace_call( sh4addr_t source, sh4addr_t dest ) 

{

    if( call_stack_depth < MAX_CALLSTACK ) {

	call_stack[call_stack_depth].call_addr = source;

	call_stack[call_stack_depth].target_addr = dest;

	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

    }

    call_stack_depth++;

}

static inline trace_return( sh4addr_t source, sh4addr_t dest )

{

    if( call_stack_depth > 0 ) {

	call_stack_depth--;

    }

}

void fprint_stack_trace( FILE *f )

{

    int i = call_stack_depth -1;

    if( i >= MAX_CALLSTACK )

	i = MAX_CALLSTACK - 1;

    for( ; i >= 0; i-- ) {

	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 

		 (call_stack_depth - i), call_stack[i].call_addr,

		 call_stack[i].target_addr, call_stack[i].stack_pointer );

    }

}

#define TRACE_CALL( source, dest ) trace_call(source, dest)

#define TRACE_RETURN( source, dest ) trace_return(source, dest)

#else

#define TRACE_CALL( dest, rts ) 

#define TRACE_RETURN( source, dest )

#endif

#define RAISE( x, v ) do{			\

    if( sh4r.vbr == 0 ) { \

        ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \

        dreamcast_stop(); return FALSE;	\

    } else { \

        sh4r.spc = sh4r.pc;	\

        sh4r.ssr = sh4_read_sr(); \

        sh4r.sgr = sh4r.r[15]; \

        MMIO_WRITE(MMU,EXPEVT,x); \

        sh4r.pc = sh4r.vbr + v; \

        sh4r.new_pc = sh4r.pc + 2; \

        sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \

	if( sh4r.in_delay_slot ) { \

	    sh4r.in_delay_slot = 0; \

	    sh4r.spc -= 2; \

	} \

    } \

    return TRUE; } while(0)

#define MEM_READ_BYTE( addr ) sh4_read_byte(addr)

#define MEM_READ_WORD( addr ) sh4_read_word(addr)

#define MEM_READ_LONG( addr ) sh4_read_long(addr)

#define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)

#define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)

#define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)

#define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

#define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

#define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

#define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

#define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

#define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

#define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

#define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

#define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

#define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

static void sh4_switch_banks( )

{

    uint32_t tmp[8];

    memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );

    memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );

    memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );

}

void sh4_write_sr( uint32_t newval )

{

    if( (newval ^ sh4r.sr) & SR_RB )

        sh4_switch_banks();

    sh4r.sr = newval;

    sh4r.t = (newval&SR_T) ? 1 : 0;

    sh4r.s = (newval&SR_S) ? 1 : 0;

    sh4r.m = (newval&SR_M) ? 1 : 0;

    sh4r.q = (newval&SR_Q) ? 1 : 0;

    intc_mask_changed();

}

static void sh4_write_float( uint32_t addr, int reg )

{

    if( IS_FPU_DOUBLESIZE() ) {

	if( reg & 1 ) {

	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

	} else {

	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 

	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

	}

    } else {

	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

    }

}

static void sh4_read_float( uint32_t addr, int reg )

{

    if( IS_FPU_DOUBLESIZE() ) {

	if( reg & 1 ) {

	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

	} else {

	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

	}

    } else {

	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

    }

}

uint32_t sh4_read_sr( void )

{

    /* synchronize sh4r.sr with the various bitflags */

    sh4r.sr &= SR_MQSTMASK;

    if( sh4r.t ) sh4r.sr |= SR_T;

    if( sh4r.s ) sh4r.sr |= SR_S;

    if( sh4r.m ) sh4r.sr |= SR_M;

    if( sh4r.q ) sh4r.sr |= SR_Q;

    return sh4r.sr;

}

/**

 * Raise a general CPU exception for the specified exception code.

 * (NOT for TRAPA or TLB exceptions)

 */

gboolean sh4_raise_exception( int code )

{

    RAISE( code, EXV_EXCEPTION );

}

gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {

    if( sh4r.in_delay_slot ) {

	return sh4_raise_exception(slot_code);

    } else {

	return sh4_raise_exception(normal_code);

    }

}

gboolean sh4_raise_tlb_exception( int code )

{

    RAISE( code, EXV_TLBMISS );

}

void sh4_accept_interrupt( void )

{

    uint32_t code = intc_accept_interrupt();

    sh4r.ssr = sh4_read_sr();

    sh4r.spc = sh4r.pc;

    sh4r.sgr = sh4r.r[15];

    sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );

    MMIO_WRITE( MMU, INTEVT, code );

    sh4r.pc = sh4r.vbr + 0x600;

    sh4r.new_pc = sh4r.pc + 2;

    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );

}

gboolean sh4_execute_instruction( void )

{

    uint32_t pc;

    unsigned short ir;

    uint32_t tmp;

    float ftmp;

    double dtmp;

#define R0 sh4r.r[0]

    pc = sh4r.pc;

    if( pc > 0xFFFFFF00 ) {

	/* SYSCALL Magic */

	syscall_invoke( pc );

	sh4r.in_delay_slot = 0;

	pc = sh4r.pc = sh4r.pr;

	sh4r.new_pc = sh4r.pc + 2;

    }

    CHECKRALIGN16(pc);

    /* Read instruction */

    uint32_t pageaddr = pc >> 12;

    if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {

	ir = sh4_icache[(pc&0xFFF)>>1];

    } else {

	sh4_icache = (uint16_t *)mem_get_page(pc);

	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {

	    /* If someone's actually been so daft as to try to execute out of an IO

	     * region, fallback on the full-blown memory read

	     */

	    sh4_icache = NULL;

	    ir = MEM_READ_WORD(pc);

	} else {

	    sh4_icache_addr = pageaddr;

	    ir = sh4_icache[(pc&0xFFF)>>1];

	}

    }

        switch( (ir&0xF000) >> 12 ) {

            case 0x0:

                switch( ir&0xF ) {

                    case 0x2:

                        switch( (ir&0x80) >> 7 ) {

                            case 0x0:

                                switch( (ir&0x70) >> 4 ) {

                                    case 0x0:

                                        { /* STC SR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        CHECKPRIV();

                                        sh4r.r[Rn] = sh4_read_sr();

                                        }

                                        break;

                                    case 0x1:

                                        { /* STC GBR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        CHECKPRIV();

                                        sh4r.r[Rn] = sh4r.gbr;

                                        }

                                        break;

                                    case 0x2:

                                        { /* STC VBR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        CHECKPRIV();

                                        sh4r.r[Rn] = sh4r.vbr;

                                        }

                                        break;

                                    case 0x3:

                                        { /* STC SSR, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        CHECKPRIV();

                                        sh4r.r[Rn] = sh4r.ssr;

                                        }

                                        break;

                                    case 0x4:

                                        { /* STC SPC, Rn */

                                        uint32_t Rn = ((ir>>8)&0xF); 

                                        CHECKPRIV();

                                        sh4r.r[Rn] = sh4r.spc;

                                        }

                                        break;

                                    default:

                                        UNDEF();

                                        break;

                                }

                                break;

                            case 0x1:

                                { /* STC Rm_BANK, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 

                                CHECKPRIV();

                                sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

                                }

                                break;

                        }

                        break;

                    case 0x3:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* BSRF Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                CHECKSLOTILLEGAL();

                                CHECKDEST( pc + 4 + sh4r.r[Rn] );

                                sh4r.in_delay_slot = 1;

                                sh4r.pr = sh4r.pc + 4;

                                sh4r.pc = sh4r.new_pc;

                                sh4r.new_pc = pc + 4 + sh4r.r[Rn];

                                TRACE_CALL( pc, sh4r.new_pc );

                                return TRUE;

                                }

                                break;

                            case 0x2:

                                { /* BRAF Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                CHECKSLOTILLEGAL();

                                CHECKDEST( pc + 4 + sh4r.r[Rn] );

                                sh4r.in_delay_slot = 1;

                                sh4r.pc = sh4r.new_pc;

                                sh4r.new_pc = pc + 4 + sh4r.r[Rn];

                                return TRUE;

                                }

                                break;

                            case 0x8:

                                { /* PREF @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                tmp = sh4r.r[Rn];

                                if( (tmp & 0xFC000000) == 0xE0000000 ) {

                           	 sh4_flush_store_queue(tmp);

                                }

                                }

                                break;

                            case 0x9:

                                { /* OCBI @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xA:

                                { /* OCBP @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xB:

                                { /* OCBWB @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                }

                                break;

                            case 0xC:

                                { /* MOVCA.L R0, @Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                tmp = sh4r.r[Rn];

                                CHECKWALIGN32(tmp);

                                MEM_WRITE_LONG( tmp, R0 );

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0x4:

                        { /* MOV.B Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x5:

                        { /* MOV.W Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKWALIGN16( R0 + sh4r.r[Rn] );

                        MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x6:

                        { /* MOV.L Rm, @(R0, Rn) */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKWALIGN32( R0 + sh4r.r[Rn] );

                        MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x7:

                        { /* MUL.L Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                                               (sh4r.r[Rm] * sh4r.r[Rn]);

                        }

                        break;

                    case 0x8:

                        switch( (ir&0xFF0) >> 4 ) {

                            case 0x0:

                                { /* CLRT */

                                sh4r.t = 0;

                                }

                                break;

                            case 0x1:

                                { /* SETT */

                                sh4r.t = 1;

                                }

                                break;

                            case 0x2:

                                { /* CLRMAC */

                                sh4r.mac = 0;

                                }

                                break;

                            case 0x3:

                                { /* LDTLB */

                                /* TODO */

                                }

                                break;

                            case 0x4:

                                { /* CLRS */

                                sh4r.s = 0;

                                }

                                break;

                            case 0x5:

                                { /* SETS */

                                sh4r.s = 1;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0x9:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* NOP */

                                /* NOP */

                                }

                                break;

                            case 0x1:

                                { /* DIV0U */

                                sh4r.m = sh4r.q = sh4r.t = 0;

                                }

                                break;

                            case 0x2:

                                { /* MOVT Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = sh4r.t;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xA:

                        switch( (ir&0xF0) >> 4 ) {

                            case 0x0:

                                { /* STS MACH, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = (sh4r.mac>>32);

                                }

                                break;

                            case 0x1:

                                { /* STS MACL, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = (uint32_t)sh4r.mac;

                                }

                                break;

                            case 0x2:

                                { /* STS PR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = sh4r.pr;

                                }

                                break;

                            case 0x3:

                                { /* STC SGR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                CHECKPRIV();

                                sh4r.r[Rn] = sh4r.sgr;

                                }

                                break;

                            case 0x5:

                                { /* STS FPUL, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = sh4r.fpul;

                                }

                                break;

                            case 0x6:

                                { /* STS FPSCR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                sh4r.r[Rn] = sh4r.fpscr;

                                }

                                break;

                            case 0xF:

                                { /* STC DBR, Rn */

                                uint32_t Rn = ((ir>>8)&0xF); 

                                CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xB:

                        switch( (ir&0xFF0) >> 4 ) {

                            case 0x0:

                                { /* RTS */

                                CHECKSLOTILLEGAL();

                                CHECKDEST( sh4r.pr );

                                sh4r.in_delay_slot = 1;

                                sh4r.pc = sh4r.new_pc;

                                sh4r.new_pc = sh4r.pr;

                                TRACE_RETURN( pc, sh4r.new_pc );

                                return TRUE;

                                }

                                break;

                            case 0x1:

                                { /* SLEEP */

                                if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

                            	sh4r.sh4_state = SH4_STATE_STANDBY;

                                } else {

                            	sh4r.sh4_state = SH4_STATE_SLEEP;

                                }

                                return FALSE; /* Halt CPU */

                                }

                                break;

                            case 0x2:

                                { /* RTE */

                                CHECKPRIV();

                                CHECKDEST( sh4r.spc );

                                CHECKSLOTILLEGAL();

                                sh4r.in_delay_slot = 1;

                                sh4r.pc = sh4r.new_pc;

                                sh4r.new_pc = sh4r.spc;

                                sh4_write_sr( sh4r.ssr );

                                return TRUE;

                                }

                                break;

                            default:

                                UNDEF();

                                break;

                        }

                        break;

                    case 0xC:

                        { /* MOV.B @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );

                        }

                        break;

                    case 0xD:

                        { /* MOV.W @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKRALIGN16( R0 + sh4r.r[Rm] );

                                           sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );

                        }

                        break;

                    case 0xE:

                        { /* MOV.L @(R0, Rm), Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKRALIGN32( R0 + sh4r.r[Rm] );

                                           sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );

                        }

                        break;

                    case 0xF:

                        { /* MAC.L @Rm+, @Rn+ */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKRALIGN32( sh4r.r[Rm] );

                        CHECKRALIGN32( sh4r.r[Rn] );

                        int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));

                        sh4r.r[Rn] += 4;

                        tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;

                        sh4r.r[Rm] += 4;

                        if( sh4r.s ) {

                            /* 48-bit Saturation. Yuch */

                            if( tmpl < (int64_t)0xFFFF800000000000LL )

                                tmpl = 0xFFFF800000000000LL;

                            else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

                                tmpl = 0x00007FFFFFFFFFFFLL;

                        }

                        sh4r.mac = tmpl;

                        }

                        break;

                    default:

                        UNDEF();

                        break;

                }

                break;

            case 0x1:

                { /* MOV.L Rm, @(disp, Rn) */

                uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 

                tmp = sh4r.r[Rn] + disp;

                CHECKWALIGN32( tmp );

                MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

                }

                break;

            case 0x2:

                switch( ir&0xF ) {

                    case 0x0:

                        { /* MOV.B Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x1:

                        { /* MOV.W Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x2:

                        { /* MOV.L Rm, @Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x4:

                        { /* MOV.B Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x5:

                        { /* MOV.W Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x6:

                        { /* MOV.L Rm, @-Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

                        }

                        break;

                    case 0x7:

                        { /* DIV0S Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.q = sh4r.r[Rn]>>31;

                        sh4r.m = sh4r.r[Rm]>>31;

                        sh4r.t = sh4r.q ^ sh4r.m;

                        }

                        break;

                    case 0x8:

                        { /* TST Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);

                        }

                        break;

                    case 0x9:

                        { /* AND Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] &= sh4r.r[Rm];

                        }

                        break;

                    case 0xA:

                        { /* XOR Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] ^= sh4r.r[Rm];

                        }

                        break;

                    case 0xB:

                        { /* OR Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] |= sh4r.r[Rm];

                        }

                        break;

                    case 0xC:

                        { /* CMP/STR Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        /* set T = 1 if any byte in RM & RN is the same */

                        tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

                        sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

                                 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

                        }

                        break;

                    case 0xD:

                        { /* XTRCT Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);

                        }

                        break;

                    case 0xE:

                        { /* MULU.W Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                                   (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

                        }

                        break;

                    case 0xF:

                        { /* MULS.W Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

                                   (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

                        }

                        break;

                    default:

                        UNDEF();

                        break;

                }

                break;

            case 0x3:

                switch( ir&0xF ) {

                    case 0x0:

                        { /* CMP/EQ Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );

                        }

                        break;

                    case 0x2:

                        { /* CMP/HS Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );

                        }

                        break;

                    case 0x3:

                        { /* CMP/GE Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

                        }

                        break;

                    case 0x4:

                        { /* DIV1 Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        /* This is just from the sh4p manual with some

                         * simplifications (someone want to check it's correct? :)

                         * Why they couldn't just provide a real DIV instruction...

                         */

                        uint32_t tmp0, tmp1, tmp2, dir;

                        dir = sh4r.q ^ sh4r.m;

                        sh4r.q = (sh4r.r[Rn] >> 31);

                        tmp2 = sh4r.r[Rm];

                        sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

                        tmp0 = sh4r.r[Rn];

                        if( dir ) {

                             sh4r.r[Rn] += tmp2;

                             tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

                        } else {

                             sh4r.r[Rn] -= tmp2;

                             tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

                        }

                        sh4r.q ^= sh4r.m ^ tmp1;

                        sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

                        }

                        break;

                    case 0x5:

                        { /* DMULU.L Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);

                        }

                        break;

                    case 0x6:

                        { /* CMP/HI Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );

                        }

                        break;

                    case 0x7:

                        { /* CMP/GT Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

                        }

                        break;

                    case 0x8:

                        { /* SUB Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        sh4r.r[Rn] -= sh4r.r[Rm];

                        }

                        break;

                    case 0xA:

                        { /* SUBC Rm, Rn */

                        uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 

                        tmp = sh4r.r[Rn];

                        sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

                        sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

                        }

                        break;

                    case 0xB: