lxdream.org :: lxdream/src/sh4/sh4x86.c r388:13bae2fb0373 (annotated)

tree revision 389:3e354da62264

filename	src/sh4/sh4x86.c
changeset	388:13bae2fb0373
prev	386:6fb10951326a
next	394:7eb172bfeefe
author	nkeynes
date	Tue Sep 18 09:11:53 2007 +0000 (16 years ago)
permissions	-rw-r--r--
last change	Up the max instruction size to 256 (TODO: work out what this should actually be)

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nkeynes@359	1	/**
nkeynes@388	2	* $Id: sh4x86.c,v 1.10 2007-09-18 08:59:00 nkeynes Exp $
nkeynes@359	3	*
nkeynes@359	4	* SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359	5	* outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359	6	* to test the optimizing versions against.
nkeynes@359	7	*
nkeynes@359	8	* Copyright (c) 2007 Nathan Keynes.
nkeynes@359	9	*
nkeynes@359	10	* This program is free software; you can redistribute it and/or modify
nkeynes@359	11	* it under the terms of the GNU General Public License as published by
nkeynes@359	12	* the Free Software Foundation; either version 2 of the License, or
nkeynes@359	13	* (at your option) any later version.
nkeynes@359	14	*
nkeynes@359	15	* This program is distributed in the hope that it will be useful,
nkeynes@359	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
nkeynes@359	18	* GNU General Public License for more details.
nkeynes@359	19	*/
nkeynes@359	20
nkeynes@368	21	#include <assert.h>
nkeynes@388	22	#include <math.h>
nkeynes@368	23
nkeynes@380	24	#ifndef NDEBUG
nkeynes@380	25	#define DEBUG_JUMPS 1
nkeynes@380	26	#endif
nkeynes@380	27
nkeynes@368	28	#include "sh4/sh4core.h"
nkeynes@368	29	#include "sh4/sh4trans.h"
nkeynes@388	30	#include "sh4/sh4mmio.h"
nkeynes@368	31	#include "sh4/x86op.h"
nkeynes@368	32	#include "clock.h"
nkeynes@368	33
nkeynes@368	34	#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368	35
nkeynes@368	36	/**
nkeynes@368	37	* Struct to manage internal translation state. This state is not saved -
nkeynes@368	38	* it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368	39	* sh4_translate_end_block()
nkeynes@368	40	*/
nkeynes@368	41	struct sh4_x86_state {
nkeynes@368	42	gboolean in_delay_slot;
nkeynes@368	43	gboolean priv_checked; /* true if we've already checked the cpu mode. */
nkeynes@368	44	gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@388	45	int exit_code;
nkeynes@368	46
nkeynes@368	47	/* Allocated memory for the (block-wide) back-patch list */
nkeynes@368	48	uint32_t **backpatch_list;
nkeynes@368	49	uint32_t backpatch_posn;
nkeynes@368	50	uint32_t backpatch_size;
nkeynes@368	51	};
nkeynes@368	52
nkeynes@368	53	#define EXIT_DATA_ADDR_READ 0
nkeynes@368	54	#define EXIT_DATA_ADDR_WRITE 7
nkeynes@368	55	#define EXIT_ILLEGAL 14
nkeynes@368	56	#define EXIT_SLOT_ILLEGAL 21
nkeynes@368	57	#define EXIT_FPU_DISABLED 28
nkeynes@368	58	#define EXIT_SLOT_FPU_DISABLED 35
nkeynes@368	59
nkeynes@368	60	static struct sh4_x86_state sh4_x86;
nkeynes@368	61
nkeynes@388	62	static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388	63	static uint32_t min_int = 0x80000000;
nkeynes@386	64	void signsat48( void )
nkeynes@386	65	{
nkeynes@386	66	if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
nkeynes@386	67	sh4r.mac = 0xFFFF800000000000LL;
nkeynes@386	68	else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@386	69	sh4r.mac = 0x00007FFFFFFFFFFFLL;
nkeynes@386	70	}
nkeynes@386	71
nkeynes@388	72	void sh4_fsca( uint32_t anglei, float *fr )
nkeynes@388	73	{
nkeynes@388	74	float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
nkeynes@388	75	*fr++ = cosf(angle);
nkeynes@388	76	*fr = sinf(angle);
nkeynes@388	77	}
nkeynes@388	78
nkeynes@388	79	void sh4_sleep()
nkeynes@388	80	{
nkeynes@388	81	if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@388	82	sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@388	83	} else {
nkeynes@388	84	sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@388	85	}
nkeynes@388	86	}
nkeynes@388	87
nkeynes@388	88	/**
nkeynes@388	89	* Compute the matrix tranform of fv given the matrix xf.
nkeynes@388	90	* Both fv and xf are word-swapped as per the sh4r.fr banks
nkeynes@388	91	*/
nkeynes@388	92	void sh4_ftrv( float target, float xf )
nkeynes@388	93	{
nkeynes@388	94	float fv[4] = { target[1], target[0], target[3], target[2] };
nkeynes@388	95	target[1] = xf[1] * fv[0] + xf[5]*fv[1] +
nkeynes@388	96	xf[9]fv[2] + xf[13]fv[3];
nkeynes@388	97	target[0] = xf[0] * fv[0] + xf[4]*fv[1] +
nkeynes@388	98	xf[8]fv[2] + xf[12]fv[3];
nkeynes@388	99	target[3] = xf[3] * fv[0] + xf[7]*fv[1] +
nkeynes@388	100	xf[11]fv[2] + xf[15]fv[3];
nkeynes@388	101	target[2] = xf[2] * fv[0] + xf[6]*fv[1] +
nkeynes@388	102	xf[10]fv[2] + xf[14]fv[3];
nkeynes@388	103	}
nkeynes@388	104
nkeynes@388	105
nkeynes@386	106
nkeynes@368	107	void sh4_x86_init()
nkeynes@368	108	{
nkeynes@368	109	sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@368	110	sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
nkeynes@368	111	}
nkeynes@368	112
nkeynes@368	113
nkeynes@368	114	static void sh4_x86_add_backpatch( uint8_t *ptr )
nkeynes@368	115	{
nkeynes@368	116	if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368	117	sh4_x86.backpatch_size <<= 1;
nkeynes@368	118	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
nkeynes@368	119	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368	120	}
nkeynes@368	121	sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
nkeynes@368	122	}
nkeynes@368	123
nkeynes@368	124	static void sh4_x86_do_backpatch( uint8_t *reloc_base )
nkeynes@368	125	{
nkeynes@368	126	unsigned int i;
nkeynes@368	127	for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
nkeynes@374	128	sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t )sh4_x86.backpatch_list[i]) - 4);
nkeynes@368	129	}
nkeynes@368	130	}
nkeynes@368	131
nkeynes@359	132	/**
nkeynes@359	133	* Emit an instruction to load an SH4 reg into a real register
nkeynes@359	134	*/
nkeynes@359	135	static inline void load_reg( int x86reg, int sh4reg )
nkeynes@359	136	{
nkeynes@359	137	/* mov [bp+n], reg */
nkeynes@361	138	OP(0x8B);
nkeynes@361	139	OP(0x45 + (x86reg<<3));
nkeynes@359	140	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	141	}
nkeynes@359	142
nkeynes@374	143	static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368	144	{
nkeynes@374	145	OP(0x0F);
nkeynes@374	146	OP(0xBF);
nkeynes@374	147	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368	148	}
nkeynes@368	149
nkeynes@374	150	static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368	151	{
nkeynes@374	152	OP(0x0F);
nkeynes@374	153	OP(0xB7);
nkeynes@374	154	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374	155
nkeynes@368	156	}
nkeynes@368	157
nkeynes@380	158	#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380	159	#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359	160	/**
nkeynes@359	161	* Emit an instruction to load an immediate value into a register
nkeynes@359	162	*/
nkeynes@359	163	static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359	164	/* mov #value, reg */
nkeynes@359	165	OP(0xB8 + x86reg);
nkeynes@359	166	OP32(value);
nkeynes@359	167	}
nkeynes@359	168
nkeynes@359	169	/**
nkeynes@359	170	* Emit an instruction to store an SH4 reg (RN)
nkeynes@359	171	*/
nkeynes@359	172	void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359	173	/* mov reg, [bp+n] */
nkeynes@361	174	OP(0x89);
nkeynes@361	175	OP(0x45 + (x86reg<<3));
nkeynes@359	176	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	177	}
nkeynes@374	178
nkeynes@374	179	#define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
nkeynes@374	180
nkeynes@375	181	/**
nkeynes@375	182	* Load an FR register (single-precision floating point) into an integer x86
nkeynes@375	183	* register (eg for register-to-register moves)
nkeynes@375	184	*/
nkeynes@375	185	void static inline load_fr( int bankreg, int x86reg, int frm )
nkeynes@375	186	{
nkeynes@375	187	OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
nkeynes@375	188	}
nkeynes@375	189
nkeynes@375	190	/**
nkeynes@375	191	* Store an FR register (single-precision floating point) into an integer x86
nkeynes@375	192	* register (eg for register-to-register moves)
nkeynes@375	193	*/
nkeynes@375	194	void static inline store_fr( int bankreg, int x86reg, int frn )
nkeynes@375	195	{
nkeynes@375	196	OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
nkeynes@375	197	}
nkeynes@375	198
nkeynes@375	199
nkeynes@375	200	/**
nkeynes@375	201	* Load a pointer to the back fp back into the specified x86 register. The
nkeynes@375	202	* bankreg must have been previously loaded with FPSCR.
nkeynes@388	203	* NB: 12 bytes
nkeynes@375	204	*/
nkeynes@374	205	static inline void load_xf_bank( int bankreg )
nkeynes@374	206	{
nkeynes@386	207	NOT_r32( bankreg );
nkeynes@374	208	SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
nkeynes@374	209	AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
nkeynes@374	210	OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
nkeynes@374	211	}
nkeynes@374	212
nkeynes@375	213	/**
nkeynes@386	214	* Update the fr_bank pointer based on the current fpscr value.
nkeynes@386	215	*/
nkeynes@386	216	static inline void update_fr_bank( int fpscrreg )
nkeynes@386	217	{
nkeynes@386	218	SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
nkeynes@386	219	AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
nkeynes@386	220	OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
nkeynes@386	221	store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
nkeynes@386	222	}
nkeynes@386	223	/**
nkeynes@377	224	* Push FPUL (as a 32-bit float) onto the FPU stack
nkeynes@377	225	*/
nkeynes@377	226	static inline void push_fpul( )
nkeynes@377	227	{
nkeynes@377	228	OP(0xD9); OP(0x45); OP(R_FPUL);
nkeynes@377	229	}
nkeynes@377	230
nkeynes@377	231	/**
nkeynes@377	232	* Pop FPUL (as a 32-bit float) from the FPU stack
nkeynes@377	233	*/
nkeynes@377	234	static inline void pop_fpul( )
nkeynes@377	235	{
nkeynes@377	236	OP(0xD9); OP(0x5D); OP(R_FPUL);
nkeynes@377	237	}
nkeynes@377	238
nkeynes@377	239	/**
nkeynes@375	240	* Push a 32-bit float onto the FPU stack, with bankreg previously loaded
nkeynes@375	241	* with the location of the current fp bank.
nkeynes@375	242	*/
nkeynes@374	243	static inline void push_fr( int bankreg, int frm )
nkeynes@374	244	{
nkeynes@374	245	OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
nkeynes@374	246	}
nkeynes@374	247
nkeynes@375	248	/**
nkeynes@375	249	* Pop a 32-bit float from the FPU stack and store it back into the fp bank,
nkeynes@375	250	* with bankreg previously loaded with the location of the current fp bank.
nkeynes@375	251	*/
nkeynes@374	252	static inline void pop_fr( int bankreg, int frm )
nkeynes@374	253	{
nkeynes@374	254	OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
nkeynes@374	255	}
nkeynes@374	256
nkeynes@375	257	/**
nkeynes@375	258	* Push a 64-bit double onto the FPU stack, with bankreg previously loaded
nkeynes@375	259	* with the location of the current fp bank.
nkeynes@375	260	*/
nkeynes@374	261	static inline void push_dr( int bankreg, int frm )
nkeynes@374	262	{
nkeynes@377	263	OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
nkeynes@374	264	}
nkeynes@374	265
nkeynes@374	266	static inline void pop_dr( int bankreg, int frm )
nkeynes@374	267	{
nkeynes@377	268	OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
nkeynes@374	269	}
nkeynes@374	270
nkeynes@361	271	/**
nkeynes@361	272	* Note: clobbers EAX to make the indirect call - this isn't usually
nkeynes@361	273	* a problem since the callee will usually clobber it anyway.
nkeynes@361	274	*/
nkeynes@361	275	static inline void call_func0( void *ptr )
nkeynes@361	276	{
nkeynes@361	277	load_imm32(R_EAX, (uint32_t)ptr);
nkeynes@368	278	CALL_r32(R_EAX);
nkeynes@361	279	}
nkeynes@361	280
nkeynes@361	281	static inline void call_func1( void *ptr, int arg1 )
nkeynes@361	282	{
nkeynes@361	283	PUSH_r32(arg1);
nkeynes@361	284	call_func0(ptr);
nkeynes@377	285	ADD_imm8s_r32( 4, R_ESP );
nkeynes@361	286	}
nkeynes@361	287
nkeynes@361	288	static inline void call_func2( void *ptr, int arg1, int arg2 )
nkeynes@361	289	{
nkeynes@361	290	PUSH_r32(arg2);
nkeynes@361	291	PUSH_r32(arg1);
nkeynes@361	292	call_func0(ptr);
nkeynes@377	293	ADD_imm8s_r32( 8, R_ESP );
nkeynes@375	294	}
nkeynes@375	295
nkeynes@375	296	/**
nkeynes@375	297	* Write a double (64-bit) value into memory, with the first word in arg2a, and
nkeynes@375	298	* the second in arg2b
nkeynes@375	299	* NB: 30 bytes
nkeynes@375	300	*/
nkeynes@375	301	static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375	302	{
nkeynes@375	303	ADD_imm8s_r32( 4, addr );
nkeynes@386	304	PUSH_r32(arg2b);
nkeynes@375	305	PUSH_r32(addr);
nkeynes@375	306	ADD_imm8s_r32( -4, addr );
nkeynes@386	307	PUSH_r32(arg2a);
nkeynes@375	308	PUSH_r32(addr);
nkeynes@375	309	call_func0(sh4_write_long);
nkeynes@377	310	ADD_imm8s_r32( 8, R_ESP );
nkeynes@375	311	call_func0(sh4_write_long);
nkeynes@377	312	ADD_imm8s_r32( 8, R_ESP );
nkeynes@375	313	}
nkeynes@375	314
nkeynes@375	315	/**
nkeynes@375	316	* Read a double (64-bit) value from memory, writing the first word into arg2a
nkeynes@375	317	* and the second into arg2b. The addr must not be in EAX
nkeynes@375	318	* NB: 27 bytes
nkeynes@375	319	*/
nkeynes@375	320	static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
nkeynes@375	321	{
nkeynes@375	322	PUSH_r32(addr);
nkeynes@375	323	call_func0(sh4_read_long);
nkeynes@375	324	POP_r32(addr);
nkeynes@375	325	PUSH_r32(R_EAX);
nkeynes@375	326	ADD_imm8s_r32( 4, addr );
nkeynes@375	327	PUSH_r32(addr);
nkeynes@375	328	call_func0(sh4_read_long);
nkeynes@377	329	ADD_imm8s_r32( 4, R_ESP );
nkeynes@375	330	MOV_r32_r32( R_EAX, arg2b );
nkeynes@375	331	POP_r32(arg2a);
nkeynes@361	332	}
nkeynes@361	333
nkeynes@368	334	/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@368	335	static void check_priv( )
nkeynes@368	336	{
nkeynes@368	337	if( !sh4_x86.priv_checked ) {
nkeynes@368	338	sh4_x86.priv_checked = TRUE;
nkeynes@368	339	load_spreg( R_EAX, R_SR );
nkeynes@368	340	AND_imm32_r32( SR_MD, R_EAX );
nkeynes@368	341	if( sh4_x86.in_delay_slot ) {
nkeynes@368	342	JE_exit( EXIT_SLOT_ILLEGAL );
nkeynes@368	343	} else {
nkeynes@368	344	JE_exit( EXIT_ILLEGAL );
nkeynes@368	345	}
nkeynes@368	346	}
nkeynes@368	347	}
nkeynes@368	348
nkeynes@368	349	static void check_fpuen( )
nkeynes@368	350	{
nkeynes@368	351	if( !sh4_x86.fpuen_checked ) {
nkeynes@368	352	sh4_x86.fpuen_checked = TRUE;
nkeynes@368	353	load_spreg( R_EAX, R_SR );
nkeynes@368	354	AND_imm32_r32( SR_FD, R_EAX );
nkeynes@368	355	if( sh4_x86.in_delay_slot ) {
nkeynes@368	356	JNE_exit(EXIT_SLOT_FPU_DISABLED);
nkeynes@368	357	} else {
nkeynes@368	358	JNE_exit(EXIT_FPU_DISABLED);
nkeynes@368	359	}
nkeynes@368	360	}
nkeynes@368	361	}
nkeynes@368	362
nkeynes@368	363	static void check_ralign16( int x86reg )
nkeynes@368	364	{
nkeynes@368	365	TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368	366	JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368	367	}
nkeynes@368	368
nkeynes@368	369	static void check_walign16( int x86reg )
nkeynes@368	370	{
nkeynes@368	371	TEST_imm32_r32( 0x00000001, x86reg );
nkeynes@368	372	JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368	373	}
nkeynes@368	374
nkeynes@368	375	static void check_ralign32( int x86reg )
nkeynes@368	376	{
nkeynes@368	377	TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368	378	JNE_exit(EXIT_DATA_ADDR_READ);
nkeynes@368	379	}
nkeynes@368	380	static void check_walign32( int x86reg )
nkeynes@368	381	{
nkeynes@368	382	TEST_imm32_r32( 0x00000003, x86reg );
nkeynes@368	383	JNE_exit(EXIT_DATA_ADDR_WRITE);
nkeynes@368	384	}
nkeynes@368	385
nkeynes@361	386	#define UNDEF()
nkeynes@361	387	#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@361	388	#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	389	#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	390	#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
nkeynes@361	391	#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
nkeynes@361	392	#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
nkeynes@361	393	#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
nkeynes@361	394
nkeynes@386	395	#define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
nkeynes@368	396
nkeynes@368	397
nkeynes@359	398
nkeynes@359	399	/**
nkeynes@359	400	* Emit the 'start of block' assembly. Sets up the stack frame and save
nkeynes@359	401	* SI/DI as required
nkeynes@359	402	*/
nkeynes@368	403	void sh4_translate_begin_block()
nkeynes@368	404	{
nkeynes@368	405	PUSH_r32(R_EBP);
nkeynes@359	406	/* mov &sh4r, ebp */
nkeynes@359	407	load_imm32( R_EBP, (uint32_t)&sh4r );
nkeynes@374	408	PUSH_r32(R_EDI);
nkeynes@368	409	PUSH_r32(R_ESI);
nkeynes@380	410	XOR_r32_r32(R_ESI, R_ESI);
nkeynes@368	411
nkeynes@368	412	sh4_x86.in_delay_slot = FALSE;
nkeynes@368	413	sh4_x86.priv_checked = FALSE;
nkeynes@368	414	sh4_x86.fpuen_checked = FALSE;
nkeynes@368	415	sh4_x86.backpatch_posn = 0;
nkeynes@388	416	sh4_x86.exit_code = 1;
nkeynes@368	417	}
nkeynes@359	418
nkeynes@368	419	/**
nkeynes@368	420	* Exit the block early (ie branch out), conditionally or otherwise
nkeynes@368	421	*/
nkeynes@374	422	void exit_block( )
nkeynes@368	423	{
nkeynes@374	424	store_spreg( R_EDI, REG_OFFSET(pc) );
nkeynes@368	425	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@368	426	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@368	427	MUL_r32( R_ESI );
nkeynes@368	428	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368	429	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388	430	load_imm32( R_EAX, sh4_x86.exit_code );
nkeynes@374	431	POP_r32(R_ESI);
nkeynes@374	432	POP_r32(R_EDI);
nkeynes@374	433	POP_r32(R_EBP);
nkeynes@368	434	RET();
nkeynes@359	435	}
nkeynes@359	436
nkeynes@359	437	/**
nkeynes@359	438	* Flush any open regs back to memory, restore SI/DI/, update PC, etc
nkeynes@359	439	*/
nkeynes@359	440	void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@368	441	assert( !sh4_x86.in_delay_slot ); // should never stop here
nkeynes@368	442	// Normal termination - save PC, cycle count
nkeynes@374	443	exit_block( );
nkeynes@359	444
nkeynes@388	445	if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@388	446	uint8_t *end_ptr = xlat_output;
nkeynes@388	447	// Exception termination. Jump block for various exception codes:
nkeynes@388	448	PUSH_imm32( EXC_DATA_ADDR_READ );
nkeynes@388	449	JMP_rel8( 33, target1 );
nkeynes@388	450	PUSH_imm32( EXC_DATA_ADDR_WRITE );
nkeynes@388	451	JMP_rel8( 26, target2 );
nkeynes@388	452	PUSH_imm32( EXC_ILLEGAL );
nkeynes@388	453	JMP_rel8( 19, target3 );
nkeynes@388	454	PUSH_imm32( EXC_SLOT_ILLEGAL );
nkeynes@388	455	JMP_rel8( 12, target4 );
nkeynes@388	456	PUSH_imm32( EXC_FPU_DISABLED );
nkeynes@388	457	JMP_rel8( 5, target5 );
nkeynes@388	458	PUSH_imm32( EXC_SLOT_FPU_DISABLED );
nkeynes@388	459	// target
nkeynes@388	460	JMP_TARGET(target1);
nkeynes@388	461	JMP_TARGET(target2);
nkeynes@388	462	JMP_TARGET(target3);
nkeynes@388	463	JMP_TARGET(target4);
nkeynes@388	464	JMP_TARGET(target5);
nkeynes@388	465	load_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388	466	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388	467	ADD_r32_r32( R_ESI, R_ECX );
nkeynes@388	468	store_spreg( R_ECX, REG_OFFSET(pc) );
nkeynes@388	469	MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
nkeynes@388	470	load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388	471	MUL_r32( R_ESI );
nkeynes@388	472	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@388	473	store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
nkeynes@388	474
nkeynes@388	475	load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
nkeynes@388	476	CALL_r32( R_EAX ); // 2
nkeynes@388	477	ADD_imm8s_r32( 4, R_ESP );
nkeynes@388	478	POP_r32(R_ESI);
nkeynes@388	479	POP_r32(R_EDI);
nkeynes@388	480	POP_r32(R_EBP);
nkeynes@388	481	RET();
nkeynes@368	482
nkeynes@388	483	sh4_x86_do_backpatch( end_ptr );
nkeynes@388	484	}
nkeynes@368	485
nkeynes@359	486	}
nkeynes@359	487
nkeynes@388	488
nkeynes@388	489	extern uint16_t *sh4_icache;
nkeynes@388	490	extern uint32_t sh4_icache_addr;
nkeynes@388	491
nkeynes@359	492	/**
nkeynes@359	493	* Translate a single instruction. Delayed branches are handled specially
nkeynes@359	494	* by translating both branch and delayed instruction as a single unit (as
nkeynes@359	495	*
nkeynes@359	496	*
nkeynes@359	497	* @return true if the instruction marks the end of a basic block
nkeynes@359	498	* (eg a branch or
nkeynes@359	499	*/
nkeynes@359	500	uint32_t sh4_x86_translate_instruction( uint32_t pc )
nkeynes@359	501	{
nkeynes@388	502	uint32_t ir;
nkeynes@388	503	/* Read instruction */
nkeynes@388	504	uint32_t pageaddr = pc >> 12;
nkeynes@388	505	if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
nkeynes@388	506	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388	507	} else {
nkeynes@388	508	sh4_icache = (uint16_t *)mem_get_page(pc);
nkeynes@388	509	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
nkeynes@388	510	/* If someone's actually been so daft as to try to execute out of an IO
nkeynes@388	511	* region, fallback on the full-blown memory read
nkeynes@388	512	*/
nkeynes@388	513	sh4_icache = NULL;
nkeynes@388	514	ir = sh4_read_word(pc);
nkeynes@388	515	} else {
nkeynes@388	516	sh4_icache_addr = pageaddr;
nkeynes@388	517	ir = sh4_icache[(pc&0xFFF)>>1];
nkeynes@388	518	}
nkeynes@388	519	}
nkeynes@388	520
nkeynes@359	521	switch( (ir&0xF000) >> 12 ) {
nkeynes@359	522	case 0x0:
nkeynes@359	523	switch( ir&0xF ) {
nkeynes@359	524	case 0x2:
nkeynes@359	525	switch( (ir&0x80) >> 7 ) {
nkeynes@359	526	case 0x0:
nkeynes@359	527	switch( (ir&0x70) >> 4 ) {
nkeynes@359	528	case 0x0:
nkeynes@359	529	{ /* STC SR, Rn */
nkeynes@359	530	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	531	check_priv();
nkeynes@374	532	call_func0(sh4_read_sr);
nkeynes@368	533	store_reg( R_EAX, Rn );
nkeynes@359	534	}
nkeynes@359	535	break;
nkeynes@359	536	case 0x1:
nkeynes@359	537	{ /* STC GBR, Rn */
nkeynes@359	538	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	539	load_spreg( R_EAX, R_GBR );
nkeynes@359	540	store_reg( R_EAX, Rn );
nkeynes@359	541	}
nkeynes@359	542	break;
nkeynes@359	543	case 0x2:
nkeynes@359	544	{ /* STC VBR, Rn */
nkeynes@359	545	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	546	check_priv();
nkeynes@359	547	load_spreg( R_EAX, R_VBR );
nkeynes@359	548	store_reg( R_EAX, Rn );
nkeynes@359	549	}
nkeynes@359	550	break;
nkeynes@359	551	case 0x3:
nkeynes@359	552	{ /* STC SSR, Rn */
nkeynes@359	553	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	554	check_priv();
nkeynes@359	555	load_spreg( R_EAX, R_SSR );
nkeynes@359	556	store_reg( R_EAX, Rn );
nkeynes@359	557	}
nkeynes@359	558	break;
nkeynes@359	559	case 0x4:
nkeynes@359	560	{ /* STC SPC, Rn */
nkeynes@359	561	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	562	check_priv();
nkeynes@359	563	load_spreg( R_EAX, R_SPC );
nkeynes@359	564	store_reg( R_EAX, Rn );
nkeynes@359	565	}
nkeynes@359	566	break;
nkeynes@359	567	default:
nkeynes@359	568	UNDEF();
nkeynes@359	569	break;
nkeynes@359	570	}
nkeynes@359	571	break;
nkeynes@359	572	case 0x1:
nkeynes@359	573	{ /* STC Rm_BANK, Rn */
nkeynes@359	574	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
nkeynes@386	575	check_priv();
nkeynes@374	576	load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374	577	store_reg( R_EAX, Rn );
nkeynes@359	578	}
nkeynes@359	579	break;
nkeynes@359	580	}
nkeynes@359	581	break;
nkeynes@359	582	case 0x3:
nkeynes@359	583	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	584	case 0x0:
nkeynes@359	585	{ /* BSRF Rn */
nkeynes@359	586	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	587	if( sh4_x86.in_delay_slot ) {
nkeynes@374	588	SLOTILLEGAL();
nkeynes@374	589	} else {
nkeynes@374	590	load_imm32( R_EAX, pc + 4 );
nkeynes@374	591	store_spreg( R_EAX, R_PR );
nkeynes@374	592	load_reg( R_EDI, Rn );
nkeynes@374	593	ADD_r32_r32( R_EAX, R_EDI );
nkeynes@374	594	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	595	return 0;
nkeynes@374	596	}
nkeynes@359	597	}
nkeynes@359	598	break;
nkeynes@359	599	case 0x2:
nkeynes@359	600	{ /* BRAF Rn */
nkeynes@359	601	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	602	if( sh4_x86.in_delay_slot ) {
nkeynes@374	603	SLOTILLEGAL();
nkeynes@374	604	} else {
nkeynes@374	605	load_reg( R_EDI, Rn );
nkeynes@386	606	ADD_imm32_r32( pc + 4, R_EDI );
nkeynes@374	607	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	608	return 0;
nkeynes@374	609	}
nkeynes@359	610	}
nkeynes@359	611	break;
nkeynes@359	612	case 0x8:
nkeynes@359	613	{ /* PREF @Rn */
nkeynes@359	614	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	615	load_reg( R_EAX, Rn );
nkeynes@374	616	PUSH_r32( R_EAX );
nkeynes@374	617	AND_imm32_r32( 0xFC000000, R_EAX );
nkeynes@374	618	CMP_imm32_r32( 0xE0000000, R_EAX );
nkeynes@380	619	JNE_rel8(7, end);
nkeynes@374	620	call_func0( sh4_flush_store_queue );
nkeynes@380	621	JMP_TARGET(end);
nkeynes@377	622	ADD_imm8s_r32( 4, R_ESP );
nkeynes@359	623	}
nkeynes@359	624	break;
nkeynes@359	625	case 0x9:
nkeynes@359	626	{ /* OCBI @Rn */
nkeynes@359	627	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	628	}
nkeynes@359	629	break;
nkeynes@359	630	case 0xA:
nkeynes@359	631	{ /* OCBP @Rn */
nkeynes@359	632	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	633	}
nkeynes@359	634	break;
nkeynes@359	635	case 0xB:
nkeynes@359	636	{ /* OCBWB @Rn */
nkeynes@359	637	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	638	}
nkeynes@359	639	break;
nkeynes@359	640	case 0xC:
nkeynes@359	641	{ /* MOVCA.L R0, @Rn */
nkeynes@359	642	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@361	643	load_reg( R_EAX, 0 );
nkeynes@361	644	load_reg( R_ECX, Rn );
nkeynes@374	645	check_walign32( R_ECX );
nkeynes@361	646	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	647	}
nkeynes@359	648	break;
nkeynes@359	649	default:
nkeynes@359	650	UNDEF();
nkeynes@359	651	break;
nkeynes@359	652	}
nkeynes@359	653	break;
nkeynes@359	654	case 0x4:
nkeynes@359	655	{ /* MOV.B Rm, @(R0, Rn) */
nkeynes@359	656	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	657	load_reg( R_EAX, 0 );
nkeynes@359	658	load_reg( R_ECX, Rn );
nkeynes@359	659	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	660	load_reg( R_EAX, Rm );
nkeynes@359	661	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	662	}
nkeynes@359	663	break;
nkeynes@359	664	case 0x5:
nkeynes@359	665	{ /* MOV.W Rm, @(R0, Rn) */
nkeynes@359	666	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	667	load_reg( R_EAX, 0 );
nkeynes@361	668	load_reg( R_ECX, Rn );
nkeynes@361	669	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374	670	check_walign16( R_ECX );
nkeynes@361	671	load_reg( R_EAX, Rm );
nkeynes@361	672	MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359	673	}
nkeynes@359	674	break;
nkeynes@359	675	case 0x6:
nkeynes@359	676	{ /* MOV.L Rm, @(R0, Rn) */
nkeynes@359	677	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	678	load_reg( R_EAX, 0 );
nkeynes@361	679	load_reg( R_ECX, Rn );
nkeynes@361	680	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374	681	check_walign32( R_ECX );
nkeynes@361	682	load_reg( R_EAX, Rm );
nkeynes@361	683	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	684	}
nkeynes@359	685	break;
nkeynes@359	686	case 0x7:
nkeynes@359	687	{ /* MUL.L Rm, Rn */
nkeynes@359	688	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	689	load_reg( R_EAX, Rm );
nkeynes@361	690	load_reg( R_ECX, Rn );
nkeynes@361	691	MUL_r32( R_ECX );
nkeynes@361	692	store_spreg( R_EAX, R_MACL );
nkeynes@359	693	}
nkeynes@359	694	break;
nkeynes@359	695	case 0x8:
nkeynes@359	696	switch( (ir&0xFF0) >> 4 ) {
nkeynes@359	697	case 0x0:
nkeynes@359	698	{ /* CLRT */
nkeynes@374	699	CLC();
nkeynes@374	700	SETC_t();
nkeynes@359	701	}
nkeynes@359	702	break;
nkeynes@359	703	case 0x1:
nkeynes@359	704	{ /* SETT */
nkeynes@374	705	STC();
nkeynes@374	706	SETC_t();
nkeynes@359	707	}
nkeynes@359	708	break;
nkeynes@359	709	case 0x2:
nkeynes@359	710	{ /* CLRMAC */
nkeynes@374	711	XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374	712	store_spreg( R_EAX, R_MACL );
nkeynes@374	713	store_spreg( R_EAX, R_MACH );
nkeynes@359	714	}
nkeynes@359	715	break;
nkeynes@359	716	case 0x3:
nkeynes@359	717	{ /* LDTLB */
nkeynes@359	718	}
nkeynes@359	719	break;
nkeynes@359	720	case 0x4:
nkeynes@359	721	{ /* CLRS */
nkeynes@374	722	CLC();
nkeynes@374	723	SETC_sh4r(R_S);
nkeynes@359	724	}
nkeynes@359	725	break;
nkeynes@359	726	case 0x5:
nkeynes@359	727	{ /* SETS */
nkeynes@374	728	STC();
nkeynes@374	729	SETC_sh4r(R_S);
nkeynes@359	730	}
nkeynes@359	731	break;
nkeynes@359	732	default:
nkeynes@359	733	UNDEF();
nkeynes@359	734	break;
nkeynes@359	735	}
nkeynes@359	736	break;
nkeynes@359	737	case 0x9:
nkeynes@359	738	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	739	case 0x0:
nkeynes@359	740	{ /* NOP */
nkeynes@359	741	/* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@359	742	}
nkeynes@359	743	break;
nkeynes@359	744	case 0x1:
nkeynes@359	745	{ /* DIV0U */
nkeynes@361	746	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361	747	store_spreg( R_EAX, R_Q );
nkeynes@361	748	store_spreg( R_EAX, R_M );
nkeynes@361	749	store_spreg( R_EAX, R_T );
nkeynes@359	750	}
nkeynes@359	751	break;
nkeynes@359	752	case 0x2:
nkeynes@359	753	{ /* MOVT Rn */
nkeynes@359	754	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	755	load_spreg( R_EAX, R_T );
nkeynes@359	756	store_reg( R_EAX, Rn );
nkeynes@359	757	}
nkeynes@359	758	break;
nkeynes@359	759	default:
nkeynes@359	760	UNDEF();
nkeynes@359	761	break;
nkeynes@359	762	}
nkeynes@359	763	break;
nkeynes@359	764	case 0xA:
nkeynes@359	765	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	766	case 0x0:
nkeynes@359	767	{ /* STS MACH, Rn */
nkeynes@359	768	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	769	load_spreg( R_EAX, R_MACH );
nkeynes@359	770	store_reg( R_EAX, Rn );
nkeynes@359	771	}
nkeynes@359	772	break;
nkeynes@359	773	case 0x1:
nkeynes@359	774	{ /* STS MACL, Rn */
nkeynes@359	775	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	776	load_spreg( R_EAX, R_MACL );
nkeynes@359	777	store_reg( R_EAX, Rn );
nkeynes@359	778	}
nkeynes@359	779	break;
nkeynes@359	780	case 0x2:
nkeynes@359	781	{ /* STS PR, Rn */
nkeynes@359	782	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	783	load_spreg( R_EAX, R_PR );
nkeynes@359	784	store_reg( R_EAX, Rn );
nkeynes@359	785	}
nkeynes@359	786	break;
nkeynes@359	787	case 0x3:
nkeynes@359	788	{ /* STC SGR, Rn */
nkeynes@359	789	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	790	check_priv();
nkeynes@359	791	load_spreg( R_EAX, R_SGR );
nkeynes@359	792	store_reg( R_EAX, Rn );
nkeynes@359	793	}
nkeynes@359	794	break;
nkeynes@359	795	case 0x5:
nkeynes@359	796	{ /* STS FPUL, Rn */
nkeynes@359	797	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	798	load_spreg( R_EAX, R_FPUL );
nkeynes@359	799	store_reg( R_EAX, Rn );
nkeynes@359	800	}
nkeynes@359	801	break;
nkeynes@359	802	case 0x6:
nkeynes@359	803	{ /* STS FPSCR, Rn */
nkeynes@359	804	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	805	load_spreg( R_EAX, R_FPSCR );
nkeynes@359	806	store_reg( R_EAX, Rn );
nkeynes@359	807	}
nkeynes@359	808	break;
nkeynes@359	809	case 0xF:
nkeynes@359	810	{ /* STC DBR, Rn */
nkeynes@359	811	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	812	check_priv();
nkeynes@359	813	load_spreg( R_EAX, R_DBR );
nkeynes@359	814	store_reg( R_EAX, Rn );
nkeynes@359	815	}
nkeynes@359	816	break;
nkeynes@359	817	default:
nkeynes@359	818	UNDEF();
nkeynes@359	819	break;
nkeynes@359	820	}
nkeynes@359	821	break;
nkeynes@359	822	case 0xB:
nkeynes@359	823	switch( (ir&0xFF0) >> 4 ) {
nkeynes@359	824	case 0x0:
nkeynes@359	825	{ /* RTS */
nkeynes@374	826	if( sh4_x86.in_delay_slot ) {
nkeynes@374	827	SLOTILLEGAL();
nkeynes@374	828	} else {
nkeynes@374	829	load_spreg( R_EDI, R_PR );
nkeynes@374	830	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	831	return 0;
nkeynes@374	832	}
nkeynes@359	833	}
nkeynes@359	834	break;
nkeynes@359	835	case 0x1:
nkeynes@359	836	{ /* SLEEP */
nkeynes@388	837	check_priv();
nkeynes@388	838	call_func0( sh4_sleep );
nkeynes@388	839	sh4_x86.exit_code = 0;
nkeynes@388	840	sh4_x86.in_delay_slot = FALSE;
nkeynes@388	841	return 1;
nkeynes@359	842	}
nkeynes@359	843	break;
nkeynes@359	844	case 0x2:
nkeynes@359	845	{ /* RTE */
nkeynes@374	846	check_priv();
nkeynes@374	847	if( sh4_x86.in_delay_slot ) {
nkeynes@374	848	SLOTILLEGAL();
nkeynes@374	849	} else {
nkeynes@386	850	load_spreg( R_EDI, R_SPC );
nkeynes@374	851	load_spreg( R_EAX, R_SSR );
nkeynes@374	852	call_func1( sh4_write_sr, R_EAX );
nkeynes@374	853	sh4_x86.in_delay_slot = TRUE;
nkeynes@377	854	sh4_x86.priv_checked = FALSE;
nkeynes@377	855	sh4_x86.fpuen_checked = FALSE;
nkeynes@374	856	return 0;
nkeynes@374	857	}
nkeynes@359	858	}
nkeynes@359	859	break;
nkeynes@359	860	default:
nkeynes@359	861	UNDEF();
nkeynes@359	862	break;
nkeynes@359	863	}
nkeynes@359	864	break;
nkeynes@359	865	case 0xC:
nkeynes@359	866	{ /* MOV.B @(R0, Rm), Rn */
nkeynes@359	867	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	868	load_reg( R_EAX, 0 );
nkeynes@359	869	load_reg( R_ECX, Rm );
nkeynes@359	870	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	871	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359	872	store_reg( R_EAX, Rn );
nkeynes@359	873	}
nkeynes@359	874	break;
nkeynes@359	875	case 0xD:
nkeynes@359	876	{ /* MOV.W @(R0, Rm), Rn */
nkeynes@359	877	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	878	load_reg( R_EAX, 0 );
nkeynes@361	879	load_reg( R_ECX, Rm );
nkeynes@361	880	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374	881	check_ralign16( R_ECX );
nkeynes@361	882	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361	883	store_reg( R_EAX, Rn );
nkeynes@359	884	}
nkeynes@359	885	break;
nkeynes@359	886	case 0xE:
nkeynes@359	887	{ /* MOV.L @(R0, Rm), Rn */
nkeynes@359	888	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	889	load_reg( R_EAX, 0 );
nkeynes@361	890	load_reg( R_ECX, Rm );
nkeynes@361	891	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@374	892	check_ralign32( R_ECX );
nkeynes@361	893	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361	894	store_reg( R_EAX, Rn );
nkeynes@359	895	}
nkeynes@359	896	break;
nkeynes@359	897	case 0xF:
nkeynes@359	898	{ /* MAC.L @Rm+, @Rn+ */
nkeynes@359	899	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@386	900	load_reg( R_ECX, Rm );
nkeynes@386	901	check_ralign32( R_ECX );
nkeynes@386	902	load_reg( R_ECX, Rn );
nkeynes@386	903	check_ralign32( R_ECX );
nkeynes@386	904	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@386	905	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386	906	PUSH_r32( R_EAX );
nkeynes@386	907	load_reg( R_ECX, Rm );
nkeynes@386	908	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386	909	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386	910	POP_r32( R_ECX );
nkeynes@386	911	IMUL_r32( R_ECX );
nkeynes@386	912	ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386	913	ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386	914
nkeynes@386	915	load_spreg( R_ECX, R_S );
nkeynes@386	916	TEST_r32_r32(R_ECX, R_ECX);
nkeynes@386	917	JE_rel8( 7, nosat );
nkeynes@386	918	call_func0( signsat48 );
nkeynes@386	919	JMP_TARGET( nosat );
nkeynes@359	920	}
nkeynes@359	921	break;
nkeynes@359	922	default:
nkeynes@359	923	UNDEF();
nkeynes@359	924	break;
nkeynes@359	925	}
nkeynes@359	926	break;
nkeynes@359	927	case 0x1:
nkeynes@359	928	{ /* MOV.L Rm, @(disp, Rn) */
nkeynes@359	929	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
nkeynes@361	930	load_reg( R_ECX, Rn );
nkeynes@361	931	load_reg( R_EAX, Rm );
nkeynes@361	932	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	933	check_walign32( R_ECX );
nkeynes@361	934	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	935	}
nkeynes@359	936	break;
nkeynes@359	937	case 0x2:
nkeynes@359	938	switch( ir&0xF ) {
nkeynes@359	939	case 0x0:
nkeynes@359	940	{ /* MOV.B Rm, @Rn */
nkeynes@359	941	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	942	load_reg( R_EAX, Rm );
nkeynes@359	943	load_reg( R_ECX, Rn );
nkeynes@359	944	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	945	}
nkeynes@359	946	break;
nkeynes@359	947	case 0x1:
nkeynes@359	948	{ /* MOV.W Rm, @Rn */
nkeynes@359	949	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	950	load_reg( R_ECX, Rn );
nkeynes@374	951	check_walign16( R_ECX );
nkeynes@386	952	load_reg( R_EAX, Rm );
nkeynes@386	953	MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359	954	}
nkeynes@359	955	break;
nkeynes@359	956	case 0x2:
nkeynes@359	957	{ /* MOV.L Rm, @Rn */
nkeynes@359	958	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	959	load_reg( R_EAX, Rm );
nkeynes@361	960	load_reg( R_ECX, Rn );
nkeynes@374	961	check_walign32(R_ECX);
nkeynes@361	962	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	963	}
nkeynes@359	964	break;
nkeynes@359	965	case 0x4:
nkeynes@359	966	{ /* MOV.B Rm, @-Rn */
nkeynes@359	967	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	968	load_reg( R_EAX, Rm );
nkeynes@359	969	load_reg( R_ECX, Rn );
nkeynes@386	970	ADD_imm8s_r32( -1, R_ECX );
nkeynes@359	971	store_reg( R_ECX, Rn );
nkeynes@359	972	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	973	}
nkeynes@359	974	break;
nkeynes@359	975	case 0x5:
nkeynes@359	976	{ /* MOV.W Rm, @-Rn */
nkeynes@359	977	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	978	load_reg( R_ECX, Rn );
nkeynes@374	979	check_walign16( R_ECX );
nkeynes@361	980	load_reg( R_EAX, Rm );
nkeynes@361	981	ADD_imm8s_r32( -2, R_ECX );
nkeynes@386	982	store_reg( R_ECX, Rn );
nkeynes@361	983	MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359	984	}
nkeynes@359	985	break;
nkeynes@359	986	case 0x6:
nkeynes@359	987	{ /* MOV.L Rm, @-Rn */
nkeynes@359	988	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	989	load_reg( R_EAX, Rm );
nkeynes@361	990	load_reg( R_ECX, Rn );
nkeynes@374	991	check_walign32( R_ECX );
nkeynes@361	992	ADD_imm8s_r32( -4, R_ECX );
nkeynes@361	993	store_reg( R_ECX, Rn );
nkeynes@361	994	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	995	}
nkeynes@359	996	break;
nkeynes@359	997	case 0x7:
nkeynes@359	998	{ /* DIV0S Rm, Rn */
nkeynes@359	999	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1000	load_reg( R_EAX, Rm );
nkeynes@386	1001	load_reg( R_ECX, Rn );
nkeynes@361	1002	SHR_imm8_r32( 31, R_EAX );
nkeynes@361	1003	SHR_imm8_r32( 31, R_ECX );
nkeynes@361	1004	store_spreg( R_EAX, R_M );
nkeynes@361	1005	store_spreg( R_ECX, R_Q );
nkeynes@361	1006	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386	1007	SETNE_t();
nkeynes@359	1008	}
nkeynes@359	1009	break;
nkeynes@359	1010	case 0x8:
nkeynes@359	1011	{ /* TST Rm, Rn */
nkeynes@359	1012	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1013	load_reg( R_EAX, Rm );
nkeynes@361	1014	load_reg( R_ECX, Rn );
nkeynes@361	1015	TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361	1016	SETE_t();
nkeynes@359	1017	}
nkeynes@359	1018	break;
nkeynes@359	1019	case 0x9:
nkeynes@359	1020	{ /* AND Rm, Rn */
nkeynes@359	1021	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1022	load_reg( R_EAX, Rm );
nkeynes@359	1023	load_reg( R_ECX, Rn );
nkeynes@359	1024	AND_r32_r32( R_EAX, R_ECX );
nkeynes@359	1025	store_reg( R_ECX, Rn );
nkeynes@359	1026	}
nkeynes@359	1027	break;
nkeynes@359	1028	case 0xA:
nkeynes@359	1029	{ /* XOR Rm, Rn */
nkeynes@359	1030	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1031	load_reg( R_EAX, Rm );
nkeynes@359	1032	load_reg( R_ECX, Rn );
nkeynes@359	1033	XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1034	store_reg( R_ECX, Rn );
nkeynes@359	1035	}
nkeynes@359	1036	break;
nkeynes@359	1037	case 0xB:
nkeynes@359	1038	{ /* OR Rm, Rn */
nkeynes@359	1039	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1040	load_reg( R_EAX, Rm );
nkeynes@359	1041	load_reg( R_ECX, Rn );
nkeynes@359	1042	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1043	store_reg( R_ECX, Rn );
nkeynes@359	1044	}
nkeynes@359	1045	break;
nkeynes@359	1046	case 0xC:
nkeynes@359	1047	{ /* CMP/STR Rm, Rn */
nkeynes@359	1048	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@368	1049	load_reg( R_EAX, Rm );
nkeynes@368	1050	load_reg( R_ECX, Rn );
nkeynes@368	1051	XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368	1052	TEST_r8_r8( R_AL, R_AL );
nkeynes@380	1053	JE_rel8(13, target1);
nkeynes@368	1054	TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380	1055	JE_rel8(9, target2);
nkeynes@368	1056	SHR_imm8_r32( 16, R_EAX ); // 3
nkeynes@368	1057	TEST_r8_r8( R_AL, R_AL ); // 2
nkeynes@380	1058	JE_rel8(2, target3);
nkeynes@368	1059	TEST_r8_r8( R_AH, R_AH ); // 2
nkeynes@380	1060	JMP_TARGET(target1);
nkeynes@380	1061	JMP_TARGET(target2);
nkeynes@380	1062	JMP_TARGET(target3);
nkeynes@368	1063	SETE_t();
nkeynes@359	1064	}
nkeynes@359	1065	break;
nkeynes@359	1066	case 0xD:
nkeynes@359	1067	{ /* XTRCT Rm, Rn */
nkeynes@359	1068	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1069	load_reg( R_EAX, Rm );
nkeynes@361	1070	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361	1071	SHR_imm8_r32( 16, R_EAX );
nkeynes@361	1072	SHL_imm8_r32( 16, R_ECX );
nkeynes@361	1073	OR_r32_r32( R_EAX, R_ECX );
nkeynes@361	1074	store_reg( R_ECX, Rn );
nkeynes@359	1075	}
nkeynes@359	1076	break;
nkeynes@359	1077	case 0xE:
nkeynes@359	1078	{ /* MULU.W Rm, Rn */
nkeynes@359	1079	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@374	1080	load_reg16u( R_EAX, Rm );
nkeynes@374	1081	load_reg16u( R_ECX, Rn );
nkeynes@374	1082	MUL_r32( R_ECX );
nkeynes@374	1083	store_spreg( R_EAX, R_MACL );
nkeynes@359	1084	}
nkeynes@359	1085	break;
nkeynes@359	1086	case 0xF:
nkeynes@359	1087	{ /* MULS.W Rm, Rn */
nkeynes@359	1088	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@374	1089	load_reg16s( R_EAX, Rm );
nkeynes@374	1090	load_reg16s( R_ECX, Rn );
nkeynes@374	1091	MUL_r32( R_ECX );
nkeynes@374	1092	store_spreg( R_EAX, R_MACL );
nkeynes@359	1093	}
nkeynes@359	1094	break;
nkeynes@359	1095	default:
nkeynes@359	1096	UNDEF();
nkeynes@359	1097	break;
nkeynes@359	1098	}
nkeynes@359	1099	break;
nkeynes@359	1100	case 0x3:
nkeynes@359	1101	switch( ir&0xF ) {
nkeynes@359	1102	case 0x0:
nkeynes@359	1103	{ /* CMP/EQ Rm, Rn */
nkeynes@359	1104	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1105	load_reg( R_EAX, Rm );
nkeynes@359	1106	load_reg( R_ECX, Rn );
nkeynes@359	1107	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1108	SETE_t();
nkeynes@359	1109	}
nkeynes@359	1110	break;
nkeynes@359	1111	case 0x2:
nkeynes@359	1112	{ /* CMP/HS Rm, Rn */
nkeynes@359	1113	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1114	load_reg( R_EAX, Rm );
nkeynes@359	1115	load_reg( R_ECX, Rn );
nkeynes@359	1116	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1117	SETAE_t();
nkeynes@359	1118	}
nkeynes@359	1119	break;
nkeynes@359	1120	case 0x3:
nkeynes@359	1121	{ /* CMP/GE Rm, Rn */
nkeynes@359	1122	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1123	load_reg( R_EAX, Rm );
nkeynes@359	1124	load_reg( R_ECX, Rn );
nkeynes@359	1125	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1126	SETGE_t();
nkeynes@359	1127	}
nkeynes@359	1128	break;
nkeynes@359	1129	case 0x4:
nkeynes@359	1130	{ /* DIV1 Rm, Rn */
nkeynes@359	1131	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@386	1132	load_spreg( R_ECX, R_M );
nkeynes@386	1133	load_reg( R_EAX, Rn );
nkeynes@374	1134	LDC_t();
nkeynes@386	1135	RCL1_r32( R_EAX );
nkeynes@386	1136	SETC_r8( R_DL ); // Q'
nkeynes@386	1137	CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@386	1138	JE_rel8(5, mqequal);
nkeynes@386	1139	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386	1140	JMP_rel8(3, end);
nkeynes@380	1141	JMP_TARGET(mqequal);
nkeynes@386	1142	SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386	1143	JMP_TARGET(end);
nkeynes@386	1144	store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386	1145	SETC_r8(R_AL); // tmp1
nkeynes@386	1146	XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386	1147	XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386	1148	store_spreg( R_ECX, R_Q );
nkeynes@386	1149	XOR_imm8s_r32( 1, R_AL ); // T = !Q'
nkeynes@386	1150	MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386	1151	store_spreg( R_EAX, R_T );
nkeynes@359	1152	}
nkeynes@359	1153	break;
nkeynes@359	1154	case 0x5:
nkeynes@359	1155	{ /* DMULU.L Rm, Rn */
nkeynes@359	1156	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1157	load_reg( R_EAX, Rm );
nkeynes@361	1158	load_reg( R_ECX, Rn );
nkeynes@361	1159	MUL_r32(R_ECX);
nkeynes@361	1160	store_spreg( R_EDX, R_MACH );
nkeynes@361	1161	store_spreg( R_EAX, R_MACL );
nkeynes@359	1162	}
nkeynes@359	1163	break;
nkeynes@359	1164	case 0x6:
nkeynes@359	1165	{ /* CMP/HI Rm, Rn */
nkeynes@359	1166	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1167	load_reg( R_EAX, Rm );
nkeynes@359	1168	load_reg( R_ECX, Rn );
nkeynes@359	1169	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1170	SETA_t();
nkeynes@359	1171	}
nkeynes@359	1172	break;
nkeynes@359	1173	case 0x7:
nkeynes@359	1174	{ /* CMP/GT Rm, Rn */
nkeynes@359	1175	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1176	load_reg( R_EAX, Rm );
nkeynes@359	1177	load_reg( R_ECX, Rn );
nkeynes@359	1178	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	1179	SETG_t();
nkeynes@359	1180	}
nkeynes@359	1181	break;
nkeynes@359	1182	case 0x8:
nkeynes@359	1183	{ /* SUB Rm, Rn */
nkeynes@359	1184	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1185	load_reg( R_EAX, Rm );
nkeynes@359	1186	load_reg( R_ECX, Rn );
nkeynes@359	1187	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1188	store_reg( R_ECX, Rn );
nkeynes@359	1189	}
nkeynes@359	1190	break;
nkeynes@359	1191	case 0xA:
nkeynes@359	1192	{ /* SUBC Rm, Rn */
nkeynes@359	1193	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1194	load_reg( R_EAX, Rm );
nkeynes@359	1195	load_reg( R_ECX, Rn );
nkeynes@359	1196	LDC_t();
nkeynes@359	1197	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1198	store_reg( R_ECX, Rn );
nkeynes@359	1199	}
nkeynes@359	1200	break;
nkeynes@359	1201	case 0xB:
nkeynes@359	1202	{ /* SUBV Rm, Rn */
nkeynes@359	1203	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1204	load_reg( R_EAX, Rm );
nkeynes@359	1205	load_reg( R_ECX, Rn );
nkeynes@359	1206	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1207	store_reg( R_ECX, Rn );
nkeynes@359	1208	SETO_t();
nkeynes@359	1209	}
nkeynes@359	1210	break;
nkeynes@359	1211	case 0xC:
nkeynes@359	1212	{ /* ADD Rm, Rn */
nkeynes@359	1213	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1214	load_reg( R_EAX, Rm );
nkeynes@359	1215	load_reg( R_ECX, Rn );
nkeynes@359	1216	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	1217	store_reg( R_ECX, Rn );
nkeynes@359	1218	}
nkeynes@359	1219	break;
nkeynes@359	1220	case 0xD:
nkeynes@359	1221	{ /* DMULS.L Rm, Rn */
nkeynes@359	1222	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	1223	load_reg( R_EAX, Rm );
nkeynes@361	1224	load_reg( R_ECX, Rn );
nkeynes@361	1225	IMUL_r32(R_ECX);
nkeynes@361	1226	store_spreg( R_EDX, R_MACH );
nkeynes@361	1227	store_spreg( R_EAX, R_MACL );
nkeynes@359	1228	}
nkeynes@359	1229	break;
nkeynes@359	1230	case 0xE:
nkeynes@359	1231	{ /* ADDC Rm, Rn */
nkeynes@359	1232	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1233	load_reg( R_EAX, Rm );
nkeynes@359	1234	load_reg( R_ECX, Rn );
nkeynes@359	1235	LDC_t();
nkeynes@359	1236	ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359	1237	store_reg( R_ECX, Rn );
nkeynes@359	1238	SETC_t();
nkeynes@359	1239	}
nkeynes@359	1240	break;
nkeynes@359	1241	case 0xF:
nkeynes@359	1242	{ /* ADDV Rm, Rn */
nkeynes@359	1243	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1244	load_reg( R_EAX, Rm );
nkeynes@359	1245	load_reg( R_ECX, Rn );
nkeynes@359	1246	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	1247	store_reg( R_ECX, Rn );
nkeynes@359	1248	SETO_t();
nkeynes@359	1249	}
nkeynes@359	1250	break;
nkeynes@359	1251	default:
nkeynes@359	1252	UNDEF();
nkeynes@359	1253	break;
nkeynes@359	1254	}
nkeynes@359	1255	break;
nkeynes@359	1256	case 0x4:
nkeynes@359	1257	switch( ir&0xF ) {
nkeynes@359	1258	case 0x0:
nkeynes@359	1259	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1260	case 0x0:
nkeynes@359	1261	{ /* SHLL Rn */
nkeynes@359	1262	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1263	load_reg( R_EAX, Rn );
nkeynes@359	1264	SHL1_r32( R_EAX );
nkeynes@359	1265	store_reg( R_EAX, Rn );
nkeynes@359	1266	}
nkeynes@359	1267	break;
nkeynes@359	1268	case 0x1:
nkeynes@359	1269	{ /* DT Rn */
nkeynes@359	1270	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1271	load_reg( R_EAX, Rn );
nkeynes@386	1272	ADD_imm8s_r32( -1, R_EAX );
nkeynes@359	1273	store_reg( R_EAX, Rn );
nkeynes@359	1274	SETE_t();
nkeynes@359	1275	}
nkeynes@359	1276	break;
nkeynes@359	1277	case 0x2:
nkeynes@359	1278	{ /* SHAL Rn */
nkeynes@359	1279	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1280	load_reg( R_EAX, Rn );
nkeynes@359	1281	SHL1_r32( R_EAX );
nkeynes@359	1282	store_reg( R_EAX, Rn );
nkeynes@359	1283	}
nkeynes@359	1284	break;
nkeynes@359	1285	default:
nkeynes@359	1286	UNDEF();
nkeynes@359	1287	break;
nkeynes@359	1288	}
nkeynes@359	1289	break;
nkeynes@359	1290	case 0x1:
nkeynes@359	1291	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1292	case 0x0:
nkeynes@359	1293	{ /* SHLR Rn */
nkeynes@359	1294	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1295	load_reg( R_EAX, Rn );
nkeynes@359	1296	SHR1_r32( R_EAX );
nkeynes@359	1297	store_reg( R_EAX, Rn );
nkeynes@359	1298	}
nkeynes@359	1299	break;
nkeynes@359	1300	case 0x1:
nkeynes@359	1301	{ /* CMP/PZ Rn */
nkeynes@359	1302	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1303	load_reg( R_EAX, Rn );
nkeynes@359	1304	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	1305	SETGE_t();
nkeynes@359	1306	}
nkeynes@359	1307	break;
nkeynes@359	1308	case 0x2:
nkeynes@359	1309	{ /* SHAR Rn */
nkeynes@359	1310	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1311	load_reg( R_EAX, Rn );
nkeynes@359	1312	SAR1_r32( R_EAX );
nkeynes@359	1313	store_reg( R_EAX, Rn );
nkeynes@359	1314	}
nkeynes@359	1315	break;
nkeynes@359	1316	default:
nkeynes@359	1317	UNDEF();
nkeynes@359	1318	break;
nkeynes@359	1319	}
nkeynes@359	1320	break;
nkeynes@359	1321	case 0x2:
nkeynes@359	1322	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1323	case 0x0:
nkeynes@359	1324	{ /* STS.L MACH, @-Rn */
nkeynes@359	1325	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1326	load_reg( R_ECX, Rn );
nkeynes@386	1327	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1328	store_reg( R_ECX, Rn );
nkeynes@359	1329	load_spreg( R_EAX, R_MACH );
nkeynes@359	1330	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1331	}
nkeynes@359	1332	break;
nkeynes@359	1333	case 0x1:
nkeynes@359	1334	{ /* STS.L MACL, @-Rn */
nkeynes@359	1335	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1336	load_reg( R_ECX, Rn );
nkeynes@386	1337	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1338	store_reg( R_ECX, Rn );
nkeynes@359	1339	load_spreg( R_EAX, R_MACL );
nkeynes@359	1340	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1341	}
nkeynes@359	1342	break;
nkeynes@359	1343	case 0x2:
nkeynes@359	1344	{ /* STS.L PR, @-Rn */
nkeynes@359	1345	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1346	load_reg( R_ECX, Rn );
nkeynes@386	1347	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1348	store_reg( R_ECX, Rn );
nkeynes@359	1349	load_spreg( R_EAX, R_PR );
nkeynes@359	1350	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1351	}
nkeynes@359	1352	break;
nkeynes@359	1353	case 0x3:
nkeynes@359	1354	{ /* STC.L SGR, @-Rn */
nkeynes@359	1355	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1356	check_priv();
nkeynes@359	1357	load_reg( R_ECX, Rn );
nkeynes@386	1358	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1359	store_reg( R_ECX, Rn );
nkeynes@359	1360	load_spreg( R_EAX, R_SGR );
nkeynes@359	1361	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1362	}
nkeynes@359	1363	break;
nkeynes@359	1364	case 0x5:
nkeynes@359	1365	{ /* STS.L FPUL, @-Rn */
nkeynes@359	1366	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1367	load_reg( R_ECX, Rn );
nkeynes@386	1368	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1369	store_reg( R_ECX, Rn );
nkeynes@359	1370	load_spreg( R_EAX, R_FPUL );
nkeynes@359	1371	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1372	}
nkeynes@359	1373	break;
nkeynes@359	1374	case 0x6:
nkeynes@359	1375	{ /* STS.L FPSCR, @-Rn */
nkeynes@359	1376	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1377	load_reg( R_ECX, Rn );
nkeynes@386	1378	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1379	store_reg( R_ECX, Rn );
nkeynes@359	1380	load_spreg( R_EAX, R_FPSCR );
nkeynes@359	1381	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1382	}
nkeynes@359	1383	break;
nkeynes@359	1384	case 0xF:
nkeynes@359	1385	{ /* STC.L DBR, @-Rn */
nkeynes@359	1386	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1387	check_priv();
nkeynes@359	1388	load_reg( R_ECX, Rn );
nkeynes@386	1389	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1390	store_reg( R_ECX, Rn );
nkeynes@359	1391	load_spreg( R_EAX, R_DBR );
nkeynes@359	1392	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1393	}
nkeynes@359	1394	break;
nkeynes@359	1395	default:
nkeynes@359	1396	UNDEF();
nkeynes@359	1397	break;
nkeynes@359	1398	}
nkeynes@359	1399	break;
nkeynes@359	1400	case 0x3:
nkeynes@359	1401	switch( (ir&0x80) >> 7 ) {
nkeynes@359	1402	case 0x0:
nkeynes@359	1403	switch( (ir&0x70) >> 4 ) {
nkeynes@359	1404	case 0x0:
nkeynes@359	1405	{ /* STC.L SR, @-Rn */
nkeynes@359	1406	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1407	check_priv();
nkeynes@374	1408	load_reg( R_ECX, Rn );
nkeynes@386	1409	ADD_imm8s_r32( -4, R_ECX );
nkeynes@374	1410	store_reg( R_ECX, Rn );
nkeynes@374	1411	call_func0( sh4_read_sr );
nkeynes@374	1412	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1413	}
nkeynes@359	1414	break;
nkeynes@359	1415	case 0x1:
nkeynes@359	1416	{ /* STC.L GBR, @-Rn */
nkeynes@359	1417	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1418	load_reg( R_ECX, Rn );
nkeynes@386	1419	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1420	store_reg( R_ECX, Rn );
nkeynes@359	1421	load_spreg( R_EAX, R_GBR );
nkeynes@359	1422	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1423	}
nkeynes@359	1424	break;
nkeynes@359	1425	case 0x2:
nkeynes@359	1426	{ /* STC.L VBR, @-Rn */
nkeynes@359	1427	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1428	check_priv();
nkeynes@359	1429	load_reg( R_ECX, Rn );
nkeynes@386	1430	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1431	store_reg( R_ECX, Rn );
nkeynes@359	1432	load_spreg( R_EAX, R_VBR );
nkeynes@359	1433	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1434	}
nkeynes@359	1435	break;
nkeynes@359	1436	case 0x3:
nkeynes@359	1437	{ /* STC.L SSR, @-Rn */
nkeynes@359	1438	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1439	check_priv();
nkeynes@359	1440	load_reg( R_ECX, Rn );
nkeynes@386	1441	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1442	store_reg( R_ECX, Rn );
nkeynes@359	1443	load_spreg( R_EAX, R_SSR );
nkeynes@359	1444	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1445	}
nkeynes@359	1446	break;
nkeynes@359	1447	case 0x4:
nkeynes@359	1448	{ /* STC.L SPC, @-Rn */
nkeynes@359	1449	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@386	1450	check_priv();
nkeynes@359	1451	load_reg( R_ECX, Rn );
nkeynes@386	1452	ADD_imm8s_r32( -4, R_ECX );
nkeynes@359	1453	store_reg( R_ECX, Rn );
nkeynes@359	1454	load_spreg( R_EAX, R_SPC );
nkeynes@359	1455	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1456	}
nkeynes@359	1457	break;
nkeynes@359	1458	default:
nkeynes@359	1459	UNDEF();
nkeynes@359	1460	break;
nkeynes@359	1461	}
nkeynes@359	1462	break;
nkeynes@359	1463	case 0x1:
nkeynes@359	1464	{ /* STC.L Rm_BANK, @-Rn */
nkeynes@359	1465	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
nkeynes@386	1466	check_priv();
nkeynes@374	1467	load_reg( R_ECX, Rn );
nkeynes@386	1468	ADD_imm8s_r32( -4, R_ECX );
nkeynes@374	1469	store_reg( R_ECX, Rn );
nkeynes@374	1470	load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374	1471	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	1472	}
nkeynes@359	1473	break;
nkeynes@359	1474	}
nkeynes@359	1475	break;
nkeynes@359	1476	case 0x4:
nkeynes@359	1477	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1478	case 0x0:
nkeynes@359	1479	{ /* ROTL Rn */
nkeynes@359	1480	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1481	load_reg( R_EAX, Rn );
nkeynes@359	1482	ROL1_r32( R_EAX );
nkeynes@359	1483	store_reg( R_EAX, Rn );
nkeynes@359	1484	SETC_t();
nkeynes@359	1485	}
nkeynes@359	1486	break;
nkeynes@359	1487	case 0x2:
nkeynes@359	1488	{ /* ROTCL Rn */
nkeynes@359	1489	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1490	load_reg( R_EAX, Rn );
nkeynes@359	1491	LDC_t();
nkeynes@359	1492	RCL1_r32( R_EAX );
nkeynes@359	1493	store_reg( R_EAX, Rn );
nkeynes@359	1494	SETC_t();
nkeynes@359	1495	}
nkeynes@359	1496	break;
nkeynes@359	1497	default:
nkeynes@359	1498	UNDEF();
nkeynes@359	1499	break;
nkeynes@359	1500	}
nkeynes@359	1501	break;
nkeynes@359	1502	case 0x5:
nkeynes@359	1503	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1504	case 0x0:
nkeynes@359	1505	{ /* ROTR Rn */
nkeynes@359	1506	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1507	load_reg( R_EAX, Rn );
nkeynes@359	1508	ROR1_r32( R_EAX );
nkeynes@359	1509	store_reg( R_EAX, Rn );
nkeynes@359	1510	SETC_t();
nkeynes@359	1511	}
nkeynes@359	1512	break;
nkeynes@359	1513	case 0x1:
nkeynes@359	1514	{ /* CMP/PL Rn */
nkeynes@359	1515	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1516	load_reg( R_EAX, Rn );
nkeynes@359	1517	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	1518	SETG_t();
nkeynes@359	1519	}
nkeynes@359	1520	break;
nkeynes@359	1521	case 0x2:
nkeynes@359	1522	{ /* ROTCR Rn */
nkeynes@359	1523	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1524	load_reg( R_EAX, Rn );
nkeynes@359	1525	LDC_t();
nkeynes@359	1526	RCR1_r32( R_EAX );
nkeynes@359	1527	store_reg( R_EAX, Rn );
nkeynes@359	1528	SETC_t();
nkeynes@359	1529	}
nkeynes@359	1530	break;
nkeynes@359	1531	default:
nkeynes@359	1532	UNDEF();
nkeynes@359	1533	break;
nkeynes@359	1534	}
nkeynes@359	1535	break;
nkeynes@359	1536	case 0x6:
nkeynes@359	1537	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1538	case 0x0:
nkeynes@359	1539	{ /* LDS.L @Rm+, MACH */
nkeynes@359	1540	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1541	load_reg( R_EAX, Rm );
nkeynes@359	1542	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1543	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1544	store_reg( R_EAX, Rm );
nkeynes@359	1545	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1546	store_spreg( R_EAX, R_MACH );
nkeynes@359	1547	}
nkeynes@359	1548	break;
nkeynes@359	1549	case 0x1:
nkeynes@359	1550	{ /* LDS.L @Rm+, MACL */
nkeynes@359	1551	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1552	load_reg( R_EAX, Rm );
nkeynes@359	1553	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1554	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1555	store_reg( R_EAX, Rm );
nkeynes@359	1556	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1557	store_spreg( R_EAX, R_MACL );
nkeynes@359	1558	}
nkeynes@359	1559	break;
nkeynes@359	1560	case 0x2:
nkeynes@359	1561	{ /* LDS.L @Rm+, PR */
nkeynes@359	1562	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1563	load_reg( R_EAX, Rm );
nkeynes@359	1564	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1565	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1566	store_reg( R_EAX, Rm );
nkeynes@359	1567	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1568	store_spreg( R_EAX, R_PR );
nkeynes@359	1569	}
nkeynes@359	1570	break;
nkeynes@359	1571	case 0x3:
nkeynes@359	1572	{ /* LDC.L @Rm+, SGR */
nkeynes@359	1573	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1574	check_priv();
nkeynes@359	1575	load_reg( R_EAX, Rm );
nkeynes@359	1576	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1577	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1578	store_reg( R_EAX, Rm );
nkeynes@359	1579	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1580	store_spreg( R_EAX, R_SGR );
nkeynes@359	1581	}
nkeynes@359	1582	break;
nkeynes@359	1583	case 0x5:
nkeynes@359	1584	{ /* LDS.L @Rm+, FPUL */
nkeynes@359	1585	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1586	load_reg( R_EAX, Rm );
nkeynes@359	1587	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1588	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1589	store_reg( R_EAX, Rm );
nkeynes@359	1590	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1591	store_spreg( R_EAX, R_FPUL );
nkeynes@359	1592	}
nkeynes@359	1593	break;
nkeynes@359	1594	case 0x6:
nkeynes@359	1595	{ /* LDS.L @Rm+, FPSCR */
nkeynes@359	1596	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1597	load_reg( R_EAX, Rm );
nkeynes@359	1598	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1599	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1600	store_reg( R_EAX, Rm );
nkeynes@359	1601	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1602	store_spreg( R_EAX, R_FPSCR );
nkeynes@386	1603	update_fr_bank( R_EAX );
nkeynes@359	1604	}
nkeynes@359	1605	break;
nkeynes@359	1606	case 0xF:
nkeynes@359	1607	{ /* LDC.L @Rm+, DBR */
nkeynes@359	1608	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1609	check_priv();
nkeynes@359	1610	load_reg( R_EAX, Rm );
nkeynes@359	1611	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1612	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1613	store_reg( R_EAX, Rm );
nkeynes@359	1614	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1615	store_spreg( R_EAX, R_DBR );
nkeynes@359	1616	}
nkeynes@359	1617	break;
nkeynes@359	1618	default:
nkeynes@359	1619	UNDEF();
nkeynes@359	1620	break;
nkeynes@359	1621	}
nkeynes@359	1622	break;
nkeynes@359	1623	case 0x7:
nkeynes@359	1624	switch( (ir&0x80) >> 7 ) {
nkeynes@359	1625	case 0x0:
nkeynes@359	1626	switch( (ir&0x70) >> 4 ) {
nkeynes@359	1627	case 0x0:
nkeynes@359	1628	{ /* LDC.L @Rm+, SR */
nkeynes@359	1629	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1630	if( sh4_x86.in_delay_slot ) {
nkeynes@386	1631	SLOTILLEGAL();
nkeynes@386	1632	} else {
nkeynes@386	1633	check_priv();
nkeynes@386	1634	load_reg( R_EAX, Rm );
nkeynes@386	1635	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@386	1636	ADD_imm8s_r32( 4, R_EAX );
nkeynes@386	1637	store_reg( R_EAX, Rm );
nkeynes@386	1638	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@386	1639	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	1640	sh4_x86.priv_checked = FALSE;
nkeynes@386	1641	sh4_x86.fpuen_checked = FALSE;
nkeynes@386	1642	}
nkeynes@359	1643	}
nkeynes@359	1644	break;
nkeynes@359	1645	case 0x1:
nkeynes@359	1646	{ /* LDC.L @Rm+, GBR */
nkeynes@359	1647	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1648	load_reg( R_EAX, Rm );
nkeynes@359	1649	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1650	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1651	store_reg( R_EAX, Rm );
nkeynes@359	1652	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1653	store_spreg( R_EAX, R_GBR );
nkeynes@359	1654	}
nkeynes@359	1655	break;
nkeynes@359	1656	case 0x2:
nkeynes@359	1657	{ /* LDC.L @Rm+, VBR */
nkeynes@359	1658	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1659	check_priv();
nkeynes@359	1660	load_reg( R_EAX, Rm );
nkeynes@359	1661	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1662	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1663	store_reg( R_EAX, Rm );
nkeynes@359	1664	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1665	store_spreg( R_EAX, R_VBR );
nkeynes@359	1666	}
nkeynes@359	1667	break;
nkeynes@359	1668	case 0x3:
nkeynes@359	1669	{ /* LDC.L @Rm+, SSR */
nkeynes@359	1670	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1671	check_priv();
nkeynes@359	1672	load_reg( R_EAX, Rm );
nkeynes@359	1673	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1674	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1675	store_reg( R_EAX, Rm );
nkeynes@359	1676	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1677	store_spreg( R_EAX, R_SSR );
nkeynes@359	1678	}
nkeynes@359	1679	break;
nkeynes@359	1680	case 0x4:
nkeynes@359	1681	{ /* LDC.L @Rm+, SPC */
nkeynes@359	1682	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1683	check_priv();
nkeynes@359	1684	load_reg( R_EAX, Rm );
nkeynes@359	1685	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1686	ADD_imm8s_r32( 4, R_EAX );
nkeynes@359	1687	store_reg( R_EAX, Rm );
nkeynes@359	1688	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@359	1689	store_spreg( R_EAX, R_SPC );
nkeynes@359	1690	}
nkeynes@359	1691	break;
nkeynes@359	1692	default:
nkeynes@359	1693	UNDEF();
nkeynes@359	1694	break;
nkeynes@359	1695	}
nkeynes@359	1696	break;
nkeynes@359	1697	case 0x1:
nkeynes@359	1698	{ /* LDC.L @Rm+, Rn_BANK */
nkeynes@359	1699	uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
nkeynes@386	1700	check_priv();
nkeynes@374	1701	load_reg( R_EAX, Rm );
nkeynes@374	1702	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@374	1703	ADD_imm8s_r32( 4, R_EAX );
nkeynes@374	1704	store_reg( R_EAX, Rm );
nkeynes@374	1705	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@374	1706	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359	1707	}
nkeynes@359	1708	break;
nkeynes@359	1709	}
nkeynes@359	1710	break;
nkeynes@359	1711	case 0x8:
nkeynes@359	1712	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1713	case 0x0:
nkeynes@359	1714	{ /* SHLL2 Rn */
nkeynes@359	1715	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1716	load_reg( R_EAX, Rn );
nkeynes@359	1717	SHL_imm8_r32( 2, R_EAX );
nkeynes@359	1718	store_reg( R_EAX, Rn );
nkeynes@359	1719	}
nkeynes@359	1720	break;
nkeynes@359	1721	case 0x1:
nkeynes@359	1722	{ /* SHLL8 Rn */
nkeynes@359	1723	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1724	load_reg( R_EAX, Rn );
nkeynes@359	1725	SHL_imm8_r32( 8, R_EAX );
nkeynes@359	1726	store_reg( R_EAX, Rn );
nkeynes@359	1727	}
nkeynes@359	1728	break;
nkeynes@359	1729	case 0x2:
nkeynes@359	1730	{ /* SHLL16 Rn */
nkeynes@359	1731	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1732	load_reg( R_EAX, Rn );
nkeynes@359	1733	SHL_imm8_r32( 16, R_EAX );
nkeynes@359	1734	store_reg( R_EAX, Rn );
nkeynes@359	1735	}
nkeynes@359	1736	break;
nkeynes@359	1737	default:
nkeynes@359	1738	UNDEF();
nkeynes@359	1739	break;
nkeynes@359	1740	}
nkeynes@359	1741	break;
nkeynes@359	1742	case 0x9:
nkeynes@359	1743	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1744	case 0x0:
nkeynes@359	1745	{ /* SHLR2 Rn */
nkeynes@359	1746	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1747	load_reg( R_EAX, Rn );
nkeynes@359	1748	SHR_imm8_r32( 2, R_EAX );
nkeynes@359	1749	store_reg( R_EAX, Rn );
nkeynes@359	1750	}
nkeynes@359	1751	break;
nkeynes@359	1752	case 0x1:
nkeynes@359	1753	{ /* SHLR8 Rn */
nkeynes@359	1754	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1755	load_reg( R_EAX, Rn );
nkeynes@359	1756	SHR_imm8_r32( 8, R_EAX );
nkeynes@359	1757	store_reg( R_EAX, Rn );
nkeynes@359	1758	}
nkeynes@359	1759	break;
nkeynes@359	1760	case 0x2:
nkeynes@359	1761	{ /* SHLR16 Rn */
nkeynes@359	1762	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@359	1763	load_reg( R_EAX, Rn );
nkeynes@359	1764	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	1765	store_reg( R_EAX, Rn );
nkeynes@359	1766	}
nkeynes@359	1767	break;
nkeynes@359	1768	default:
nkeynes@359	1769	UNDEF();
nkeynes@359	1770	break;
nkeynes@359	1771	}
nkeynes@359	1772	break;
nkeynes@359	1773	case 0xA:
nkeynes@359	1774	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1775	case 0x0:
nkeynes@359	1776	{ /* LDS Rm, MACH */
nkeynes@359	1777	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1778	load_reg( R_EAX, Rm );
nkeynes@359	1779	store_spreg( R_EAX, R_MACH );
nkeynes@359	1780	}
nkeynes@359	1781	break;
nkeynes@359	1782	case 0x1:
nkeynes@359	1783	{ /* LDS Rm, MACL */
nkeynes@359	1784	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1785	load_reg( R_EAX, Rm );
nkeynes@359	1786	store_spreg( R_EAX, R_MACL );
nkeynes@359	1787	}
nkeynes@359	1788	break;
nkeynes@359	1789	case 0x2:
nkeynes@359	1790	{ /* LDS Rm, PR */
nkeynes@359	1791	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1792	load_reg( R_EAX, Rm );
nkeynes@359	1793	store_spreg( R_EAX, R_PR );
nkeynes@359	1794	}
nkeynes@359	1795	break;
nkeynes@359	1796	case 0x3:
nkeynes@359	1797	{ /* LDC Rm, SGR */
nkeynes@359	1798	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1799	check_priv();
nkeynes@359	1800	load_reg( R_EAX, Rm );
nkeynes@359	1801	store_spreg( R_EAX, R_SGR );
nkeynes@359	1802	}
nkeynes@359	1803	break;
nkeynes@359	1804	case 0x5:
nkeynes@359	1805	{ /* LDS Rm, FPUL */
nkeynes@359	1806	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1807	load_reg( R_EAX, Rm );
nkeynes@359	1808	store_spreg( R_EAX, R_FPUL );
nkeynes@359	1809	}
nkeynes@359	1810	break;
nkeynes@359	1811	case 0x6:
nkeynes@359	1812	{ /* LDS Rm, FPSCR */
nkeynes@359	1813	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1814	load_reg( R_EAX, Rm );
nkeynes@359	1815	store_spreg( R_EAX, R_FPSCR );
nkeynes@386	1816	update_fr_bank( R_EAX );
nkeynes@359	1817	}
nkeynes@359	1818	break;
nkeynes@359	1819	case 0xF:
nkeynes@359	1820	{ /* LDC Rm, DBR */
nkeynes@359	1821	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1822	check_priv();
nkeynes@359	1823	load_reg( R_EAX, Rm );
nkeynes@359	1824	store_spreg( R_EAX, R_DBR );
nkeynes@359	1825	}
nkeynes@359	1826	break;
nkeynes@359	1827	default:
nkeynes@359	1828	UNDEF();
nkeynes@359	1829	break;
nkeynes@359	1830	}
nkeynes@359	1831	break;
nkeynes@359	1832	case 0xB:
nkeynes@359	1833	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	1834	case 0x0:
nkeynes@359	1835	{ /* JSR @Rn */
nkeynes@359	1836	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	1837	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1838	SLOTILLEGAL();
nkeynes@374	1839	} else {
nkeynes@374	1840	load_imm32( R_EAX, pc + 4 );
nkeynes@374	1841	store_spreg( R_EAX, R_PR );
nkeynes@374	1842	load_reg( R_EDI, Rn );
nkeynes@374	1843	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	1844	return 0;
nkeynes@374	1845	}
nkeynes@359	1846	}
nkeynes@359	1847	break;
nkeynes@359	1848	case 0x1:
nkeynes@359	1849	{ /* TAS.B @Rn */
nkeynes@359	1850	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@361	1851	load_reg( R_ECX, Rn );
nkeynes@361	1852	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@361	1853	TEST_r8_r8( R_AL, R_AL );
nkeynes@361	1854	SETE_t();
nkeynes@361	1855	OR_imm8_r8( 0x80, R_AL );
nkeynes@386	1856	load_reg( R_ECX, Rn );
nkeynes@361	1857	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	1858	}
nkeynes@359	1859	break;
nkeynes@359	1860	case 0x2:
nkeynes@359	1861	{ /* JMP @Rn */
nkeynes@359	1862	uint32_t Rn = ((ir>>8)&0xF);
nkeynes@374	1863	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1864	SLOTILLEGAL();
nkeynes@374	1865	} else {
nkeynes@374	1866	load_reg( R_EDI, Rn );
nkeynes@374	1867	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	1868	return 0;
nkeynes@374	1869	}
nkeynes@359	1870	}
nkeynes@359	1871	break;
nkeynes@359	1872	default:
nkeynes@359	1873	UNDEF();
nkeynes@359	1874	break;
nkeynes@359	1875	}
nkeynes@359	1876	break;
nkeynes@359	1877	case 0xC:
nkeynes@359	1878	{ /* SHAD Rm, Rn */
nkeynes@359	1879	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	1880	/* Annoyingly enough, not directly convertible */
nkeynes@361	1881	load_reg( R_EAX, Rn );
nkeynes@361	1882	load_reg( R_ECX, Rm );
nkeynes@361	1883	CMP_imm32_r32( 0, R_ECX );
nkeynes@386	1884	JGE_rel8(16, doshl);
nkeynes@361	1885
nkeynes@361	1886	NEG_r32( R_ECX ); // 2
nkeynes@361	1887	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	1888	JE_rel8( 4, emptysar); // 2
nkeynes@361	1889	SAR_r32_CL( R_EAX ); // 2
nkeynes@386	1890	JMP_rel8(10, end); // 2
nkeynes@386	1891
nkeynes@386	1892	JMP_TARGET(emptysar);
nkeynes@386	1893	SAR_imm8_r32(31, R_EAX ); // 3
nkeynes@386	1894	JMP_rel8(5, end2);
nkeynes@386	1895
nkeynes@380	1896	JMP_TARGET(doshl);
nkeynes@361	1897	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361	1898	SHL_r32_CL( R_EAX ); // 2
nkeynes@380	1899	JMP_TARGET(end);
nkeynes@386	1900	JMP_TARGET(end2);
nkeynes@361	1901	store_reg( R_EAX, Rn );
nkeynes@359	1902	}
nkeynes@359	1903	break;
nkeynes@359	1904	case 0xD:
nkeynes@359	1905	{ /* SHLD Rm, Rn */
nkeynes@359	1906	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@368	1907	load_reg( R_EAX, Rn );
nkeynes@368	1908	load_reg( R_ECX, Rm );
nkeynes@386	1909	CMP_imm32_r32( 0, R_ECX );
nkeynes@386	1910	JGE_rel8(15, doshl);
nkeynes@368	1911
nkeynes@386	1912	NEG_r32( R_ECX ); // 2
nkeynes@386	1913	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	1914	JE_rel8( 4, emptyshr );
nkeynes@386	1915	SHR_r32_CL( R_EAX ); // 2
nkeynes@386	1916	JMP_rel8(9, end); // 2
nkeynes@386	1917
nkeynes@386	1918	JMP_TARGET(emptyshr);
nkeynes@386	1919	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@386	1920	JMP_rel8(5, end2);
nkeynes@386	1921
nkeynes@386	1922	JMP_TARGET(doshl);
nkeynes@386	1923	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@386	1924	SHL_r32_CL( R_EAX ); // 2
nkeynes@386	1925	JMP_TARGET(end);
nkeynes@386	1926	JMP_TARGET(end2);
nkeynes@368	1927	store_reg( R_EAX, Rn );
nkeynes@359	1928	}
nkeynes@359	1929	break;
nkeynes@359	1930	case 0xE:
nkeynes@359	1931	switch( (ir&0x80) >> 7 ) {
nkeynes@359	1932	case 0x0:
nkeynes@359	1933	switch( (ir&0x70) >> 4 ) {
nkeynes@359	1934	case 0x0:
nkeynes@359	1935	{ /* LDC Rm, SR */
nkeynes@359	1936	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1937	if( sh4_x86.in_delay_slot ) {
nkeynes@386	1938	SLOTILLEGAL();
nkeynes@386	1939	} else {
nkeynes@386	1940	check_priv();
nkeynes@386	1941	load_reg( R_EAX, Rm );
nkeynes@386	1942	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	1943	sh4_x86.priv_checked = FALSE;
nkeynes@386	1944	sh4_x86.fpuen_checked = FALSE;
nkeynes@386	1945	}
nkeynes@359	1946	}
nkeynes@359	1947	break;
nkeynes@359	1948	case 0x1:
nkeynes@359	1949	{ /* LDC Rm, GBR */
nkeynes@359	1950	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@359	1951	load_reg( R_EAX, Rm );
nkeynes@359	1952	store_spreg( R_EAX, R_GBR );
nkeynes@359	1953	}
nkeynes@359	1954	break;
nkeynes@359	1955	case 0x2:
nkeynes@359	1956	{ /* LDC Rm, VBR */
nkeynes@359	1957	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1958	check_priv();
nkeynes@359	1959	load_reg( R_EAX, Rm );
nkeynes@359	1960	store_spreg( R_EAX, R_VBR );
nkeynes@359	1961	}
nkeynes@359	1962	break;
nkeynes@359	1963	case 0x3:
nkeynes@359	1964	{ /* LDC Rm, SSR */
nkeynes@359	1965	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1966	check_priv();
nkeynes@359	1967	load_reg( R_EAX, Rm );
nkeynes@359	1968	store_spreg( R_EAX, R_SSR );
nkeynes@359	1969	}
nkeynes@359	1970	break;
nkeynes@359	1971	case 0x4:
nkeynes@359	1972	{ /* LDC Rm, SPC */
nkeynes@359	1973	uint32_t Rm = ((ir>>8)&0xF);
nkeynes@386	1974	check_priv();
nkeynes@359	1975	load_reg( R_EAX, Rm );
nkeynes@359	1976	store_spreg( R_EAX, R_SPC );
nkeynes@359	1977	}
nkeynes@359	1978	break;
nkeynes@359	1979	default:
nkeynes@359	1980	UNDEF();
nkeynes@359	1981	break;
nkeynes@359	1982	}
nkeynes@359	1983	break;
nkeynes@359	1984	case 0x1:
nkeynes@359	1985	{ /* LDC Rm, Rn_BANK */
nkeynes@359	1986	uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
nkeynes@386	1987	check_priv();
nkeynes@374	1988	load_reg( R_EAX, Rm );
nkeynes@374	1989	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@359	1990	}
nkeynes@359	1991	break;
nkeynes@359	1992	}
nkeynes@359	1993	break;
nkeynes@359	1994	case 0xF:
nkeynes@359	1995	{ /* MAC.W @Rm+, @Rn+ */
nkeynes@359	1996	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@386	1997	load_reg( R_ECX, Rm );
nkeynes@386	1998	check_ralign16( R_ECX );
nkeynes@386	1999	load_reg( R_ECX, Rn );
nkeynes@386	2000	check_ralign16( R_ECX );
nkeynes@386	2001	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@386	2002	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386	2003	PUSH_r32( R_EAX );
nkeynes@386	2004	load_reg( R_ECX, Rm );
nkeynes@386	2005	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@386	2006	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@386	2007	POP_r32( R_ECX );
nkeynes@386	2008	IMUL_r32( R_ECX );
nkeynes@386	2009
nkeynes@386	2010	load_spreg( R_ECX, R_S );
nkeynes@386	2011	TEST_r32_r32( R_ECX, R_ECX );
nkeynes@386	2012	JE_rel8( 47, nosat );
nkeynes@386	2013
nkeynes@386	2014	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@386	2015	JNO_rel8( 51, end ); // 2
nkeynes@386	2016	load_imm32( R_EDX, 1 ); // 5
nkeynes@386	2017	store_spreg( R_EDX, R_MACH ); // 6
nkeynes@386	2018	JS_rel8( 13, positive ); // 2
nkeynes@386	2019	load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386	2020	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@386	2021	JMP_rel8( 25, end2 ); // 2
nkeynes@386	2022
nkeynes@386	2023	JMP_TARGET(positive);
nkeynes@386	2024	load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386	2025	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@386	2026	JMP_rel8( 12, end3); // 2
nkeynes@386	2027
nkeynes@386	2028	JMP_TARGET(nosat);
nkeynes@386	2029	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@386	2030	ADC_r32_sh4r( R_EDX, R_MACH ); // 6
nkeynes@386	2031	JMP_TARGET(end);
nkeynes@386	2032	JMP_TARGET(end2);
nkeynes@386	2033	JMP_TARGET(end3);
nkeynes@359	2034	}
nkeynes@359	2035	break;
nkeynes@359	2036	}
nkeynes@359	2037	break;
nkeynes@359	2038	case 0x5:
nkeynes@359	2039	{ /* MOV.L @(disp, Rm), Rn */
nkeynes@359	2040	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
nkeynes@361	2041	load_reg( R_ECX, Rm );
nkeynes@361	2042	ADD_imm8s_r32( disp, R_ECX );
nkeynes@374	2043	check_ralign32( R_ECX );
nkeynes@361	2044	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361	2045	store_reg( R_EAX, Rn );
nkeynes@359	2046	}
nkeynes@359	2047	break;
nkeynes@359	2048	case 0x6:
nkeynes@359	2049	switch( ir&0xF ) {
nkeynes@359	2050	case 0x0:
nkeynes@359	2051	{ /* MOV.B @Rm, Rn */
nkeynes@359	2052	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2053	load_reg( R_ECX, Rm );
nkeynes@359	2054	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@386	2055	store_reg( R_EAX, Rn );
nkeynes@359	2056	}
nkeynes@359	2057	break;
nkeynes@359	2058	case 0x1:
nkeynes@359	2059	{ /* MOV.W @Rm, Rn */
nkeynes@359	2060	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2061	load_reg( R_ECX, Rm );
nkeynes@374	2062	check_ralign16( R_ECX );
nkeynes@361	2063	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361	2064	store_reg( R_EAX, Rn );
nkeynes@359	2065	}
nkeynes@359	2066	break;
nkeynes@359	2067	case 0x2:
nkeynes@359	2068	{ /* MOV.L @Rm, Rn */
nkeynes@359	2069	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2070	load_reg( R_ECX, Rm );
nkeynes@374	2071	check_ralign32( R_ECX );
nkeynes@361	2072	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361	2073	store_reg( R_EAX, Rn );
nkeynes@359	2074	}
nkeynes@359	2075	break;
nkeynes@359	2076	case 0x3:
nkeynes@359	2077	{ /* MOV Rm, Rn */
nkeynes@359	2078	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2079	load_reg( R_EAX, Rm );
nkeynes@359	2080	store_reg( R_EAX, Rn );
nkeynes@359	2081	}
nkeynes@359	2082	break;
nkeynes@359	2083	case 0x4:
nkeynes@359	2084	{ /* MOV.B @Rm+, Rn */
nkeynes@359	2085	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2086	load_reg( R_ECX, Rm );
nkeynes@359	2087	MOV_r32_r32( R_ECX, R_EAX );
nkeynes@359	2088	ADD_imm8s_r32( 1, R_EAX );
nkeynes@359	2089	store_reg( R_EAX, Rm );
nkeynes@359	2090	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359	2091	store_reg( R_EAX, Rn );
nkeynes@359	2092	}
nkeynes@359	2093	break;
nkeynes@359	2094	case 0x5:
nkeynes@359	2095	{ /* MOV.W @Rm+, Rn */
nkeynes@359	2096	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2097	load_reg( R_EAX, Rm );
nkeynes@374	2098	check_ralign16( R_EAX );
nkeynes@361	2099	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361	2100	ADD_imm8s_r32( 2, R_EAX );
nkeynes@361	2101	store_reg( R_EAX, Rm );
nkeynes@361	2102	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361	2103	store_reg( R_EAX, Rn );
nkeynes@359	2104	}
nkeynes@359	2105	break;
nkeynes@359	2106	case 0x6:
nkeynes@359	2107	{ /* MOV.L @Rm+, Rn */
nkeynes@359	2108	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2109	load_reg( R_EAX, Rm );
nkeynes@386	2110	check_ralign32( R_EAX );
nkeynes@361	2111	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@361	2112	ADD_imm8s_r32( 4, R_EAX );
nkeynes@361	2113	store_reg( R_EAX, Rm );
nkeynes@361	2114	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361	2115	store_reg( R_EAX, Rn );
nkeynes@359	2116	}
nkeynes@359	2117	break;
nkeynes@359	2118	case 0x7:
nkeynes@359	2119	{ /* NOT Rm, Rn */
nkeynes@359	2120	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2121	load_reg( R_EAX, Rm );
nkeynes@359	2122	NOT_r32( R_EAX );
nkeynes@359	2123	store_reg( R_EAX, Rn );
nkeynes@359	2124	}
nkeynes@359	2125	break;
nkeynes@359	2126	case 0x8:
nkeynes@359	2127	{ /* SWAP.B Rm, Rn */
nkeynes@359	2128	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2129	load_reg( R_EAX, Rm );
nkeynes@359	2130	XCHG_r8_r8( R_AL, R_AH );
nkeynes@359	2131	store_reg( R_EAX, Rn );
nkeynes@359	2132	}
nkeynes@359	2133	break;
nkeynes@359	2134	case 0x9:
nkeynes@359	2135	{ /* SWAP.W Rm, Rn */
nkeynes@359	2136	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2137	load_reg( R_EAX, Rm );
nkeynes@359	2138	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	2139	SHL_imm8_r32( 16, R_ECX );
nkeynes@359	2140	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	2141	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	2142	store_reg( R_ECX, Rn );
nkeynes@359	2143	}
nkeynes@359	2144	break;
nkeynes@359	2145	case 0xA:
nkeynes@359	2146	{ /* NEGC Rm, Rn */
nkeynes@359	2147	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2148	load_reg( R_EAX, Rm );
nkeynes@359	2149	XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359	2150	LDC_t();
nkeynes@359	2151	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	2152	store_reg( R_ECX, Rn );
nkeynes@359	2153	SETC_t();
nkeynes@359	2154	}
nkeynes@359	2155	break;
nkeynes@359	2156	case 0xB:
nkeynes@359	2157	{ /* NEG Rm, Rn */
nkeynes@359	2158	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2159	load_reg( R_EAX, Rm );
nkeynes@359	2160	NEG_r32( R_EAX );
nkeynes@359	2161	store_reg( R_EAX, Rn );
nkeynes@359	2162	}
nkeynes@359	2163	break;
nkeynes@359	2164	case 0xC:
nkeynes@359	2165	{ /* EXTU.B Rm, Rn */
nkeynes@359	2166	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2167	load_reg( R_EAX, Rm );
nkeynes@361	2168	MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361	2169	store_reg( R_EAX, Rn );
nkeynes@359	2170	}
nkeynes@359	2171	break;
nkeynes@359	2172	case 0xD:
nkeynes@359	2173	{ /* EXTU.W Rm, Rn */
nkeynes@359	2174	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2175	load_reg( R_EAX, Rm );
nkeynes@361	2176	MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361	2177	store_reg( R_EAX, Rn );
nkeynes@359	2178	}
nkeynes@359	2179	break;
nkeynes@359	2180	case 0xE:
nkeynes@359	2181	{ /* EXTS.B Rm, Rn */
nkeynes@359	2182	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@359	2183	load_reg( R_EAX, Rm );
nkeynes@359	2184	MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359	2185	store_reg( R_EAX, Rn );
nkeynes@359	2186	}
nkeynes@359	2187	break;
nkeynes@359	2188	case 0xF:
nkeynes@359	2189	{ /* EXTS.W Rm, Rn */
nkeynes@359	2190	uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@361	2191	load_reg( R_EAX, Rm );
nkeynes@361	2192	MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361	2193	store_reg( R_EAX, Rn );
nkeynes@359	2194	}
nkeynes@359	2195	break;
nkeynes@359	2196	}
nkeynes@359	2197	break;
nkeynes@359	2198	case 0x7:
nkeynes@359	2199	{ /* ADD #imm, Rn */
nkeynes@359	2200	uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2201	load_reg( R_EAX, Rn );
nkeynes@359	2202	ADD_imm8s_r32( imm, R_EAX );
nkeynes@359	2203	store_reg( R_EAX, Rn );
nkeynes@359	2204	}
nkeynes@359	2205	break;
nkeynes@359	2206	case 0x8:
nkeynes@359	2207	switch( (ir&0xF00) >> 8 ) {
nkeynes@359	2208	case 0x0:
nkeynes@359	2209	{ /* MOV.B R0, @(disp, Rn) */
nkeynes@359	2210	uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
nkeynes@359	2211	load_reg( R_EAX, 0 );
nkeynes@359	2212	load_reg( R_ECX, Rn );
nkeynes@359	2213	ADD_imm32_r32( disp, R_ECX );
nkeynes@359	2214	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	2215	}
nkeynes@359	2216	break;
nkeynes@359	2217	case 0x1:
nkeynes@359	2218	{ /* MOV.W R0, @(disp, Rn) */
nkeynes@359	2219	uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
nkeynes@361	2220	load_reg( R_ECX, Rn );
nkeynes@361	2221	load_reg( R_EAX, 0 );
nkeynes@361	2222	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2223	check_walign16( R_ECX );
nkeynes@361	2224	MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359	2225	}
nkeynes@359	2226	break;
nkeynes@359	2227	case 0x4:
nkeynes@359	2228	{ /* MOV.B @(disp, Rm), R0 */
nkeynes@359	2229	uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
nkeynes@359	2230	load_reg( R_ECX, Rm );
nkeynes@359	2231	ADD_imm32_r32( disp, R_ECX );
nkeynes@359	2232	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359	2233	store_reg( R_EAX, 0 );
nkeynes@359	2234	}
nkeynes@359	2235	break;
nkeynes@359	2236	case 0x5:
nkeynes@359	2237	{ /* MOV.W @(disp, Rm), R0 */
nkeynes@359	2238	uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
nkeynes@361	2239	load_reg( R_ECX, Rm );
nkeynes@361	2240	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2241	check_ralign16( R_ECX );
nkeynes@361	2242	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361	2243	store_reg( R_EAX, 0 );
nkeynes@359	2244	}
nkeynes@359	2245	break;
nkeynes@359	2246	case 0x8:
nkeynes@359	2247	{ /* CMP/EQ #imm, R0 */
nkeynes@359	2248	int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2249	load_reg( R_EAX, 0 );
nkeynes@359	2250	CMP_imm8s_r32(imm, R_EAX);
nkeynes@359	2251	SETE_t();
nkeynes@359	2252	}
nkeynes@359	2253	break;
nkeynes@359	2254	case 0x9:
nkeynes@359	2255	{ /* BT disp */
nkeynes@359	2256	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2257	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2258	SLOTILLEGAL();
nkeynes@374	2259	} else {
nkeynes@374	2260	load_imm32( R_EDI, pc + 2 );
nkeynes@374	2261	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380	2262	JE_rel8( 5, nottaken );
nkeynes@374	2263	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380	2264	JMP_TARGET(nottaken);
nkeynes@374	2265	INC_r32(R_ESI);
nkeynes@374	2266	return 1;
nkeynes@374	2267	}
nkeynes@359	2268	}
nkeynes@359	2269	break;
nkeynes@359	2270	case 0xB:
nkeynes@359	2271	{ /* BF disp */
nkeynes@359	2272	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2273	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2274	SLOTILLEGAL();
nkeynes@374	2275	} else {
nkeynes@374	2276	load_imm32( R_EDI, pc + 2 );
nkeynes@374	2277	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380	2278	JNE_rel8( 5, nottaken );
nkeynes@374	2279	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380	2280	JMP_TARGET(nottaken);
nkeynes@374	2281	INC_r32(R_ESI);
nkeynes@374	2282	return 1;
nkeynes@374	2283	}
nkeynes@359	2284	}
nkeynes@359	2285	break;
nkeynes@359	2286	case 0xD:
nkeynes@359	2287	{ /* BT/S disp */
nkeynes@359	2288	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2289	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2290	SLOTILLEGAL();
nkeynes@374	2291	} else {
nkeynes@386	2292	load_imm32( R_EDI, pc + 4 );
nkeynes@374	2293	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380	2294	JE_rel8( 5, nottaken );
nkeynes@374	2295	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380	2296	JMP_TARGET(nottaken);
nkeynes@374	2297	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	2298	return 0;
nkeynes@374	2299	}
nkeynes@359	2300	}
nkeynes@359	2301	break;
nkeynes@359	2302	case 0xF:
nkeynes@359	2303	{ /* BF/S disp */
nkeynes@359	2304	int32_t disp = SIGNEXT8(ir&0xFF)<<1;
nkeynes@374	2305	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2306	SLOTILLEGAL();
nkeynes@374	2307	} else {
nkeynes@386	2308	load_imm32( R_EDI, pc + 4 );
nkeynes@374	2309	CMP_imm8s_sh4r( 0, R_T );
nkeynes@380	2310	JNE_rel8( 5, nottaken );
nkeynes@374	2311	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@380	2312	JMP_TARGET(nottaken);
nkeynes@374	2313	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	2314	return 0;
nkeynes@374	2315	}
nkeynes@359	2316	}
nkeynes@359	2317	break;
nkeynes@359	2318	default:
nkeynes@359	2319	UNDEF();
nkeynes@359	2320	break;
nkeynes@359	2321	}
nkeynes@359	2322	break;
nkeynes@359	2323	case 0x9:
nkeynes@359	2324	{ /* MOV.W @(disp, PC), Rn */
nkeynes@359	2325	uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
nkeynes@374	2326	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2327	SLOTILLEGAL();
nkeynes@374	2328	} else {
nkeynes@374	2329	load_imm32( R_ECX, pc + disp + 4 );
nkeynes@374	2330	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@374	2331	store_reg( R_EAX, Rn );
nkeynes@374	2332	}
nkeynes@359	2333	}
nkeynes@359	2334	break;
nkeynes@359	2335	case 0xA:
nkeynes@359	2336	{ /* BRA disp */
nkeynes@359	2337	int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
nkeynes@374	2338	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2339	SLOTILLEGAL();
nkeynes@374	2340	} else {
nkeynes@374	2341	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374	2342	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	2343	return 0;
nkeynes@374	2344	}
nkeynes@359	2345	}
nkeynes@359	2346	break;
nkeynes@359	2347	case 0xB:
nkeynes@359	2348	{ /* BSR disp */
nkeynes@359	2349	int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
nkeynes@374	2350	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2351	SLOTILLEGAL();
nkeynes@374	2352	} else {
nkeynes@374	2353	load_imm32( R_EAX, pc + 4 );
nkeynes@374	2354	store_spreg( R_EAX, R_PR );
nkeynes@374	2355	load_imm32( R_EDI, disp + pc + 4 );
nkeynes@374	2356	sh4_x86.in_delay_slot = TRUE;
nkeynes@374	2357	return 0;
nkeynes@374	2358	}
nkeynes@359	2359	}
nkeynes@359	2360	break;
nkeynes@359	2361	case 0xC:
nkeynes@359	2362	switch( (ir&0xF00) >> 8 ) {
nkeynes@359	2363	case 0x0:
nkeynes@359	2364	{ /* MOV.B R0, @(disp, GBR) */
nkeynes@359	2365	uint32_t disp = (ir&0xFF);
nkeynes@359	2366	load_reg( R_EAX, 0 );
nkeynes@359	2367	load_spreg( R_ECX, R_GBR );
nkeynes@359	2368	ADD_imm32_r32( disp, R_ECX );
nkeynes@359	2369	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	2370	}
nkeynes@359	2371	break;
nkeynes@359	2372	case 0x1:
nkeynes@359	2373	{ /* MOV.W R0, @(disp, GBR) */
nkeynes@359	2374	uint32_t disp = (ir&0xFF)<<1;
nkeynes@361	2375	load_spreg( R_ECX, R_GBR );
nkeynes@361	2376	load_reg( R_EAX, 0 );
nkeynes@361	2377	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2378	check_walign16( R_ECX );
nkeynes@361	2379	MEM_WRITE_WORD( R_ECX, R_EAX );
nkeynes@359	2380	}
nkeynes@359	2381	break;
nkeynes@359	2382	case 0x2:
nkeynes@359	2383	{ /* MOV.L R0, @(disp, GBR) */
nkeynes@359	2384	uint32_t disp = (ir&0xFF)<<2;
nkeynes@361	2385	load_spreg( R_ECX, R_GBR );
nkeynes@361	2386	load_reg( R_EAX, 0 );
nkeynes@361	2387	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2388	check_walign32( R_ECX );
nkeynes@361	2389	MEM_WRITE_LONG( R_ECX, R_EAX );
nkeynes@359	2390	}
nkeynes@359	2391	break;
nkeynes@359	2392	case 0x3:
nkeynes@359	2393	{ /* TRAPA #imm */
nkeynes@359	2394	uint32_t imm = (ir&0xFF);
nkeynes@374	2395	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2396	SLOTILLEGAL();
nkeynes@374	2397	} else {
nkeynes@388	2398	PUSH_imm32( imm );
nkeynes@388	2399	call_func0( sh4_raise_trap );
nkeynes@388	2400	ADD_imm8s_r32( 4, R_ESP );
nkeynes@374	2401	}
nkeynes@359	2402	}
nkeynes@359	2403	break;
nkeynes@359	2404	case 0x4:
nkeynes@359	2405	{ /* MOV.B @(disp, GBR), R0 */
nkeynes@359	2406	uint32_t disp = (ir&0xFF);
nkeynes@359	2407	load_spreg( R_ECX, R_GBR );
nkeynes@359	2408	ADD_imm32_r32( disp, R_ECX );
nkeynes@359	2409	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@359	2410	store_reg( R_EAX, 0 );
nkeynes@359	2411	}
nkeynes@359	2412	break;
nkeynes@359	2413	case 0x5:
nkeynes@359	2414	{ /* MOV.W @(disp, GBR), R0 */
nkeynes@359	2415	uint32_t disp = (ir&0xFF)<<1;
nkeynes@361	2416	load_spreg( R_ECX, R_GBR );
nkeynes@361	2417	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2418	check_ralign16( R_ECX );
nkeynes@361	2419	MEM_READ_WORD( R_ECX, R_EAX );
nkeynes@361	2420	store_reg( R_EAX, 0 );
nkeynes@359	2421	}
nkeynes@359	2422	break;
nkeynes@359	2423	case 0x6:
nkeynes@359	2424	{ /* MOV.L @(disp, GBR), R0 */
nkeynes@359	2425	uint32_t disp = (ir&0xFF)<<2;
nkeynes@361	2426	load_spreg( R_ECX, R_GBR );
nkeynes@361	2427	ADD_imm32_r32( disp, R_ECX );
nkeynes@374	2428	check_ralign32( R_ECX );
nkeynes@361	2429	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@361	2430	store_reg( R_EAX, 0 );
nkeynes@359	2431	}
nkeynes@359	2432	break;
nkeynes@359	2433	case 0x7:
nkeynes@359	2434	{ /* MOVA @(disp, PC), R0 */
nkeynes@359	2435	uint32_t disp = (ir&0xFF)<<2;
nkeynes@374	2436	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2437	SLOTILLEGAL();
nkeynes@374	2438	} else {
nkeynes@374	2439	load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
nkeynes@374	2440	store_reg( R_ECX, 0 );
nkeynes@374	2441	}
nkeynes@359	2442	}
nkeynes@359	2443	break;
nkeynes@359	2444	case 0x8:
nkeynes@359	2445	{ /* TST #imm, R0 */
nkeynes@359	2446	uint32_t imm = (ir&0xFF);
nkeynes@368	2447	load_reg( R_EAX, 0 );
nkeynes@368	2448	TEST_imm32_r32( imm, R_EAX );
nkeynes@368	2449	SETE_t();
nkeynes@359	2450	}
nkeynes@359	2451	break;
nkeynes@359	2452	case 0x9:
nkeynes@359	2453	{ /* AND #imm, R0 */
nkeynes@359	2454	uint32_t imm = (ir&0xFF);
nkeynes@359	2455	load_reg( R_EAX, 0 );
nkeynes@359	2456	AND_imm32_r32(imm, R_EAX);
nkeynes@359	2457	store_reg( R_EAX, 0 );
nkeynes@359	2458	}
nkeynes@359	2459	break;
nkeynes@359	2460	case 0xA:
nkeynes@359	2461	{ /* XOR #imm, R0 */
nkeynes@359	2462	uint32_t imm = (ir&0xFF);
nkeynes@359	2463	load_reg( R_EAX, 0 );
nkeynes@359	2464	XOR_imm32_r32( imm, R_EAX );
nkeynes@359	2465	store_reg( R_EAX, 0 );
nkeynes@359	2466	}
nkeynes@359	2467	break;
nkeynes@359	2468	case 0xB:
nkeynes@359	2469	{ /* OR #imm, R0 */
nkeynes@359	2470	uint32_t imm = (ir&0xFF);
nkeynes@359	2471	load_reg( R_EAX, 0 );
nkeynes@359	2472	OR_imm32_r32(imm, R_EAX);
nkeynes@359	2473	store_reg( R_EAX, 0 );
nkeynes@359	2474	}
nkeynes@359	2475	break;
nkeynes@359	2476	case 0xC:
nkeynes@359	2477	{ /* TST.B #imm, @(R0, GBR) */
nkeynes@359	2478	uint32_t imm = (ir&0xFF);
nkeynes@368	2479	load_reg( R_EAX, 0);
nkeynes@368	2480	load_reg( R_ECX, R_GBR);
nkeynes@368	2481	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@368	2482	MEM_READ_BYTE( R_ECX, R_EAX );
nkeynes@368	2483	TEST_imm8_r8( imm, R_EAX );
nkeynes@368	2484	SETE_t();
nkeynes@359	2485	}
nkeynes@359	2486	break;
nkeynes@359	2487	case 0xD:
nkeynes@359	2488	{ /* AND.B #imm, @(R0, GBR) */
nkeynes@359	2489	uint32_t imm = (ir&0xFF);
nkeynes@359	2490	load_reg( R_EAX, 0 );
nkeynes@359	2491	load_spreg( R_ECX, R_GBR );
nkeynes@374	2492	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386	2493	PUSH_r32(R_ECX);
nkeynes@386	2494	call_func0(sh4_read_byte);
nkeynes@386	2495	POP_r32(R_ECX);
nkeynes@386	2496	AND_imm32_r32(imm, R_EAX );
nkeynes@359	2497	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	2498	}
nkeynes@359	2499	break;
nkeynes@359	2500	case 0xE:
nkeynes@359	2501	{ /* XOR.B #imm, @(R0, GBR) */
nkeynes@359	2502	uint32_t imm = (ir&0xFF);
nkeynes@359	2503	load_reg( R_EAX, 0 );
nkeynes@359	2504	load_spreg( R_ECX, R_GBR );
nkeynes@359	2505	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386	2506	PUSH_r32(R_ECX);
nkeynes@386	2507	call_func0(sh4_read_byte);
nkeynes@386	2508	POP_r32(R_ECX);
nkeynes@359	2509	XOR_imm32_r32( imm, R_EAX );
nkeynes@359	2510	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	2511	}
nkeynes@359	2512	break;
nkeynes@359	2513	case 0xF:
nkeynes@359	2514	{ /* OR.B #imm, @(R0, GBR) */
nkeynes@359	2515	uint32_t imm = (ir&0xFF);
nkeynes@374	2516	load_reg( R_EAX, 0 );
nkeynes@374	2517	load_spreg( R_ECX, R_GBR );
nkeynes@374	2518	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@386	2519	PUSH_r32(R_ECX);
nkeynes@386	2520	call_func0(sh4_read_byte);
nkeynes@386	2521	POP_r32(R_ECX);
nkeynes@386	2522	OR_imm32_r32(imm, R_EAX );
nkeynes@374	2523	MEM_WRITE_BYTE( R_ECX, R_EAX );
nkeynes@359	2524	}
nkeynes@359	2525	break;
nkeynes@359	2526	}
nkeynes@359	2527	break;
nkeynes@359	2528	case 0xD:
nkeynes@359	2529	{ /* MOV.L @(disp, PC), Rn */
nkeynes@359	2530	uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
nkeynes@374	2531	if( sh4_x86.in_delay_slot ) {
nkeynes@374	2532	SLOTILLEGAL();
nkeynes@374	2533	} else {
nkeynes@388	2534	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@388	2535	char *ptr = mem_get_region(target);
nkeynes@388	2536	if( ptr != NULL ) {
nkeynes@388	2537	MOV_moff32_EAX( (uint32_t)ptr );
nkeynes@388	2538	} else {
nkeynes@388	2539	load_imm32( R_ECX, target );
nkeynes@388	2540	MEM_READ_LONG( R_ECX, R_EAX );
nkeynes@388	2541	}
nkeynes@386	2542	store_reg( R_EAX, Rn );
nkeynes@374	2543	}
nkeynes@359	2544	}
nkeynes@359	2545	break;
nkeynes@359	2546	case 0xE:
nkeynes@359	2547	{ /* MOV #imm, Rn */
nkeynes@359	2548	uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
nkeynes@359	2549	load_imm32( R_EAX, imm );
nkeynes@359	2550	store_reg( R_EAX, Rn );
nkeynes@359	2551	}
nkeynes@359	2552	break;
nkeynes@359	2553	case 0xF:
nkeynes@359	2554	switch( ir&0xF ) {
nkeynes@359	2555	case 0x0:
nkeynes@359	2556	{ /* FADD FRm, FRn */
nkeynes@359	2557	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2558	check_fpuen();
nkeynes@377	2559	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2560	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2561	load_fr_bank( R_EDX );
nkeynes@380	2562	JNE_rel8(13,doubleprec);
nkeynes@377	2563	push_fr(R_EDX, FRm);
nkeynes@377	2564	push_fr(R_EDX, FRn);
nkeynes@377	2565	FADDP_st(1);
nkeynes@377	2566	pop_fr(R_EDX, FRn);
nkeynes@380	2567	JMP_rel8(11,end);
nkeynes@380	2568	JMP_TARGET(doubleprec);
nkeynes@377	2569	push_dr(R_EDX, FRm);
nkeynes@377	2570	push_dr(R_EDX, FRn);
nkeynes@377	2571	FADDP_st(1);
nkeynes@377	2572	pop_dr(R_EDX, FRn);
nkeynes@380	2573	JMP_TARGET(end);
nkeynes@359	2574	}
nkeynes@359	2575	break;
nkeynes@359	2576	case 0x1:
nkeynes@359	2577	{ /* FSUB FRm, FRn */
nkeynes@359	2578	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2579	check_fpuen();
nkeynes@377	2580	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2581	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2582	load_fr_bank( R_EDX );
nkeynes@380	2583	JNE_rel8(13, doubleprec);
nkeynes@377	2584	push_fr(R_EDX, FRn);
nkeynes@377	2585	push_fr(R_EDX, FRm);
nkeynes@388	2586	FSUBP_st(1);
nkeynes@377	2587	pop_fr(R_EDX, FRn);
nkeynes@380	2588	JMP_rel8(11, end);
nkeynes@380	2589	JMP_TARGET(doubleprec);
nkeynes@377	2590	push_dr(R_EDX, FRn);
nkeynes@377	2591	push_dr(R_EDX, FRm);
nkeynes@388	2592	FSUBP_st(1);
nkeynes@377	2593	pop_dr(R_EDX, FRn);
nkeynes@380	2594	JMP_TARGET(end);
nkeynes@359	2595	}
nkeynes@359	2596	break;
nkeynes@359	2597	case 0x2:
nkeynes@359	2598	{ /* FMUL FRm, FRn */
nkeynes@359	2599	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2600	check_fpuen();
nkeynes@377	2601	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2602	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2603	load_fr_bank( R_EDX );
nkeynes@380	2604	JNE_rel8(13, doubleprec);
nkeynes@377	2605	push_fr(R_EDX, FRm);
nkeynes@377	2606	push_fr(R_EDX, FRn);
nkeynes@377	2607	FMULP_st(1);
nkeynes@377	2608	pop_fr(R_EDX, FRn);
nkeynes@380	2609	JMP_rel8(11, end);
nkeynes@380	2610	JMP_TARGET(doubleprec);
nkeynes@377	2611	push_dr(R_EDX, FRm);
nkeynes@377	2612	push_dr(R_EDX, FRn);
nkeynes@377	2613	FMULP_st(1);
nkeynes@377	2614	pop_dr(R_EDX, FRn);
nkeynes@380	2615	JMP_TARGET(end);
nkeynes@359	2616	}
nkeynes@359	2617	break;
nkeynes@359	2618	case 0x3:
nkeynes@359	2619	{ /* FDIV FRm, FRn */
nkeynes@359	2620	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2621	check_fpuen();
nkeynes@377	2622	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2623	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2624	load_fr_bank( R_EDX );
nkeynes@380	2625	JNE_rel8(13, doubleprec);
nkeynes@377	2626	push_fr(R_EDX, FRn);
nkeynes@377	2627	push_fr(R_EDX, FRm);
nkeynes@377	2628	FDIVP_st(1);
nkeynes@377	2629	pop_fr(R_EDX, FRn);
nkeynes@380	2630	JMP_rel8(11, end);
nkeynes@380	2631	JMP_TARGET(doubleprec);
nkeynes@377	2632	push_dr(R_EDX, FRn);
nkeynes@377	2633	push_dr(R_EDX, FRm);
nkeynes@377	2634	FDIVP_st(1);
nkeynes@377	2635	pop_dr(R_EDX, FRn);
nkeynes@380	2636	JMP_TARGET(end);
nkeynes@359	2637	}
nkeynes@359	2638	break;
nkeynes@359	2639	case 0x4:
nkeynes@359	2640	{ /* FCMP/EQ FRm, FRn */
nkeynes@359	2641	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2642	check_fpuen();
nkeynes@377	2643	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2644	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2645	load_fr_bank( R_EDX );
nkeynes@380	2646	JNE_rel8(8, doubleprec);
nkeynes@377	2647	push_fr(R_EDX, FRm);
nkeynes@377	2648	push_fr(R_EDX, FRn);
nkeynes@380	2649	JMP_rel8(6, end);
nkeynes@380	2650	JMP_TARGET(doubleprec);
nkeynes@377	2651	push_dr(R_EDX, FRm);
nkeynes@377	2652	push_dr(R_EDX, FRn);
nkeynes@386	2653	JMP_TARGET(end);
nkeynes@377	2654	FCOMIP_st(1);
nkeynes@377	2655	SETE_t();
nkeynes@377	2656	FPOP_st();
nkeynes@359	2657	}
nkeynes@359	2658	break;
nkeynes@359	2659	case 0x5:
nkeynes@359	2660	{ /* FCMP/GT FRm, FRn */
nkeynes@359	2661	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2662	check_fpuen();
nkeynes@377	2663	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2664	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	2665	load_fr_bank( R_EDX );
nkeynes@380	2666	JNE_rel8(8, doubleprec);
nkeynes@377	2667	push_fr(R_EDX, FRm);
nkeynes@377	2668	push_fr(R_EDX, FRn);
nkeynes@380	2669	JMP_rel8(6, end);
nkeynes@380	2670	JMP_TARGET(doubleprec);
nkeynes@377	2671	push_dr(R_EDX, FRm);
nkeynes@377	2672	push_dr(R_EDX, FRn);
nkeynes@380	2673	JMP_TARGET(end);
nkeynes@377	2674	FCOMIP_st(1);
nkeynes@377	2675	SETA_t();
nkeynes@377	2676	FPOP_st();
nkeynes@359	2677	}
nkeynes@359	2678	break;
nkeynes@359	2679	case 0x6:
nkeynes@359	2680	{ /* FMOV @(R0, Rm), FRn */
nkeynes@359	2681	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@377	2682	check_fpuen();
nkeynes@375	2683	load_reg( R_EDX, Rm );
nkeynes@377	2684	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@375	2685	check_ralign32( R_EDX );
nkeynes@375	2686	load_spreg( R_ECX, R_FPSCR );
nkeynes@375	2687	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2688	JNE_rel8(19, doublesize);
nkeynes@375	2689	MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377	2690	load_fr_bank( R_ECX );
nkeynes@375	2691	store_fr( R_ECX, R_EAX, FRn );
nkeynes@375	2692	if( FRn&1 ) {
nkeynes@386	2693	JMP_rel8(48, end);
nkeynes@380	2694	JMP_TARGET(doublesize);
nkeynes@375	2695	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@375	2696	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@375	2697	load_xf_bank( R_ECX );
nkeynes@380	2698	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2699	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2700	JMP_TARGET(end);
nkeynes@375	2701	} else {
nkeynes@380	2702	JMP_rel8(36, end);
nkeynes@380	2703	JMP_TARGET(doublesize);
nkeynes@375	2704	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377	2705	load_fr_bank( R_ECX );
nkeynes@380	2706	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2707	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2708	JMP_TARGET(end);
nkeynes@377	2709	}
nkeynes@377	2710	}
nkeynes@377	2711	break;
nkeynes@377	2712	case 0x7:
nkeynes@377	2713	{ /* FMOV FRm, @(R0, Rn) */
nkeynes@377	2714	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2715	check_fpuen();
nkeynes@377	2716	load_reg( R_EDX, Rn );
nkeynes@377	2717	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
nkeynes@377	2718	check_walign32( R_EDX );
nkeynes@377	2719	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2720	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2721	JNE_rel8(20, doublesize);
nkeynes@377	2722	load_fr_bank( R_ECX );
nkeynes@377	2723	load_fr( R_ECX, R_EAX, FRm );
nkeynes@377	2724	MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377	2725	if( FRm&1 ) {
nkeynes@386	2726	JMP_rel8( 48, end );
nkeynes@380	2727	JMP_TARGET(doublesize);
nkeynes@377	2728	load_xf_bank( R_ECX );
nkeynes@380	2729	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2730	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2731	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2732	JMP_TARGET(end);
nkeynes@377	2733	} else {
nkeynes@380	2734	JMP_rel8( 39, end );
nkeynes@380	2735	JMP_TARGET(doublesize);
nkeynes@377	2736	load_fr_bank( R_ECX );
nkeynes@380	2737	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2738	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2739	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2740	JMP_TARGET(end);
nkeynes@377	2741	}
nkeynes@377	2742	}
nkeynes@377	2743	break;
nkeynes@377	2744	case 0x8:
nkeynes@377	2745	{ /* FMOV @Rm, FRn */
nkeynes@377	2746	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@377	2747	check_fpuen();
nkeynes@377	2748	load_reg( R_EDX, Rm );
nkeynes@377	2749	check_ralign32( R_EDX );
nkeynes@377	2750	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2751	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2752	JNE_rel8(19, doublesize);
nkeynes@377	2753	MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377	2754	load_fr_bank( R_ECX );
nkeynes@377	2755	store_fr( R_ECX, R_EAX, FRn );
nkeynes@377	2756	if( FRn&1 ) {
nkeynes@386	2757	JMP_rel8(48, end);
nkeynes@380	2758	JMP_TARGET(doublesize);
nkeynes@377	2759	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377	2760	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377	2761	load_xf_bank( R_ECX );
nkeynes@380	2762	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2763	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2764	JMP_TARGET(end);
nkeynes@377	2765	} else {
nkeynes@380	2766	JMP_rel8(36, end);
nkeynes@380	2767	JMP_TARGET(doublesize);
nkeynes@377	2768	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377	2769	load_fr_bank( R_ECX );
nkeynes@380	2770	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2771	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2772	JMP_TARGET(end);
nkeynes@375	2773	}
nkeynes@359	2774	}
nkeynes@359	2775	break;
nkeynes@359	2776	case 0x9:
nkeynes@359	2777	{ /* FMOV @Rm+, FRn */
nkeynes@359	2778	uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
nkeynes@377	2779	check_fpuen();
nkeynes@377	2780	load_reg( R_EDX, Rm );
nkeynes@377	2781	check_ralign32( R_EDX );
nkeynes@377	2782	MOV_r32_r32( R_EDX, R_EAX );
nkeynes@377	2783	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2784	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2785	JNE_rel8(25, doublesize);
nkeynes@377	2786	ADD_imm8s_r32( 4, R_EAX );
nkeynes@377	2787	store_reg( R_EAX, Rm );
nkeynes@377	2788	MEM_READ_LONG( R_EDX, R_EAX );
nkeynes@377	2789	load_fr_bank( R_ECX );
nkeynes@377	2790	store_fr( R_ECX, R_EAX, FRn );
nkeynes@377	2791	if( FRn&1 ) {
nkeynes@386	2792	JMP_rel8(54, end);
nkeynes@380	2793	JMP_TARGET(doublesize);
nkeynes@377	2794	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377	2795	store_reg(R_EAX, Rm);
nkeynes@377	2796	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377	2797	load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
nkeynes@377	2798	load_xf_bank( R_ECX );
nkeynes@380	2799	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2800	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2801	JMP_TARGET(end);
nkeynes@377	2802	} else {
nkeynes@380	2803	JMP_rel8(42, end);
nkeynes@377	2804	ADD_imm8s_r32( 8, R_EAX );
nkeynes@377	2805	store_reg(R_EAX, Rm);
nkeynes@377	2806	MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
nkeynes@377	2807	load_fr_bank( R_ECX );
nkeynes@380	2808	store_fr( R_ECX, R_EAX, FRn&0x0E );
nkeynes@380	2809	store_fr( R_ECX, R_EDX, FRn\|0x01 );
nkeynes@380	2810	JMP_TARGET(end);
nkeynes@377	2811	}
nkeynes@359	2812	}
nkeynes@359	2813	break;
nkeynes@359	2814	case 0xA:
nkeynes@359	2815	{ /* FMOV FRm, @Rn */
nkeynes@359	2816	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2817	check_fpuen();
nkeynes@375	2818	load_reg( R_EDX, Rn );
nkeynes@375	2819	check_walign32( R_EDX );
nkeynes@375	2820	load_spreg( R_ECX, R_FPSCR );
nkeynes@375	2821	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2822	JNE_rel8(20, doublesize);
nkeynes@377	2823	load_fr_bank( R_ECX );
nkeynes@375	2824	load_fr( R_ECX, R_EAX, FRm );
nkeynes@375	2825	MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@375	2826	if( FRm&1 ) {
nkeynes@386	2827	JMP_rel8( 48, end );
nkeynes@380	2828	JMP_TARGET(doublesize);
nkeynes@375	2829	load_xf_bank( R_ECX );
nkeynes@380	2830	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2831	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2832	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2833	JMP_TARGET(end);
nkeynes@375	2834	} else {
nkeynes@380	2835	JMP_rel8( 39, end );
nkeynes@380	2836	JMP_TARGET(doublesize);
nkeynes@377	2837	load_fr_bank( R_ECX );
nkeynes@380	2838	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2839	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2840	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2841	JMP_TARGET(end);
nkeynes@375	2842	}
nkeynes@359	2843	}
nkeynes@359	2844	break;
nkeynes@359	2845	case 0xB:
nkeynes@359	2846	{ /* FMOV FRm, @-Rn */
nkeynes@359	2847	uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	2848	check_fpuen();
nkeynes@377	2849	load_reg( R_EDX, Rn );
nkeynes@377	2850	check_walign32( R_EDX );
nkeynes@377	2851	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2852	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@386	2853	JNE_rel8(26, doublesize);
nkeynes@377	2854	load_fr_bank( R_ECX );
nkeynes@377	2855	load_fr( R_ECX, R_EAX, FRm );
nkeynes@377	2856	ADD_imm8s_r32(-4,R_EDX);
nkeynes@377	2857	store_reg( R_EDX, Rn );
nkeynes@377	2858	MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
nkeynes@377	2859	if( FRm&1 ) {
nkeynes@386	2860	JMP_rel8( 54, end );
nkeynes@380	2861	JMP_TARGET(doublesize);
nkeynes@377	2862	load_xf_bank( R_ECX );
nkeynes@380	2863	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2864	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2865	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380	2866	store_reg( R_EDX, Rn );
nkeynes@380	2867	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2868	JMP_TARGET(end);
nkeynes@377	2869	} else {
nkeynes@386	2870	JMP_rel8( 45, end );
nkeynes@380	2871	JMP_TARGET(doublesize);
nkeynes@377	2872	load_fr_bank( R_ECX );
nkeynes@380	2873	load_fr( R_ECX, R_EAX, FRm&0x0E );
nkeynes@380	2874	load_fr( R_ECX, R_ECX, FRm\|0x01 );
nkeynes@380	2875	ADD_imm8s_r32(-8,R_EDX);
nkeynes@380	2876	store_reg( R_EDX, Rn );
nkeynes@380	2877	MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
nkeynes@380	2878	JMP_TARGET(end);
nkeynes@377	2879	}
nkeynes@359	2880	}
nkeynes@359	2881	break;
nkeynes@359	2882	case 0xC:
nkeynes@359	2883	{ /* FMOV FRm, FRn */
nkeynes@359	2884	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@375	2885	/* As horrible as this looks, it's actually covering 5 separate cases:
nkeynes@375	2886	* 1. 32-bit fr-to-fr (PR=0)
nkeynes@375	2887	* 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
nkeynes@375	2888	* 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
nkeynes@375	2889	* 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
nkeynes@375	2890	* 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
nkeynes@375	2891	*/
nkeynes@377	2892	check_fpuen();
nkeynes@375	2893	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2894	load_fr_bank( R_EDX );
nkeynes@375	2895	TEST_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@380	2896	JNE_rel8(8, doublesize);
nkeynes@375	2897	load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
nkeynes@375	2898	store_fr( R_EDX, R_EAX, FRn );
nkeynes@375	2899	if( FRm&1 ) {
nkeynes@386	2900	JMP_rel8(24, end);
nkeynes@380	2901	JMP_TARGET(doublesize);
nkeynes@375	2902	load_xf_bank( R_ECX );
nkeynes@375	2903	load_fr( R_ECX, R_EAX, FRm-1 );
nkeynes@375	2904	if( FRn&1 ) {
nkeynes@375	2905	load_fr( R_ECX, R_EDX, FRm );
nkeynes@375	2906	store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375	2907	store_fr( R_ECX, R_EDX, FRn );
nkeynes@375	2908	} else /* FRn&1 == 0 */ {
nkeynes@375	2909	load_fr( R_ECX, R_ECX, FRm );
nkeynes@388	2910	store_fr( R_EDX, R_EAX, FRn );
nkeynes@388	2911	store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@375	2912	}
nkeynes@380	2913	JMP_TARGET(end);
nkeynes@375	2914	} else /* FRm&1 == 0 */ {
nkeynes@375	2915	if( FRn&1 ) {
nkeynes@386	2916	JMP_rel8(24, end);
nkeynes@375	2917	load_xf_bank( R_ECX );
nkeynes@375	2918	load_fr( R_EDX, R_EAX, FRm );
nkeynes@375	2919	load_fr( R_EDX, R_EDX, FRm+1 );
nkeynes@375	2920	store_fr( R_ECX, R_EAX, FRn-1 );
nkeynes@375	2921	store_fr( R_ECX, R_EDX, FRn );
nkeynes@380	2922	JMP_TARGET(end);
nkeynes@375	2923	} else /* FRn&1 == 0 */ {
nkeynes@380	2924	JMP_rel8(12, end);
nkeynes@375	2925	load_fr( R_EDX, R_EAX, FRm );
nkeynes@375	2926	load_fr( R_EDX, R_ECX, FRm+1 );
nkeynes@375	2927	store_fr( R_EDX, R_EAX, FRn );
nkeynes@375	2928	store_fr( R_EDX, R_ECX, FRn+1 );
nkeynes@380	2929	JMP_TARGET(end);
nkeynes@375	2930	}
nkeynes@375	2931	}
nkeynes@359	2932	}
nkeynes@359	2933	break;
nkeynes@359	2934	case 0xD:
nkeynes@359	2935	switch( (ir&0xF0) >> 4 ) {
nkeynes@359	2936	case 0x0:
nkeynes@359	2937	{ /* FSTS FPUL, FRn */
nkeynes@359	2938	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	2939	check_fpuen();
nkeynes@377	2940	load_fr_bank( R_ECX );
nkeynes@377	2941	load_spreg( R_EAX, R_FPUL );
nkeynes@377	2942	store_fr( R_ECX, R_EAX, FRn );
nkeynes@359	2943	}
nkeynes@359	2944	break;
nkeynes@359	2945	case 0x1:
nkeynes@359	2946	{ /* FLDS FRm, FPUL */
nkeynes@359	2947	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	2948	check_fpuen();
nkeynes@377	2949	load_fr_bank( R_ECX );
nkeynes@377	2950	load_fr( R_ECX, R_EAX, FRm );
nkeynes@377	2951	store_spreg( R_EAX, R_FPUL );
nkeynes@359	2952	}
nkeynes@359	2953	break;
nkeynes@359	2954	case 0x2:
nkeynes@359	2955	{ /* FLOAT FPUL, FRn */
nkeynes@359	2956	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	2957	check_fpuen();
nkeynes@377	2958	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	2959	load_spreg(R_EDX, REG_OFFSET(fr_bank));
nkeynes@377	2960	FILD_sh4r(R_FPUL);
nkeynes@377	2961	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	2962	JNE_rel8(5, doubleprec);
nkeynes@377	2963	pop_fr( R_EDX, FRn );
nkeynes@380	2964	JMP_rel8(3, end);
nkeynes@380	2965	JMP_TARGET(doubleprec);
nkeynes@377	2966	pop_dr( R_EDX, FRn );
nkeynes@380	2967	JMP_TARGET(end);
nkeynes@359	2968	}
nkeynes@359	2969	break;
nkeynes@359	2970	case 0x3:
nkeynes@359	2971	{ /* FTRC FRm, FPUL */
nkeynes@359	2972	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	2973	check_fpuen();
nkeynes@388	2974	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	2975	load_fr_bank( R_EDX );
nkeynes@388	2976	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	2977	JNE_rel8(5, doubleprec);
nkeynes@388	2978	push_fr( R_EDX, FRm );
nkeynes@388	2979	JMP_rel8(3, doop);
nkeynes@388	2980	JMP_TARGET(doubleprec);
nkeynes@388	2981	push_dr( R_EDX, FRm );
nkeynes@388	2982	JMP_TARGET( doop );
nkeynes@388	2983	load_imm32( R_ECX, (uint32_t)&max_int );
nkeynes@388	2984	FILD_r32ind( R_ECX );
nkeynes@388	2985	FCOMIP_st(1);
nkeynes@388	2986	JNA_rel8( 16, sat );
nkeynes@388	2987	load_imm32( R_ECX, (uint32_t)&min_int ); // 5
nkeynes@388	2988	FILD_r32ind( R_ECX ); // 2
nkeynes@388	2989	FCOMIP_st(1); // 2
nkeynes@388	2990	JAE_rel8( 5, sat2 ); // 2
nkeynes@388	2991	FISTP_sh4r(R_FPUL); // 3
nkeynes@388	2992	JMP_rel8( 9, end ); // 2
nkeynes@388	2993
nkeynes@388	2994	JMP_TARGET(sat);
nkeynes@388	2995	JMP_TARGET(sat2);
nkeynes@388	2996	MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388	2997	store_spreg( R_ECX, R_FPUL );
nkeynes@388	2998	FPOP_st();
nkeynes@388	2999	JMP_TARGET(end);
nkeynes@359	3000	}
nkeynes@359	3001	break;
nkeynes@359	3002	case 0x4:
nkeynes@359	3003	{ /* FNEG FRn */
nkeynes@359	3004	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3005	check_fpuen();
nkeynes@377	3006	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3007	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3008	load_fr_bank( R_EDX );
nkeynes@380	3009	JNE_rel8(10, doubleprec);
nkeynes@377	3010	push_fr(R_EDX, FRn);
nkeynes@377	3011	FCHS_st0();
nkeynes@377	3012	pop_fr(R_EDX, FRn);
nkeynes@380	3013	JMP_rel8(8, end);
nkeynes@380	3014	JMP_TARGET(doubleprec);
nkeynes@377	3015	push_dr(R_EDX, FRn);
nkeynes@377	3016	FCHS_st0();
nkeynes@377	3017	pop_dr(R_EDX, FRn);
nkeynes@380	3018	JMP_TARGET(end);
nkeynes@359	3019	}
nkeynes@359	3020	break;
nkeynes@359	3021	case 0x5:
nkeynes@359	3022	{ /* FABS FRn */
nkeynes@359	3023	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3024	check_fpuen();
nkeynes@374	3025	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3026	load_fr_bank( R_EDX );
nkeynes@374	3027	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3028	JNE_rel8(10, doubleprec);
nkeynes@374	3029	push_fr(R_EDX, FRn); // 3
nkeynes@374	3030	FABS_st0(); // 2
nkeynes@374	3031	pop_fr( R_EDX, FRn); //3
nkeynes@380	3032	JMP_rel8(8,end); // 2
nkeynes@380	3033	JMP_TARGET(doubleprec);
nkeynes@374	3034	push_dr(R_EDX, FRn);
nkeynes@374	3035	FABS_st0();
nkeynes@374	3036	pop_dr(R_EDX, FRn);
nkeynes@380	3037	JMP_TARGET(end);
nkeynes@359	3038	}
nkeynes@359	3039	break;
nkeynes@359	3040	case 0x6:
nkeynes@359	3041	{ /* FSQRT FRn */
nkeynes@359	3042	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3043	check_fpuen();
nkeynes@377	3044	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3045	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3046	load_fr_bank( R_EDX );
nkeynes@380	3047	JNE_rel8(10, doubleprec);
nkeynes@377	3048	push_fr(R_EDX, FRn);
nkeynes@377	3049	FSQRT_st0();
nkeynes@377	3050	pop_fr(R_EDX, FRn);
nkeynes@380	3051	JMP_rel8(8, end);
nkeynes@380	3052	JMP_TARGET(doubleprec);
nkeynes@377	3053	push_dr(R_EDX, FRn);
nkeynes@377	3054	FSQRT_st0();
nkeynes@377	3055	pop_dr(R_EDX, FRn);
nkeynes@380	3056	JMP_TARGET(end);
nkeynes@359	3057	}
nkeynes@359	3058	break;
nkeynes@359	3059	case 0x7:
nkeynes@359	3060	{ /* FSRRA FRn */
nkeynes@359	3061	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3062	check_fpuen();
nkeynes@377	3063	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3064	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@377	3065	load_fr_bank( R_EDX );
nkeynes@380	3066	JNE_rel8(12, end); // PR=0 only
nkeynes@377	3067	FLD1_st0();
nkeynes@377	3068	push_fr(R_EDX, FRn);
nkeynes@377	3069	FSQRT_st0();
nkeynes@377	3070	FDIVP_st(1);
nkeynes@377	3071	pop_fr(R_EDX, FRn);
nkeynes@380	3072	JMP_TARGET(end);
nkeynes@359	3073	}
nkeynes@359	3074	break;
nkeynes@359	3075	case 0x8:
nkeynes@359	3076	{ /* FLDI0 FRn */
nkeynes@359	3077	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3078	/* IFF PR=0 */
nkeynes@377	3079	check_fpuen();
nkeynes@377	3080	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3081	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3082	JNE_rel8(8, end);
nkeynes@377	3083	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@377	3084	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377	3085	store_fr( R_ECX, R_EAX, FRn );
nkeynes@380	3086	JMP_TARGET(end);
nkeynes@359	3087	}
nkeynes@359	3088	break;
nkeynes@359	3089	case 0x9:
nkeynes@359	3090	{ /* FLDI1 FRn */
nkeynes@359	3091	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3092	/* IFF PR=0 */
nkeynes@377	3093	check_fpuen();
nkeynes@377	3094	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3095	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3096	JNE_rel8(11, end);
nkeynes@377	3097	load_imm32(R_EAX, 0x3F800000);
nkeynes@377	3098	load_spreg( R_ECX, REG_OFFSET(fr_bank) );
nkeynes@377	3099	store_fr( R_ECX, R_EAX, FRn );
nkeynes@380	3100	JMP_TARGET(end);
nkeynes@359	3101	}
nkeynes@359	3102	break;
nkeynes@359	3103	case 0xA:
nkeynes@359	3104	{ /* FCNVSD FPUL, FRn */
nkeynes@359	3105	uint32_t FRn = ((ir>>8)&0xF);
nkeynes@377	3106	check_fpuen();
nkeynes@377	3107	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3108	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3109	JE_rel8(9, end); // only when PR=1
nkeynes@377	3110	load_fr_bank( R_ECX );
nkeynes@377	3111	push_fpul();
nkeynes@377	3112	pop_dr( R_ECX, FRn );
nkeynes@380	3113	JMP_TARGET(end);
nkeynes@359	3114	}
nkeynes@359	3115	break;
nkeynes@359	3116	case 0xB:
nkeynes@359	3117	{ /* FCNVDS FRm, FPUL */
nkeynes@359	3118	uint32_t FRm = ((ir>>8)&0xF);
nkeynes@377	3119	check_fpuen();
nkeynes@377	3120	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3121	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3122	JE_rel8(9, end); // only when PR=1
nkeynes@377	3123	load_fr_bank( R_ECX );
nkeynes@377	3124	push_dr( R_ECX, FRm );
nkeynes@377	3125	pop_fpul();
nkeynes@380	3126	JMP_TARGET(end);
nkeynes@359	3127	}
nkeynes@359	3128	break;
nkeynes@359	3129	case 0xE:
nkeynes@359	3130	{ /* FIPR FVm, FVn */
nkeynes@359	3131	uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
nkeynes@377	3132	check_fpuen();
nkeynes@388	3133	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3134	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	3135	JNE_rel8(44, doubleprec);
nkeynes@388	3136
nkeynes@388	3137	load_fr_bank( R_ECX );
nkeynes@388	3138	push_fr( R_ECX, FVm<<2 );
nkeynes@388	3139	push_fr( R_ECX, FVn<<2 );
nkeynes@388	3140	FMULP_st(1);
nkeynes@388	3141	push_fr( R_ECX, (FVm<<2)+1);
nkeynes@388	3142	push_fr( R_ECX, (FVn<<2)+1);
nkeynes@388	3143	FMULP_st(1);
nkeynes@388	3144	FADDP_st(1);
nkeynes@388	3145	push_fr( R_ECX, (FVm<<2)+2);
nkeynes@388	3146	push_fr( R_ECX, (FVn<<2)+2);
nkeynes@388	3147	FMULP_st(1);
nkeynes@388	3148	FADDP_st(1);
nkeynes@388	3149	push_fr( R_ECX, (FVm<<2)+3);
nkeynes@388	3150	push_fr( R_ECX, (FVn<<2)+3);
nkeynes@388	3151	FMULP_st(1);
nkeynes@388	3152	FADDP_st(1);
nkeynes@388	3153	pop_fr( R_ECX, (FVn<<2)+3);
nkeynes@388	3154	JMP_TARGET(doubleprec);
nkeynes@359	3155	}
nkeynes@359	3156	break;
nkeynes@359	3157	case 0xF:
nkeynes@359	3158	switch( (ir&0x100) >> 8 ) {
nkeynes@359	3159	case 0x0:
nkeynes@359	3160	{ /* FSCA FPUL, FRn */
nkeynes@359	3161	uint32_t FRn = ((ir>>9)&0x7)<<1;
nkeynes@377	3162	check_fpuen();
nkeynes@388	3163	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3164	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	3165	JNE_rel8( 21, doubleprec );
nkeynes@388	3166	load_fr_bank( R_ECX );
nkeynes@388	3167	ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
nkeynes@388	3168	load_spreg( R_EDX, R_FPUL );
nkeynes@388	3169	call_func2( sh4_fsca, R_EDX, R_ECX );
nkeynes@388	3170	JMP_TARGET(doubleprec);
nkeynes@359	3171	}
nkeynes@359	3172	break;
nkeynes@359	3173	case 0x1:
nkeynes@359	3174	switch( (ir&0x200) >> 9 ) {
nkeynes@359	3175	case 0x0:
nkeynes@359	3176	{ /* FTRV XMTRX, FVn */
nkeynes@359	3177	uint32_t FVn = ((ir>>10)&0x3);
nkeynes@377	3178	check_fpuen();
nkeynes@388	3179	load_spreg( R_ECX, R_FPSCR );
nkeynes@388	3180	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@388	3181	JNE_rel8( 30, doubleprec );
nkeynes@388	3182	load_fr_bank( R_EDX ); // 3
nkeynes@388	3183	ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
nkeynes@388	3184	load_xf_bank( R_ECX ); // 12
nkeynes@388	3185	call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
nkeynes@388	3186	JMP_TARGET(doubleprec);
nkeynes@359	3187	}
nkeynes@359	3188	break;
nkeynes@359	3189	case 0x1:
nkeynes@359	3190	switch( (ir&0xC00) >> 10 ) {
nkeynes@359	3191	case 0x0:
nkeynes@359	3192	{ /* FSCHG */
nkeynes@377	3193	check_fpuen();
nkeynes@377	3194	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3195	XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377	3196	store_spreg( R_ECX, R_FPSCR );
nkeynes@359	3197	}
nkeynes@359	3198	break;
nkeynes@359	3199	case 0x2:
nkeynes@359	3200	{ /* FRCHG */
nkeynes@377	3201	check_fpuen();
nkeynes@377	3202	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3203	XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377	3204	store_spreg( R_ECX, R_FPSCR );
nkeynes@386	3205	update_fr_bank( R_ECX );
nkeynes@359	3206	}
nkeynes@359	3207	break;
nkeynes@359	3208	case 0x3:
nkeynes@359	3209	{ /* UNDEF */
nkeynes@374	3210	if( sh4_x86.in_delay_slot ) {
nkeynes@386	3211	SLOTILLEGAL();
nkeynes@374	3212	} else {
nkeynes@386	3213	JMP_exit(EXIT_ILLEGAL);
nkeynes@386	3214	return 1;
nkeynes@374	3215	}
nkeynes@359	3216	}
nkeynes@359	3217	break;
nkeynes@359	3218	default:
nkeynes@359	3219	UNDEF();
nkeynes@359	3220	break;
nkeynes@359	3221	}
nkeynes@359	3222	break;
nkeynes@359	3223	}
nkeynes@359	3224	break;
nkeynes@359	3225	}
nkeynes@359	3226	break;
nkeynes@359	3227	default:
nkeynes@359	3228	UNDEF();
nkeynes@359	3229	break;
nkeynes@359	3230	}
nkeynes@359	3231	break;
nkeynes@359	3232	case 0xE:
nkeynes@359	3233	{ /* FMAC FR0, FRm, FRn */
nkeynes@359	3234	uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
nkeynes@377	3235	check_fpuen();
nkeynes@377	3236	load_spreg( R_ECX, R_FPSCR );
nkeynes@377	3237	load_spreg( R_EDX, REG_OFFSET(fr_bank));
nkeynes@377	3238	TEST_imm32_r32( FPSCR_PR, R_ECX );
nkeynes@380	3239	JNE_rel8(18, doubleprec);
nkeynes@377	3240	push_fr( R_EDX, 0 );
nkeynes@377	3241	push_fr( R_EDX, FRm );
nkeynes@377	3242	FMULP_st(1);
nkeynes@377	3243	push_fr( R_EDX, FRn );
nkeynes@377	3244	FADDP_st(1);
nkeynes@377	3245	pop_fr( R_EDX, FRn );
nkeynes@380	3246	JMP_rel8(16, end);
nkeynes@380	3247	JMP_TARGET(doubleprec);
nkeynes@377	3248	push_dr( R_EDX, 0 );
nkeynes@377	3249	push_dr( R_EDX, FRm );
nkeynes@377	3250	FMULP_st(1);
nkeynes@377	3251	push_dr( R_EDX, FRn );
nkeynes@377	3252	FADDP_st(1);
nkeynes@377	3253	pop_dr( R_EDX, FRn );
nkeynes@380	3254	JMP_TARGET(end);
nkeynes@359	3255	}
nkeynes@359	3256	break;
nkeynes@359	3257	default:
nkeynes@359	3258	UNDEF();
nkeynes@359	3259	break;
nkeynes@359	3260	}
nkeynes@359	3261	break;
nkeynes@359	3262	}
nkeynes@359	3263
nkeynes@374	3264	if( sh4_x86.in_delay_slot ) {
nkeynes@386	3265	ADD_imm8s_r32(2,R_ESI);
nkeynes@374	3266	sh4_x86.in_delay_slot = FALSE;
nkeynes@374	3267	return 1;
nkeynes@386	3268	} else {
nkeynes@386	3269	INC_r32(R_ESI);
nkeynes@374	3270	}
nkeynes@359	3271	return 0;
nkeynes@359	3272	}