nkeynes@31 | 1 | /**
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nkeynes@334 | 2 | * $Id: asic.c,v 1.27 2007-01-27 12:02:54 nkeynes Exp $
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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nkeynes@31 | 5 | * and DMA).
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nkeynes@31 | 6 | *
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nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 8 | *
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nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 12 | * (at your option) any later version.
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nkeynes@31 | 13 | *
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nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 17 | * GNU General Public License for more details.
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nkeynes@31 | 18 | */
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nkeynes@35 | 19 |
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nkeynes@35 | 20 | #define MODULE asic_module
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nkeynes@35 | 21 |
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nkeynes@1 | 22 | #include <assert.h>
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nkeynes@137 | 23 | #include <stdlib.h>
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nkeynes@1 | 24 | #include "dream.h"
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nkeynes@1 | 25 | #include "mem.h"
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nkeynes@1 | 26 | #include "sh4/intc.h"
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nkeynes@56 | 27 | #include "sh4/dmac.h"
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nkeynes@2 | 28 | #include "dreamcast.h"
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nkeynes@25 | 29 | #include "maple/maple.h"
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nkeynes@25 | 30 | #include "gdrom/ide.h"
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nkeynes@15 | 31 | #include "asic.h"
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nkeynes@1 | 32 | #define MMIO_IMPL
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nkeynes@1 | 33 | #include "asic.h"
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nkeynes@1 | 34 | /*
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nkeynes@1 | 35 | * Open questions:
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nkeynes@1 | 36 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 37 | * interrupt being delivered immediately?
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nkeynes@1 | 38 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 39 | *
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nkeynes@1 | 40 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 41 | * practically nothing is publicly known...
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nkeynes@1 | 42 | */
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nkeynes@1 | 43 |
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nkeynes@155 | 44 | static void asic_check_cleared_events( void );
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nkeynes@155 | 45 | static void asic_init( void );
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nkeynes@155 | 46 | static void asic_reset( void );
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nkeynes@302 | 47 | static uint32_t asic_run_slice( uint32_t nanosecs );
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nkeynes@155 | 48 | static void asic_save_state( FILE *f );
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nkeynes@155 | 49 | static int asic_load_state( FILE *f );
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nkeynes@302 | 50 | static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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nkeynes@155 | 51 |
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nkeynes@302 | 52 | struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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nkeynes@155 | 53 | NULL, asic_save_state, asic_load_state };
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nkeynes@15 | 54 |
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nkeynes@302 | 55 | #define G2_BIT5_TICKS 60
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nkeynes@302 | 56 | #define G2_BIT4_TICKS 160
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nkeynes@302 | 57 | #define G2_BIT0_ON_TICKS 120
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nkeynes@302 | 58 | #define G2_BIT0_OFF_TICKS 420
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nkeynes@137 | 59 |
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nkeynes@137 | 60 | struct asic_g2_state {
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nkeynes@302 | 61 | int bit5_off_timer;
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nkeynes@302 | 62 | int bit4_on_timer;
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nkeynes@302 | 63 | int bit4_off_timer;
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nkeynes@302 | 64 | int bit0_on_timer;
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nkeynes@302 | 65 | int bit0_off_timer;
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nkeynes@155 | 66 | };
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nkeynes@155 | 67 |
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nkeynes@155 | 68 | static struct asic_g2_state g2_state;
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nkeynes@155 | 69 |
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nkeynes@302 | 70 | static uint32_t asic_run_slice( uint32_t nanosecs )
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nkeynes@302 | 71 | {
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nkeynes@302 | 72 | g2_update_fifo_status(nanosecs);
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nkeynes@302 | 73 | if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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nkeynes@302 | 74 | g2_state.bit5_off_timer = -1;
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nkeynes@302 | 75 | } else {
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nkeynes@302 | 76 | g2_state.bit5_off_timer -= nanosecs;
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nkeynes@302 | 77 | }
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nkeynes@302 | 78 |
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nkeynes@302 | 79 | if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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nkeynes@302 | 80 | g2_state.bit4_off_timer = -1;
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nkeynes@302 | 81 | } else {
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nkeynes@302 | 82 | g2_state.bit4_off_timer -= nanosecs;
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nkeynes@302 | 83 | }
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nkeynes@302 | 84 | if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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nkeynes@302 | 85 | g2_state.bit4_on_timer = -1;
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nkeynes@302 | 86 | } else {
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nkeynes@302 | 87 | g2_state.bit4_on_timer -= nanosecs;
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nkeynes@302 | 88 | }
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nkeynes@302 | 89 |
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nkeynes@302 | 90 | if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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nkeynes@302 | 91 | g2_state.bit0_off_timer = -1;
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nkeynes@302 | 92 | } else {
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nkeynes@302 | 93 | g2_state.bit0_off_timer -= nanosecs;
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nkeynes@302 | 94 | }
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nkeynes@302 | 95 | if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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nkeynes@302 | 96 | g2_state.bit0_on_timer = -1;
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nkeynes@302 | 97 | } else {
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nkeynes@302 | 98 | g2_state.bit0_on_timer -= nanosecs;
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nkeynes@302 | 99 | }
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nkeynes@302 | 100 |
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nkeynes@302 | 101 | return nanosecs;
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nkeynes@302 | 102 | }
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nkeynes@302 | 103 |
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nkeynes@155 | 104 | static void asic_init( void )
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nkeynes@155 | 105 | {
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nkeynes@155 | 106 | register_io_region( &mmio_region_ASIC );
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nkeynes@155 | 107 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@155 | 108 | asic_reset();
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nkeynes@155 | 109 | }
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nkeynes@155 | 110 |
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nkeynes@155 | 111 | static void asic_reset( void )
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nkeynes@155 | 112 | {
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nkeynes@302 | 113 | memset( &g2_state, 0xFF, sizeof(g2_state) );
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nkeynes@155 | 114 | }
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nkeynes@155 | 115 |
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nkeynes@155 | 116 | static void asic_save_state( FILE *f )
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nkeynes@155 | 117 | {
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nkeynes@155 | 118 | fwrite( &g2_state, sizeof(g2_state), 1, f );
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nkeynes@155 | 119 | }
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nkeynes@155 | 120 |
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nkeynes@155 | 121 | static int asic_load_state( FILE *f )
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nkeynes@155 | 122 | {
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nkeynes@155 | 123 | if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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nkeynes@155 | 124 | return 1;
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nkeynes@155 | 125 | else
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nkeynes@155 | 126 | return 0;
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nkeynes@155 | 127 | }
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nkeynes@155 | 128 |
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nkeynes@137 | 129 |
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nkeynes@302 | 130 | /**
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nkeynes@302 | 131 | * Setup the timers for the 3 FIFO status bits following a write through the G2
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nkeynes@302 | 132 | * bus from the SH4 side. The timing is roughly as follows: (times are
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nkeynes@302 | 133 | * approximate based on software readings - I wouldn't take this as gospel but
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nkeynes@302 | 134 | * it seems to be enough to fool most programs).
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nkeynes@302 | 135 | * 0ns: Bit 5 (Input fifo?) goes high immediately on the write
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nkeynes@302 | 136 | * 40ns: Bit 5 goes low and bit 4 goes high
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nkeynes@302 | 137 | * 120ns: Bit 4 goes low, bit 0 goes high
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nkeynes@302 | 138 | * 240ns: Bit 0 goes low.
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nkeynes@302 | 139 | *
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nkeynes@302 | 140 | * Additional writes while the FIFO is in operation extend the time that the
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nkeynes@302 | 141 | * bits remain high as one might expect, without altering the time at which
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nkeynes@302 | 142 | * they initially go high.
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nkeynes@302 | 143 | */
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nkeynes@137 | 144 | void asic_g2_write_word()
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nkeynes@137 | 145 | {
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nkeynes@302 | 146 | if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@302 | 147 | g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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nkeynes@302 | 148 | } else {
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nkeynes@302 | 149 | g2_state.bit5_off_timer += G2_BIT5_TICKS;
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nkeynes@302 | 150 | }
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nkeynes@302 | 151 |
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nkeynes@302 | 152 | if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@302 | 153 | g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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nkeynes@302 | 154 | }
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nkeynes@302 | 155 |
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nkeynes@302 | 156 | if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@302 | 157 | g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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nkeynes@302 | 158 | } else {
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nkeynes@302 | 159 | g2_state.bit4_off_timer += G2_BIT4_TICKS;
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nkeynes@302 | 160 | }
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nkeynes@302 | 161 |
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nkeynes@302 | 162 | if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@302 | 163 | g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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nkeynes@302 | 164 | }
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nkeynes@302 | 165 |
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nkeynes@302 | 166 | if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@137 | 167 | g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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nkeynes@137 | 168 | } else {
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nkeynes@137 | 169 | g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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nkeynes@137 | 170 | }
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nkeynes@302 | 171 |
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nkeynes@137 | 172 | MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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nkeynes@137 | 173 | }
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nkeynes@137 | 174 |
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nkeynes@302 | 175 | static uint32_t g2_update_fifo_status( uint32_t nanos )
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nkeynes@137 | 176 | {
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nkeynes@302 | 177 | uint32_t val = MMIO_READ( ASIC, G2STATUS );
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nkeynes@302 | 178 | if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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nkeynes@302 | 179 | val = val & (~0x20);
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nkeynes@302 | 180 | g2_state.bit5_off_timer = -1;
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nkeynes@163 | 181 | }
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nkeynes@302 | 182 | if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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nkeynes@302 | 183 | val = val | 0x10;
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nkeynes@302 | 184 | g2_state.bit4_on_timer = -1;
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nkeynes@302 | 185 | }
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nkeynes@302 | 186 | if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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nkeynes@137 | 187 | val = val & (~0x10);
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nkeynes@302 | 188 | g2_state.bit4_off_timer = -1;
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nkeynes@302 | 189 | }
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nkeynes@302 | 190 |
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nkeynes@302 | 191 | if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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nkeynes@302 | 192 | val = val | 0x01;
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nkeynes@302 | 193 | g2_state.bit0_on_timer = -1;
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nkeynes@302 | 194 | }
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nkeynes@302 | 195 | if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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nkeynes@137 | 196 | val = val & (~0x01);
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nkeynes@302 | 197 | g2_state.bit0_off_timer = -1;
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nkeynes@302 | 198 | }
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nkeynes@302 | 199 |
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nkeynes@302 | 200 | MMIO_WRITE( ASIC, G2STATUS, val );
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nkeynes@302 | 201 | return val;
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nkeynes@137 | 202 | }
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nkeynes@137 | 203 |
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nkeynes@302 | 204 | static int g2_read_status() {
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nkeynes@302 | 205 | return g2_update_fifo_status( sh4r.slice_cycle );
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nkeynes@302 | 206 | }
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nkeynes@302 | 207 |
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nkeynes@20 | 208 |
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nkeynes@155 | 209 | void asic_event( int event )
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nkeynes@1 | 210 | {
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nkeynes@155 | 211 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 212 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@155 | 213 |
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nkeynes@155 | 214 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@155 | 215 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@155 | 216 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@155 | 217 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@155 | 218 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@155 | 219 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@305 | 220 |
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nkeynes@305 | 221 | if( event >= 64 ) { /* Third word */
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nkeynes@305 | 222 | asic_event( EVENT_CASCADE2 );
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nkeynes@305 | 223 | } else if( event >= 32 ) { /* Second word */
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nkeynes@305 | 224 | asic_event( EVENT_CASCADE1 );
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nkeynes@305 | 225 | }
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nkeynes@1 | 226 | }
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nkeynes@1 | 227 |
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nkeynes@155 | 228 | void asic_clear_event( int event ) {
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nkeynes@155 | 229 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 230 | uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
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nkeynes@155 | 231 | MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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nkeynes@305 | 232 | if( result == 0 ) {
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nkeynes@305 | 233 | /* clear cascades if necessary */
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nkeynes@305 | 234 | if( event >= 64 ) {
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nkeynes@305 | 235 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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nkeynes@305 | 236 | } else if( event >= 32 ) {
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nkeynes@305 | 237 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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nkeynes@305 | 238 | }
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nkeynes@305 | 239 | }
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nkeynes@305 | 240 |
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nkeynes@155 | 241 | asic_check_cleared_events();
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nkeynes@155 | 242 | }
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nkeynes@155 | 243 |
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nkeynes@155 | 244 | void asic_check_cleared_events( )
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nkeynes@155 | 245 | {
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nkeynes@155 | 246 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@155 | 247 | uint32_t bits;
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nkeynes@155 | 248 | for( i=0; i<3; i++ ) {
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nkeynes@155 | 249 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@155 | 250 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@155 | 251 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@155 | 252 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@155 | 253 | }
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nkeynes@155 | 254 | if( setA == 0 )
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nkeynes@155 | 255 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@155 | 256 | if( setB == 0 )
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nkeynes@155 | 257 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@155 | 258 | if( setC == 0 )
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nkeynes@155 | 259 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@155 | 260 | }
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nkeynes@155 | 261 |
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nkeynes@279 | 262 | void g2_dma_transfer( int channel )
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nkeynes@279 | 263 | {
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nkeynes@279 | 264 | uint32_t offset = channel << 5;
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nkeynes@279 | 265 |
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nkeynes@302 | 266 | if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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nkeynes@302 | 267 | if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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nkeynes@302 | 268 | uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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nkeynes@302 | 269 | uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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nkeynes@302 | 270 | uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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nkeynes@302 | 271 | uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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nkeynes@302 | 272 | uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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nkeynes@279 | 273 | char buf[length];
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nkeynes@279 | 274 | if( dir == 0 ) { /* SH4 to device */
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nkeynes@279 | 275 | mem_copy_from_sh4( buf, sh4addr, length );
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nkeynes@279 | 276 | mem_copy_to_sh4( extaddr, buf, length );
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nkeynes@279 | 277 | } else { /* Device to SH4 */
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nkeynes@279 | 278 | mem_copy_from_sh4( buf, extaddr, length );
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nkeynes@279 | 279 | mem_copy_to_sh4( sh4addr, buf, length );
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nkeynes@279 | 280 | }
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nkeynes@302 | 281 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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nkeynes@302 | 282 | asic_event( EVENT_G2_DMA0 + channel );
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nkeynes@279 | 283 | } else {
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nkeynes@302 | 284 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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nkeynes@279 | 285 | }
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nkeynes@279 | 286 | }
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nkeynes@279 | 287 | }
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nkeynes@155 | 288 |
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nkeynes@155 | 289 | void asic_ide_dma_transfer( )
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nkeynes@155 | 290 | {
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nkeynes@158 | 291 | if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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nkeynes@158 | 292 | if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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nkeynes@158 | 293 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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nkeynes@158 | 294 |
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nkeynes@158 | 295 | uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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nkeynes@158 | 296 | uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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nkeynes@158 | 297 | int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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nkeynes@158 | 298 |
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nkeynes@158 | 299 | uint32_t xfer = ide_read_data_dma( addr, length );
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nkeynes@158 | 300 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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nkeynes@158 | 301 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@158 | 302 | } else { /* 0 */
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nkeynes@158 | 303 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@155 | 304 | }
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nkeynes@155 | 305 | }
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nkeynes@155 | 306 | }
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nkeynes@155 | 307 |
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nkeynes@325 | 308 | void pvr_dma_transfer( )
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nkeynes@325 | 309 | {
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nkeynes@325 | 310 | sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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nkeynes@325 | 311 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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nkeynes@325 | 312 | char *data = alloca( count );
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nkeynes@325 | 313 | uint32_t rcount = DMAC_get_buffer( 2, data, count );
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nkeynes@325 | 314 | if( rcount != count )
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nkeynes@325 | 315 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
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nkeynes@325 | 316 |
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nkeynes@325 | 317 | pvr2_dma_write( destaddr, data, rcount );
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nkeynes@325 | 318 |
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nkeynes@325 | 319 | MMIO_WRITE( ASIC, PVRDMACTL, 0 );
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nkeynes@325 | 320 | MMIO_WRITE( ASIC, PVRDMACNT, 0 );
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nkeynes@325 | 321 | if( destaddr & 0x01000000 ) { /* Write to texture RAM */
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nkeynes@325 | 322 | MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
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nkeynes@325 | 323 | }
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nkeynes@325 | 324 | asic_event( EVENT_PVR_DMA );
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nkeynes@325 | 325 | }
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nkeynes@155 | 326 |
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nkeynes@1 | 327 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
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nkeynes@1 | 328 | {
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nkeynes@1 | 329 | switch( reg ) {
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nkeynes@125 | 330 | case PIRQ1:
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nkeynes@305 | 331 | break; /* Treat this as read-only for the moment */
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nkeynes@56 | 332 | case PIRQ0:
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nkeynes@305 | 333 | val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
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nkeynes@305 | 334 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
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nkeynes@305 | 335 | asic_check_cleared_events();
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nkeynes@305 | 336 | break;
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nkeynes@56 | 337 | case PIRQ2:
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nkeynes@305 | 338 | /* Clear any events */
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nkeynes@305 | 339 | val = MMIO_READ(ASIC, reg)&(~val);
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nkeynes@305 | 340 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@305 | 341 | if( val == 0 ) { /* all clear - clear the cascade bit */
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nkeynes@305 | 342 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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nkeynes@305 | 343 | }
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nkeynes@56 | 344 | asic_check_cleared_events();
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nkeynes@56 | 345 | break;
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nkeynes@244 | 346 | case SYSRESET:
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nkeynes@244 | 347 | if( val == 0x7611 ) {
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nkeynes@244 | 348 | dreamcast_reset();
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nkeynes@255 | 349 | sh4r.new_pc = sh4r.pc;
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nkeynes@244 | 350 | } else {
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nkeynes@244 | 351 | WARN( "Unknown value %08X written to SYSRESET port", val );
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nkeynes@244 | 352 | }
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nkeynes@244 | 353 | break;
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nkeynes@56 | 354 | case MAPLE_STATE:
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nkeynes@56 | 355 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@56 | 356 | if( val & 1 ) {
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nkeynes@56 | 357 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
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nkeynes@56 | 358 | maple_handle_buffer( maple_addr );
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nkeynes@56 | 359 | MMIO_WRITE( ASIC, reg, 0 );
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nkeynes@56 | 360 | }
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nkeynes@56 | 361 | break;
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nkeynes@325 | 362 | case PVRDMADEST:
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nkeynes@325 | 363 | MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
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nkeynes@325 | 364 | break;
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nkeynes@325 | 365 | case PVRDMACNT:
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nkeynes@325 | 366 | MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
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nkeynes@325 | 367 | break;
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nkeynes@56 | 368 | case PVRDMACTL: /* Initiate PVR DMA transfer */
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nkeynes@325 | 369 | val = val & 0x01;
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nkeynes@94 | 370 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@325 | 371 | if( val == 1 ) {
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nkeynes@325 | 372 | pvr_dma_transfer();
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nkeynes@56 | 373 | }
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nkeynes@56 | 374 | break;
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nkeynes@325 | 375 | case MAPLE_DMA:
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nkeynes@158 | 376 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@158 | 377 | break;
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nkeynes@56 | 378 | default:
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nkeynes@56 | 379 | MMIO_WRITE( ASIC, reg, val );
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nkeynes@1 | 380 | }
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nkeynes@1 | 381 | }
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nkeynes@1 | 382 |
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nkeynes@1 | 383 | int32_t mmio_region_ASIC_read( uint32_t reg )
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nkeynes@1 | 384 | {
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nkeynes@1 | 385 | int32_t val;
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nkeynes@1 | 386 | switch( reg ) {
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nkeynes@2 | 387 | /*
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nkeynes@2 | 388 | case 0x89C:
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nkeynes@2 | 389 | sh4_stop();
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nkeynes@2 | 390 | return 0x000000B;
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nkeynes@2 | 391 | */
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nkeynes@94 | 392 | case PIRQ0:
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nkeynes@94 | 393 | case PIRQ1:
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nkeynes@94 | 394 | case PIRQ2:
|
nkeynes@94 | 395 | case IRQA0:
|
nkeynes@94 | 396 | case IRQA1:
|
nkeynes@94 | 397 | case IRQA2:
|
nkeynes@94 | 398 | case IRQB0:
|
nkeynes@94 | 399 | case IRQB1:
|
nkeynes@94 | 400 | case IRQB2:
|
nkeynes@94 | 401 | case IRQC0:
|
nkeynes@94 | 402 | case IRQC1:
|
nkeynes@94 | 403 | case IRQC2:
|
nkeynes@158 | 404 | case MAPLE_STATE:
|
nkeynes@94 | 405 | val = MMIO_READ(ASIC, reg);
|
nkeynes@94 | 406 | return val;
|
nkeynes@94 | 407 | case G2STATUS:
|
nkeynes@137 | 408 | return g2_read_status();
|
nkeynes@94 | 409 | default:
|
nkeynes@94 | 410 | val = MMIO_READ(ASIC, reg);
|
nkeynes@94 | 411 | return val;
|
nkeynes@1 | 412 | }
|
nkeynes@94 | 413 |
|
nkeynes@1 | 414 | }
|
nkeynes@1 | 415 |
|
nkeynes@1 | 416 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
|
nkeynes@1 | 417 | {
|
nkeynes@244 | 418 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
|
nkeynes@244 | 419 | return; /* disabled */
|
nkeynes@244 | 420 | }
|
nkeynes@244 | 421 |
|
nkeynes@2 | 422 | switch( reg ) {
|
nkeynes@125 | 423 | case IDEALTSTATUS: /* Device control */
|
nkeynes@125 | 424 | ide_write_control( val );
|
nkeynes@125 | 425 | break;
|
nkeynes@125 | 426 | case IDEDATA:
|
nkeynes@125 | 427 | ide_write_data_pio( val );
|
nkeynes@125 | 428 | break;
|
nkeynes@125 | 429 | case IDEFEAT:
|
nkeynes@125 | 430 | if( ide_can_write_regs() )
|
nkeynes@125 | 431 | idereg.feature = (uint8_t)val;
|
nkeynes@125 | 432 | break;
|
nkeynes@125 | 433 | case IDECOUNT:
|
nkeynes@125 | 434 | if( ide_can_write_regs() )
|
nkeynes@125 | 435 | idereg.count = (uint8_t)val;
|
nkeynes@125 | 436 | break;
|
nkeynes@125 | 437 | case IDELBA0:
|
nkeynes@125 | 438 | if( ide_can_write_regs() )
|
nkeynes@125 | 439 | idereg.lba0 = (uint8_t)val;
|
nkeynes@125 | 440 | break;
|
nkeynes@125 | 441 | case IDELBA1:
|
nkeynes@125 | 442 | if( ide_can_write_regs() )
|
nkeynes@125 | 443 | idereg.lba1 = (uint8_t)val;
|
nkeynes@125 | 444 | break;
|
nkeynes@125 | 445 | case IDELBA2:
|
nkeynes@125 | 446 | if( ide_can_write_regs() )
|
nkeynes@125 | 447 | idereg.lba2 = (uint8_t)val;
|
nkeynes@125 | 448 | break;
|
nkeynes@125 | 449 | case IDEDEV:
|
nkeynes@125 | 450 | if( ide_can_write_regs() )
|
nkeynes@125 | 451 | idereg.device = (uint8_t)val;
|
nkeynes@125 | 452 | break;
|
nkeynes@125 | 453 | case IDECMD:
|
nkeynes@240 | 454 | if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
|
nkeynes@125 | 455 | ide_write_command( (uint8_t)val );
|
nkeynes@125 | 456 | }
|
nkeynes@125 | 457 | break;
|
nkeynes@334 | 458 | case IDEDMASH4:
|
nkeynes@334 | 459 | MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
|
nkeynes@334 | 460 | break;
|
nkeynes@334 | 461 | case IDEDMASIZ:
|
nkeynes@334 | 462 | MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
|
nkeynes@334 | 463 | break;
|
nkeynes@125 | 464 | case IDEDMACTL1:
|
nkeynes@125 | 465 | case IDEDMACTL2:
|
nkeynes@334 | 466 | MMIO_WRITE( EXTDMA, reg, val & 0x01 );
|
nkeynes@155 | 467 | asic_ide_dma_transfer( );
|
nkeynes@125 | 468 | break;
|
nkeynes@244 | 469 | case IDEACTIVATE:
|
nkeynes@244 | 470 | if( val == 0x001FFFFF ) {
|
nkeynes@244 | 471 | idereg.interface_enabled = TRUE;
|
nkeynes@244 | 472 | /* Conventional wisdom says that this is necessary but not
|
nkeynes@244 | 473 | * sufficient to enable the IDE interface.
|
nkeynes@244 | 474 | */
|
nkeynes@244 | 475 | } else if( val == 0x000042FE ) {
|
nkeynes@244 | 476 | idereg.interface_enabled = FALSE;
|
nkeynes@244 | 477 | }
|
nkeynes@279 | 478 | break;
|
nkeynes@302 | 479 | case G2DMA0CTL1:
|
nkeynes@302 | 480 | case G2DMA0CTL2:
|
nkeynes@279 | 481 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@279 | 482 | g2_dma_transfer( 0 );
|
nkeynes@279 | 483 | break;
|
nkeynes@302 | 484 | case G2DMA0STOP:
|
nkeynes@279 | 485 | break;
|
nkeynes@302 | 486 | case G2DMA1CTL1:
|
nkeynes@302 | 487 | case G2DMA1CTL2:
|
nkeynes@279 | 488 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@279 | 489 | g2_dma_transfer( 1 );
|
nkeynes@279 | 490 | break;
|
nkeynes@279 | 491 |
|
nkeynes@302 | 492 | case G2DMA1STOP:
|
nkeynes@279 | 493 | break;
|
nkeynes@302 | 494 | case G2DMA2CTL1:
|
nkeynes@302 | 495 | case G2DMA2CTL2:
|
nkeynes@279 | 496 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@279 | 497 | g2_dma_transfer( 2 );
|
nkeynes@279 | 498 | break;
|
nkeynes@302 | 499 | case G2DMA2STOP:
|
nkeynes@279 | 500 | break;
|
nkeynes@302 | 501 | case G2DMA3CTL1:
|
nkeynes@302 | 502 | case G2DMA3CTL2:
|
nkeynes@279 | 503 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@279 | 504 | g2_dma_transfer( 3 );
|
nkeynes@279 | 505 | break;
|
nkeynes@302 | 506 | case G2DMA3STOP:
|
nkeynes@279 | 507 | break;
|
nkeynes@279 | 508 | case PVRDMA2CTL1:
|
nkeynes@279 | 509 | case PVRDMA2CTL2:
|
nkeynes@279 | 510 | if( val != 0 ) {
|
nkeynes@279 | 511 | ERROR( "Write to unimplemented DMA control register %08X", reg );
|
nkeynes@279 | 512 | //dreamcast_stop();
|
nkeynes@279 | 513 | //sh4_stop();
|
nkeynes@279 | 514 | }
|
nkeynes@279 | 515 | break;
|
nkeynes@125 | 516 | default:
|
nkeynes@2 | 517 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@2 | 518 | }
|
nkeynes@1 | 519 | }
|
nkeynes@1 | 520 |
|
nkeynes@1 | 521 | MMIO_REGION_READ_FN( EXTDMA, reg )
|
nkeynes@1 | 522 | {
|
nkeynes@56 | 523 | uint32_t val;
|
nkeynes@244 | 524 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
|
nkeynes@244 | 525 | return 0xFFFFFFFF; /* disabled */
|
nkeynes@244 | 526 | }
|
nkeynes@244 | 527 |
|
nkeynes@1 | 528 | switch( reg ) {
|
nkeynes@158 | 529 | case IDEALTSTATUS:
|
nkeynes@158 | 530 | val = idereg.status;
|
nkeynes@158 | 531 | return val;
|
nkeynes@158 | 532 | case IDEDATA: return ide_read_data_pio( );
|
nkeynes@158 | 533 | case IDEFEAT: return idereg.error;
|
nkeynes@158 | 534 | case IDECOUNT:return idereg.count;
|
nkeynes@158 | 535 | case IDELBA0: return idereg.disc;
|
nkeynes@158 | 536 | case IDELBA1: return idereg.lba1;
|
nkeynes@158 | 537 | case IDELBA2: return idereg.lba2;
|
nkeynes@158 | 538 | case IDEDEV: return idereg.device;
|
nkeynes@158 | 539 | case IDECMD:
|
nkeynes@158 | 540 | val = ide_read_status();
|
nkeynes@158 | 541 | return val;
|
nkeynes@158 | 542 | default:
|
nkeynes@158 | 543 | val = MMIO_READ( EXTDMA, reg );
|
nkeynes@158 | 544 | return val;
|
nkeynes@1 | 545 | }
|
nkeynes@1 | 546 | }
|
nkeynes@1 | 547 |
|