nkeynes@359 | 1 | /**
|
nkeynes@401 | 2 | * $Id: sh4x86.in,v 1.15 2007-09-20 08:37:19 nkeynes Exp $
|
nkeynes@359 | 3 | *
|
nkeynes@359 | 4 | * SH4 => x86 translation. This version does no real optimization, it just
|
nkeynes@359 | 5 | * outputs straight-line x86 code - it mainly exists to provide a baseline
|
nkeynes@359 | 6 | * to test the optimizing versions against.
|
nkeynes@359 | 7 | *
|
nkeynes@359 | 8 | * Copyright (c) 2007 Nathan Keynes.
|
nkeynes@359 | 9 | *
|
nkeynes@359 | 10 | * This program is free software; you can redistribute it and/or modify
|
nkeynes@359 | 11 | * it under the terms of the GNU General Public License as published by
|
nkeynes@359 | 12 | * the Free Software Foundation; either version 2 of the License, or
|
nkeynes@359 | 13 | * (at your option) any later version.
|
nkeynes@359 | 14 | *
|
nkeynes@359 | 15 | * This program is distributed in the hope that it will be useful,
|
nkeynes@359 | 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
nkeynes@359 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
nkeynes@359 | 18 | * GNU General Public License for more details.
|
nkeynes@359 | 19 | */
|
nkeynes@359 | 20 |
|
nkeynes@368 | 21 | #include <assert.h>
|
nkeynes@388 | 22 | #include <math.h>
|
nkeynes@368 | 23 |
|
nkeynes@380 | 24 | #ifndef NDEBUG
|
nkeynes@380 | 25 | #define DEBUG_JUMPS 1
|
nkeynes@380 | 26 | #endif
|
nkeynes@380 | 27 |
|
nkeynes@368 | 28 | #include "sh4/sh4core.h"
|
nkeynes@368 | 29 | #include "sh4/sh4trans.h"
|
nkeynes@388 | 30 | #include "sh4/sh4mmio.h"
|
nkeynes@368 | 31 | #include "sh4/x86op.h"
|
nkeynes@368 | 32 | #include "clock.h"
|
nkeynes@368 | 33 |
|
nkeynes@368 | 34 | #define DEFAULT_BACKPATCH_SIZE 4096
|
nkeynes@368 | 35 |
|
nkeynes@368 | 36 | /**
|
nkeynes@368 | 37 | * Struct to manage internal translation state. This state is not saved -
|
nkeynes@368 | 38 | * it is only valid between calls to sh4_translate_begin_block() and
|
nkeynes@368 | 39 | * sh4_translate_end_block()
|
nkeynes@368 | 40 | */
|
nkeynes@368 | 41 | struct sh4_x86_state {
|
nkeynes@368 | 42 | gboolean in_delay_slot;
|
nkeynes@368 | 43 | gboolean priv_checked; /* true if we've already checked the cpu mode. */
|
nkeynes@368 | 44 | gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
|
nkeynes@388 | 45 | int exit_code;
|
nkeynes@368 | 46 |
|
nkeynes@368 | 47 | /* Allocated memory for the (block-wide) back-patch list */
|
nkeynes@368 | 48 | uint32_t **backpatch_list;
|
nkeynes@368 | 49 | uint32_t backpatch_posn;
|
nkeynes@368 | 50 | uint32_t backpatch_size;
|
nkeynes@368 | 51 | };
|
nkeynes@368 | 52 |
|
nkeynes@368 | 53 | #define EXIT_DATA_ADDR_READ 0
|
nkeynes@368 | 54 | #define EXIT_DATA_ADDR_WRITE 7
|
nkeynes@368 | 55 | #define EXIT_ILLEGAL 14
|
nkeynes@368 | 56 | #define EXIT_SLOT_ILLEGAL 21
|
nkeynes@368 | 57 | #define EXIT_FPU_DISABLED 28
|
nkeynes@368 | 58 | #define EXIT_SLOT_FPU_DISABLED 35
|
nkeynes@368 | 59 |
|
nkeynes@368 | 60 | static struct sh4_x86_state sh4_x86;
|
nkeynes@368 | 61 |
|
nkeynes@388 | 62 | static uint32_t max_int = 0x7FFFFFFF;
|
nkeynes@388 | 63 | static uint32_t min_int = 0x80000000;
|
nkeynes@394 | 64 | static uint32_t save_fcw; /* save value for fpu control word */
|
nkeynes@394 | 65 | static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
|
nkeynes@386 | 66 |
|
nkeynes@368 | 67 | void sh4_x86_init()
|
nkeynes@368 | 68 | {
|
nkeynes@368 | 69 | sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
|
nkeynes@368 | 70 | sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(uint32_t *);
|
nkeynes@368 | 71 | }
|
nkeynes@368 | 72 |
|
nkeynes@368 | 73 |
|
nkeynes@368 | 74 | static void sh4_x86_add_backpatch( uint8_t *ptr )
|
nkeynes@368 | 75 | {
|
nkeynes@368 | 76 | if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
|
nkeynes@368 | 77 | sh4_x86.backpatch_size <<= 1;
|
nkeynes@368 | 78 | sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, sh4_x86.backpatch_size * sizeof(uint32_t *) );
|
nkeynes@368 | 79 | assert( sh4_x86.backpatch_list != NULL );
|
nkeynes@368 | 80 | }
|
nkeynes@368 | 81 | sh4_x86.backpatch_list[sh4_x86.backpatch_posn++] = (uint32_t *)ptr;
|
nkeynes@368 | 82 | }
|
nkeynes@368 | 83 |
|
nkeynes@368 | 84 | static void sh4_x86_do_backpatch( uint8_t *reloc_base )
|
nkeynes@368 | 85 | {
|
nkeynes@368 | 86 | unsigned int i;
|
nkeynes@368 | 87 | for( i=0; i<sh4_x86.backpatch_posn; i++ ) {
|
nkeynes@374 | 88 | *sh4_x86.backpatch_list[i] += (reloc_base - ((uint8_t *)sh4_x86.backpatch_list[i]) - 4);
|
nkeynes@368 | 89 | }
|
nkeynes@368 | 90 | }
|
nkeynes@368 | 91 |
|
nkeynes@359 | 92 | /**
|
nkeynes@359 | 93 | * Emit an instruction to load an SH4 reg into a real register
|
nkeynes@359 | 94 | */
|
nkeynes@359 | 95 | static inline void load_reg( int x86reg, int sh4reg )
|
nkeynes@359 | 96 | {
|
nkeynes@359 | 97 | /* mov [bp+n], reg */
|
nkeynes@361 | 98 | OP(0x8B);
|
nkeynes@361 | 99 | OP(0x45 + (x86reg<<3));
|
nkeynes@359 | 100 | OP(REG_OFFSET(r[sh4reg]));
|
nkeynes@359 | 101 | }
|
nkeynes@359 | 102 |
|
nkeynes@374 | 103 | static inline void load_reg16s( int x86reg, int sh4reg )
|
nkeynes@368 | 104 | {
|
nkeynes@374 | 105 | OP(0x0F);
|
nkeynes@374 | 106 | OP(0xBF);
|
nkeynes@374 | 107 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
|
nkeynes@368 | 108 | }
|
nkeynes@368 | 109 |
|
nkeynes@374 | 110 | static inline void load_reg16u( int x86reg, int sh4reg )
|
nkeynes@368 | 111 | {
|
nkeynes@374 | 112 | OP(0x0F);
|
nkeynes@374 | 113 | OP(0xB7);
|
nkeynes@374 | 114 | MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
|
nkeynes@374 | 115 |
|
nkeynes@368 | 116 | }
|
nkeynes@368 | 117 |
|
nkeynes@380 | 118 | #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
|
nkeynes@380 | 119 | #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
|
nkeynes@359 | 120 | /**
|
nkeynes@359 | 121 | * Emit an instruction to load an immediate value into a register
|
nkeynes@359 | 122 | */
|
nkeynes@359 | 123 | static inline void load_imm32( int x86reg, uint32_t value ) {
|
nkeynes@359 | 124 | /* mov #value, reg */
|
nkeynes@359 | 125 | OP(0xB8 + x86reg);
|
nkeynes@359 | 126 | OP32(value);
|
nkeynes@359 | 127 | }
|
nkeynes@359 | 128 |
|
nkeynes@359 | 129 | /**
|
nkeynes@359 | 130 | * Emit an instruction to store an SH4 reg (RN)
|
nkeynes@359 | 131 | */
|
nkeynes@359 | 132 | void static inline store_reg( int x86reg, int sh4reg ) {
|
nkeynes@359 | 133 | /* mov reg, [bp+n] */
|
nkeynes@361 | 134 | OP(0x89);
|
nkeynes@361 | 135 | OP(0x45 + (x86reg<<3));
|
nkeynes@359 | 136 | OP(REG_OFFSET(r[sh4reg]));
|
nkeynes@359 | 137 | }
|
nkeynes@374 | 138 |
|
nkeynes@374 | 139 | #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
|
nkeynes@374 | 140 |
|
nkeynes@375 | 141 | /**
|
nkeynes@375 | 142 | * Load an FR register (single-precision floating point) into an integer x86
|
nkeynes@375 | 143 | * register (eg for register-to-register moves)
|
nkeynes@375 | 144 | */
|
nkeynes@375 | 145 | void static inline load_fr( int bankreg, int x86reg, int frm )
|
nkeynes@375 | 146 | {
|
nkeynes@375 | 147 | OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
|
nkeynes@375 | 148 | }
|
nkeynes@375 | 149 |
|
nkeynes@375 | 150 | /**
|
nkeynes@375 | 151 | * Store an FR register (single-precision floating point) into an integer x86
|
nkeynes@375 | 152 | * register (eg for register-to-register moves)
|
nkeynes@375 | 153 | */
|
nkeynes@375 | 154 | void static inline store_fr( int bankreg, int x86reg, int frn )
|
nkeynes@375 | 155 | {
|
nkeynes@375 | 156 | OP(0x89); OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
|
nkeynes@375 | 157 | }
|
nkeynes@375 | 158 |
|
nkeynes@375 | 159 |
|
nkeynes@375 | 160 | /**
|
nkeynes@375 | 161 | * Load a pointer to the back fp back into the specified x86 register. The
|
nkeynes@375 | 162 | * bankreg must have been previously loaded with FPSCR.
|
nkeynes@388 | 163 | * NB: 12 bytes
|
nkeynes@375 | 164 | */
|
nkeynes@374 | 165 | static inline void load_xf_bank( int bankreg )
|
nkeynes@374 | 166 | {
|
nkeynes@386 | 167 | NOT_r32( bankreg );
|
nkeynes@374 | 168 | SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
|
nkeynes@374 | 169 | AND_imm8s_r32( 0x40, bankreg ); // Complete extraction
|
nkeynes@374 | 170 | OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
|
nkeynes@374 | 171 | }
|
nkeynes@374 | 172 |
|
nkeynes@375 | 173 | /**
|
nkeynes@386 | 174 | * Update the fr_bank pointer based on the current fpscr value.
|
nkeynes@386 | 175 | */
|
nkeynes@386 | 176 | static inline void update_fr_bank( int fpscrreg )
|
nkeynes@386 | 177 | {
|
nkeynes@386 | 178 | SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
|
nkeynes@386 | 179 | AND_imm8s_r32( 0x40, fpscrreg ); // Complete extraction
|
nkeynes@386 | 180 | OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
|
nkeynes@386 | 181 | store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
|
nkeynes@386 | 182 | }
|
nkeynes@386 | 183 | /**
|
nkeynes@377 | 184 | * Push FPUL (as a 32-bit float) onto the FPU stack
|
nkeynes@377 | 185 | */
|
nkeynes@377 | 186 | static inline void push_fpul( )
|
nkeynes@377 | 187 | {
|
nkeynes@377 | 188 | OP(0xD9); OP(0x45); OP(R_FPUL);
|
nkeynes@377 | 189 | }
|
nkeynes@377 | 190 |
|
nkeynes@377 | 191 | /**
|
nkeynes@377 | 192 | * Pop FPUL (as a 32-bit float) from the FPU stack
|
nkeynes@377 | 193 | */
|
nkeynes@377 | 194 | static inline void pop_fpul( )
|
nkeynes@377 | 195 | {
|
nkeynes@377 | 196 | OP(0xD9); OP(0x5D); OP(R_FPUL);
|
nkeynes@377 | 197 | }
|
nkeynes@377 | 198 |
|
nkeynes@377 | 199 | /**
|
nkeynes@375 | 200 | * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
|
nkeynes@375 | 201 | * with the location of the current fp bank.
|
nkeynes@375 | 202 | */
|
nkeynes@374 | 203 | static inline void push_fr( int bankreg, int frm )
|
nkeynes@374 | 204 | {
|
nkeynes@374 | 205 | OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2); // FLD.S [bankreg + frm^1*4]
|
nkeynes@374 | 206 | }
|
nkeynes@374 | 207 |
|
nkeynes@375 | 208 | /**
|
nkeynes@375 | 209 | * Pop a 32-bit float from the FPU stack and store it back into the fp bank,
|
nkeynes@375 | 210 | * with bankreg previously loaded with the location of the current fp bank.
|
nkeynes@375 | 211 | */
|
nkeynes@374 | 212 | static inline void pop_fr( int bankreg, int frm )
|
nkeynes@374 | 213 | {
|
nkeynes@374 | 214 | OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
|
nkeynes@374 | 215 | }
|
nkeynes@374 | 216 |
|
nkeynes@375 | 217 | /**
|
nkeynes@375 | 218 | * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
|
nkeynes@375 | 219 | * with the location of the current fp bank.
|
nkeynes@375 | 220 | */
|
nkeynes@374 | 221 | static inline void push_dr( int bankreg, int frm )
|
nkeynes@374 | 222 | {
|
nkeynes@375 | 223 | OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
|
nkeynes@374 | 224 | }
|
nkeynes@374 | 225 |
|
nkeynes@374 | 226 | static inline void pop_dr( int bankreg, int frm )
|
nkeynes@374 | 227 | {
|
nkeynes@375 | 228 | OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
|
nkeynes@374 | 229 | }
|
nkeynes@374 | 230 |
|
nkeynes@361 | 231 | /**
|
nkeynes@361 | 232 | * Note: clobbers EAX to make the indirect call - this isn't usually
|
nkeynes@361 | 233 | * a problem since the callee will usually clobber it anyway.
|
nkeynes@361 | 234 | */
|
nkeynes@361 | 235 | static inline void call_func0( void *ptr )
|
nkeynes@361 | 236 | {
|
nkeynes@361 | 237 | load_imm32(R_EAX, (uint32_t)ptr);
|
nkeynes@368 | 238 | CALL_r32(R_EAX);
|
nkeynes@361 | 239 | }
|
nkeynes@361 | 240 |
|
nkeynes@361 | 241 | static inline void call_func1( void *ptr, int arg1 )
|
nkeynes@361 | 242 | {
|
nkeynes@361 | 243 | PUSH_r32(arg1);
|
nkeynes@361 | 244 | call_func0(ptr);
|
nkeynes@377 | 245 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@361 | 246 | }
|
nkeynes@361 | 247 |
|
nkeynes@361 | 248 | static inline void call_func2( void *ptr, int arg1, int arg2 )
|
nkeynes@361 | 249 | {
|
nkeynes@361 | 250 | PUSH_r32(arg2);
|
nkeynes@361 | 251 | PUSH_r32(arg1);
|
nkeynes@361 | 252 | call_func0(ptr);
|
nkeynes@377 | 253 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 254 | }
|
nkeynes@375 | 255 |
|
nkeynes@375 | 256 | /**
|
nkeynes@375 | 257 | * Write a double (64-bit) value into memory, with the first word in arg2a, and
|
nkeynes@375 | 258 | * the second in arg2b
|
nkeynes@375 | 259 | * NB: 30 bytes
|
nkeynes@375 | 260 | */
|
nkeynes@375 | 261 | static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
|
nkeynes@375 | 262 | {
|
nkeynes@375 | 263 | ADD_imm8s_r32( 4, addr );
|
nkeynes@386 | 264 | PUSH_r32(arg2b);
|
nkeynes@375 | 265 | PUSH_r32(addr);
|
nkeynes@375 | 266 | ADD_imm8s_r32( -4, addr );
|
nkeynes@386 | 267 | PUSH_r32(arg2a);
|
nkeynes@375 | 268 | PUSH_r32(addr);
|
nkeynes@375 | 269 | call_func0(sh4_write_long);
|
nkeynes@377 | 270 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 271 | call_func0(sh4_write_long);
|
nkeynes@377 | 272 | ADD_imm8s_r32( 8, R_ESP );
|
nkeynes@375 | 273 | }
|
nkeynes@375 | 274 |
|
nkeynes@375 | 275 | /**
|
nkeynes@375 | 276 | * Read a double (64-bit) value from memory, writing the first word into arg2a
|
nkeynes@375 | 277 | * and the second into arg2b. The addr must not be in EAX
|
nkeynes@375 | 278 | * NB: 27 bytes
|
nkeynes@375 | 279 | */
|
nkeynes@375 | 280 | static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
|
nkeynes@375 | 281 | {
|
nkeynes@375 | 282 | PUSH_r32(addr);
|
nkeynes@375 | 283 | call_func0(sh4_read_long);
|
nkeynes@375 | 284 | POP_r32(addr);
|
nkeynes@375 | 285 | PUSH_r32(R_EAX);
|
nkeynes@375 | 286 | ADD_imm8s_r32( 4, addr );
|
nkeynes@375 | 287 | PUSH_r32(addr);
|
nkeynes@375 | 288 | call_func0(sh4_read_long);
|
nkeynes@377 | 289 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@375 | 290 | MOV_r32_r32( R_EAX, arg2b );
|
nkeynes@375 | 291 | POP_r32(arg2a);
|
nkeynes@361 | 292 | }
|
nkeynes@361 | 293 |
|
nkeynes@368 | 294 | /* Exception checks - Note that all exception checks will clobber EAX */
|
nkeynes@368 | 295 | static void check_priv( )
|
nkeynes@368 | 296 | {
|
nkeynes@368 | 297 | if( !sh4_x86.priv_checked ) {
|
nkeynes@368 | 298 | sh4_x86.priv_checked = TRUE;
|
nkeynes@368 | 299 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 300 | AND_imm32_r32( SR_MD, R_EAX );
|
nkeynes@368 | 301 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 302 | JE_exit( EXIT_SLOT_ILLEGAL );
|
nkeynes@368 | 303 | } else {
|
nkeynes@368 | 304 | JE_exit( EXIT_ILLEGAL );
|
nkeynes@368 | 305 | }
|
nkeynes@368 | 306 | }
|
nkeynes@368 | 307 | }
|
nkeynes@368 | 308 |
|
nkeynes@368 | 309 | static void check_fpuen( )
|
nkeynes@368 | 310 | {
|
nkeynes@368 | 311 | if( !sh4_x86.fpuen_checked ) {
|
nkeynes@368 | 312 | sh4_x86.fpuen_checked = TRUE;
|
nkeynes@368 | 313 | load_spreg( R_EAX, R_SR );
|
nkeynes@368 | 314 | AND_imm32_r32( SR_FD, R_EAX );
|
nkeynes@368 | 315 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@368 | 316 | JNE_exit(EXIT_SLOT_FPU_DISABLED);
|
nkeynes@368 | 317 | } else {
|
nkeynes@368 | 318 | JNE_exit(EXIT_FPU_DISABLED);
|
nkeynes@368 | 319 | }
|
nkeynes@368 | 320 | }
|
nkeynes@368 | 321 | }
|
nkeynes@368 | 322 |
|
nkeynes@368 | 323 | static void check_ralign16( int x86reg )
|
nkeynes@368 | 324 | {
|
nkeynes@368 | 325 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 326 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 327 | }
|
nkeynes@368 | 328 |
|
nkeynes@368 | 329 | static void check_walign16( int x86reg )
|
nkeynes@368 | 330 | {
|
nkeynes@368 | 331 | TEST_imm32_r32( 0x00000001, x86reg );
|
nkeynes@368 | 332 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 333 | }
|
nkeynes@368 | 334 |
|
nkeynes@368 | 335 | static void check_ralign32( int x86reg )
|
nkeynes@368 | 336 | {
|
nkeynes@368 | 337 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 338 | JNE_exit(EXIT_DATA_ADDR_READ);
|
nkeynes@368 | 339 | }
|
nkeynes@368 | 340 | static void check_walign32( int x86reg )
|
nkeynes@368 | 341 | {
|
nkeynes@368 | 342 | TEST_imm32_r32( 0x00000003, x86reg );
|
nkeynes@368 | 343 | JNE_exit(EXIT_DATA_ADDR_WRITE);
|
nkeynes@368 | 344 | }
|
nkeynes@368 | 345 |
|
nkeynes@361 | 346 | #define UNDEF()
|
nkeynes@361 | 347 | #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
|
nkeynes@361 | 348 | #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 349 | #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 350 | #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
|
nkeynes@361 | 351 | #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
|
nkeynes@361 | 352 | #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
|
nkeynes@361 | 353 | #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
|
nkeynes@361 | 354 |
|
nkeynes@386 | 355 | #define SLOTILLEGAL() JMP_exit(EXIT_SLOT_ILLEGAL); sh4_x86.in_delay_slot = FALSE; return 1;
|
nkeynes@368 | 356 |
|
nkeynes@368 | 357 |
|
nkeynes@359 | 358 |
|
nkeynes@359 | 359 | /**
|
nkeynes@359 | 360 | * Emit the 'start of block' assembly. Sets up the stack frame and save
|
nkeynes@359 | 361 | * SI/DI as required
|
nkeynes@359 | 362 | */
|
nkeynes@368 | 363 | void sh4_translate_begin_block()
|
nkeynes@368 | 364 | {
|
nkeynes@368 | 365 | PUSH_r32(R_EBP);
|
nkeynes@359 | 366 | /* mov &sh4r, ebp */
|
nkeynes@359 | 367 | load_imm32( R_EBP, (uint32_t)&sh4r );
|
nkeynes@374 | 368 | PUSH_r32(R_EDI);
|
nkeynes@368 | 369 | PUSH_r32(R_ESI);
|
nkeynes@380 | 370 | XOR_r32_r32(R_ESI, R_ESI);
|
nkeynes@368 | 371 |
|
nkeynes@368 | 372 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@368 | 373 | sh4_x86.priv_checked = FALSE;
|
nkeynes@368 | 374 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@368 | 375 | sh4_x86.backpatch_posn = 0;
|
nkeynes@388 | 376 | sh4_x86.exit_code = 1;
|
nkeynes@368 | 377 | }
|
nkeynes@359 | 378 |
|
nkeynes@368 | 379 | /**
|
nkeynes@368 | 380 | * Exit the block early (ie branch out), conditionally or otherwise
|
nkeynes@368 | 381 | */
|
nkeynes@374 | 382 | void exit_block( )
|
nkeynes@368 | 383 | {
|
nkeynes@374 | 384 | store_spreg( R_EDI, REG_OFFSET(pc) );
|
nkeynes@368 | 385 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@368 | 386 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@368 | 387 | MUL_r32( R_ESI );
|
nkeynes@368 | 388 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 389 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 390 | load_imm32( R_EAX, sh4_x86.exit_code );
|
nkeynes@374 | 391 | POP_r32(R_ESI);
|
nkeynes@374 | 392 | POP_r32(R_EDI);
|
nkeynes@374 | 393 | POP_r32(R_EBP);
|
nkeynes@368 | 394 | RET();
|
nkeynes@359 | 395 | }
|
nkeynes@359 | 396 |
|
nkeynes@359 | 397 | /**
|
nkeynes@359 | 398 | * Flush any open regs back to memory, restore SI/DI/, update PC, etc
|
nkeynes@359 | 399 | */
|
nkeynes@359 | 400 | void sh4_translate_end_block( sh4addr_t pc ) {
|
nkeynes@368 | 401 | assert( !sh4_x86.in_delay_slot ); // should never stop here
|
nkeynes@368 | 402 | // Normal termination - save PC, cycle count
|
nkeynes@374 | 403 | exit_block( );
|
nkeynes@359 | 404 |
|
nkeynes@388 | 405 | if( sh4_x86.backpatch_posn != 0 ) {
|
nkeynes@388 | 406 | uint8_t *end_ptr = xlat_output;
|
nkeynes@388 | 407 | // Exception termination. Jump block for various exception codes:
|
nkeynes@388 | 408 | PUSH_imm32( EXC_DATA_ADDR_READ );
|
nkeynes@388 | 409 | JMP_rel8( 33, target1 );
|
nkeynes@388 | 410 | PUSH_imm32( EXC_DATA_ADDR_WRITE );
|
nkeynes@388 | 411 | JMP_rel8( 26, target2 );
|
nkeynes@388 | 412 | PUSH_imm32( EXC_ILLEGAL );
|
nkeynes@388 | 413 | JMP_rel8( 19, target3 );
|
nkeynes@388 | 414 | PUSH_imm32( EXC_SLOT_ILLEGAL );
|
nkeynes@388 | 415 | JMP_rel8( 12, target4 );
|
nkeynes@388 | 416 | PUSH_imm32( EXC_FPU_DISABLED );
|
nkeynes@388 | 417 | JMP_rel8( 5, target5 );
|
nkeynes@388 | 418 | PUSH_imm32( EXC_SLOT_FPU_DISABLED );
|
nkeynes@388 | 419 | // target
|
nkeynes@388 | 420 | JMP_TARGET(target1);
|
nkeynes@388 | 421 | JMP_TARGET(target2);
|
nkeynes@388 | 422 | JMP_TARGET(target3);
|
nkeynes@388 | 423 | JMP_TARGET(target4);
|
nkeynes@388 | 424 | JMP_TARGET(target5);
|
nkeynes@388 | 425 | load_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 426 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 427 | ADD_r32_r32( R_ESI, R_ECX );
|
nkeynes@388 | 428 | store_spreg( R_ECX, REG_OFFSET(pc) );
|
nkeynes@388 | 429 | MOV_moff32_EAX( (uint32_t)&sh4_cpu_period );
|
nkeynes@388 | 430 | load_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 431 | MUL_r32( R_ESI );
|
nkeynes@388 | 432 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@388 | 433 | store_spreg( R_ECX, REG_OFFSET(slice_cycle) );
|
nkeynes@388 | 434 |
|
nkeynes@388 | 435 | load_imm32( R_EAX, (uint32_t)sh4_raise_exception ); // 6
|
nkeynes@388 | 436 | CALL_r32( R_EAX ); // 2
|
nkeynes@388 | 437 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@388 | 438 | POP_r32(R_ESI);
|
nkeynes@388 | 439 | POP_r32(R_EDI);
|
nkeynes@388 | 440 | POP_r32(R_EBP);
|
nkeynes@388 | 441 | RET();
|
nkeynes@368 | 442 |
|
nkeynes@388 | 443 | sh4_x86_do_backpatch( end_ptr );
|
nkeynes@388 | 444 | }
|
nkeynes@368 | 445 |
|
nkeynes@359 | 446 | }
|
nkeynes@359 | 447 |
|
nkeynes@388 | 448 |
|
nkeynes@388 | 449 | extern uint16_t *sh4_icache;
|
nkeynes@388 | 450 | extern uint32_t sh4_icache_addr;
|
nkeynes@388 | 451 |
|
nkeynes@359 | 452 | /**
|
nkeynes@359 | 453 | * Translate a single instruction. Delayed branches are handled specially
|
nkeynes@359 | 454 | * by translating both branch and delayed instruction as a single unit (as
|
nkeynes@359 | 455 | *
|
nkeynes@359 | 456 | *
|
nkeynes@359 | 457 | * @return true if the instruction marks the end of a basic block
|
nkeynes@359 | 458 | * (eg a branch or
|
nkeynes@359 | 459 | */
|
nkeynes@359 | 460 | uint32_t sh4_x86_translate_instruction( uint32_t pc )
|
nkeynes@359 | 461 | {
|
nkeynes@388 | 462 | uint32_t ir;
|
nkeynes@388 | 463 | /* Read instruction */
|
nkeynes@388 | 464 | uint32_t pageaddr = pc >> 12;
|
nkeynes@388 | 465 | if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
|
nkeynes@388 | 466 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 467 | } else {
|
nkeynes@388 | 468 | sh4_icache = (uint16_t *)mem_get_page(pc);
|
nkeynes@388 | 469 | if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
|
nkeynes@388 | 470 | /* If someone's actually been so daft as to try to execute out of an IO
|
nkeynes@388 | 471 | * region, fallback on the full-blown memory read
|
nkeynes@388 | 472 | */
|
nkeynes@388 | 473 | sh4_icache = NULL;
|
nkeynes@388 | 474 | ir = sh4_read_word(pc);
|
nkeynes@388 | 475 | } else {
|
nkeynes@388 | 476 | sh4_icache_addr = pageaddr;
|
nkeynes@388 | 477 | ir = sh4_icache[(pc&0xFFF)>>1];
|
nkeynes@388 | 478 | }
|
nkeynes@388 | 479 | }
|
nkeynes@388 | 480 |
|
nkeynes@359 | 481 | %%
|
nkeynes@359 | 482 | /* ALU operations */
|
nkeynes@359 | 483 | ADD Rm, Rn {:
|
nkeynes@359 | 484 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 485 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 486 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 487 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 488 | :}
|
nkeynes@359 | 489 | ADD #imm, Rn {:
|
nkeynes@359 | 490 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 491 | ADD_imm8s_r32( imm, R_EAX );
|
nkeynes@359 | 492 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 493 | :}
|
nkeynes@359 | 494 | ADDC Rm, Rn {:
|
nkeynes@359 | 495 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 496 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 497 | LDC_t();
|
nkeynes@359 | 498 | ADC_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 499 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 500 | SETC_t();
|
nkeynes@359 | 501 | :}
|
nkeynes@359 | 502 | ADDV Rm, Rn {:
|
nkeynes@359 | 503 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 504 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 505 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 506 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 507 | SETO_t();
|
nkeynes@359 | 508 | :}
|
nkeynes@359 | 509 | AND Rm, Rn {:
|
nkeynes@359 | 510 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 511 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 512 | AND_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 513 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 514 | :}
|
nkeynes@359 | 515 | AND #imm, R0 {:
|
nkeynes@359 | 516 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 517 | AND_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 518 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 519 | :}
|
nkeynes@359 | 520 | AND.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 521 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 522 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 523 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 524 | PUSH_r32(R_ECX);
|
nkeynes@386 | 525 | call_func0(sh4_read_byte);
|
nkeynes@386 | 526 | POP_r32(R_ECX);
|
nkeynes@386 | 527 | AND_imm32_r32(imm, R_EAX );
|
nkeynes@359 | 528 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 529 | :}
|
nkeynes@359 | 530 | CMP/EQ Rm, Rn {:
|
nkeynes@359 | 531 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 532 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 533 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 534 | SETE_t();
|
nkeynes@359 | 535 | :}
|
nkeynes@359 | 536 | CMP/EQ #imm, R0 {:
|
nkeynes@359 | 537 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 538 | CMP_imm8s_r32(imm, R_EAX);
|
nkeynes@359 | 539 | SETE_t();
|
nkeynes@359 | 540 | :}
|
nkeynes@359 | 541 | CMP/GE Rm, Rn {:
|
nkeynes@359 | 542 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 543 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 544 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 545 | SETGE_t();
|
nkeynes@359 | 546 | :}
|
nkeynes@359 | 547 | CMP/GT Rm, Rn {:
|
nkeynes@359 | 548 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 549 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 550 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 551 | SETG_t();
|
nkeynes@359 | 552 | :}
|
nkeynes@359 | 553 | CMP/HI Rm, Rn {:
|
nkeynes@359 | 554 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 555 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 556 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 557 | SETA_t();
|
nkeynes@359 | 558 | :}
|
nkeynes@359 | 559 | CMP/HS Rm, Rn {:
|
nkeynes@359 | 560 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 561 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 562 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 563 | SETAE_t();
|
nkeynes@359 | 564 | :}
|
nkeynes@359 | 565 | CMP/PL Rn {:
|
nkeynes@359 | 566 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 567 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 568 | SETG_t();
|
nkeynes@359 | 569 | :}
|
nkeynes@359 | 570 | CMP/PZ Rn {:
|
nkeynes@359 | 571 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 572 | CMP_imm8s_r32( 0, R_EAX );
|
nkeynes@359 | 573 | SETGE_t();
|
nkeynes@359 | 574 | :}
|
nkeynes@361 | 575 | CMP/STR Rm, Rn {:
|
nkeynes@368 | 576 | load_reg( R_EAX, Rm );
|
nkeynes@368 | 577 | load_reg( R_ECX, Rn );
|
nkeynes@368 | 578 | XOR_r32_r32( R_ECX, R_EAX );
|
nkeynes@368 | 579 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@380 | 580 | JE_rel8(13, target1);
|
nkeynes@368 | 581 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 582 | JE_rel8(9, target2);
|
nkeynes@368 | 583 | SHR_imm8_r32( 16, R_EAX ); // 3
|
nkeynes@368 | 584 | TEST_r8_r8( R_AL, R_AL ); // 2
|
nkeynes@380 | 585 | JE_rel8(2, target3);
|
nkeynes@368 | 586 | TEST_r8_r8( R_AH, R_AH ); // 2
|
nkeynes@380 | 587 | JMP_TARGET(target1);
|
nkeynes@380 | 588 | JMP_TARGET(target2);
|
nkeynes@380 | 589 | JMP_TARGET(target3);
|
nkeynes@368 | 590 | SETE_t();
|
nkeynes@361 | 591 | :}
|
nkeynes@361 | 592 | DIV0S Rm, Rn {:
|
nkeynes@361 | 593 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 594 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 595 | SHR_imm8_r32( 31, R_EAX );
|
nkeynes@361 | 596 | SHR_imm8_r32( 31, R_ECX );
|
nkeynes@361 | 597 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 598 | store_spreg( R_ECX, R_Q );
|
nkeynes@361 | 599 | CMP_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 600 | SETNE_t();
|
nkeynes@361 | 601 | :}
|
nkeynes@361 | 602 | DIV0U {:
|
nkeynes@361 | 603 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@361 | 604 | store_spreg( R_EAX, R_Q );
|
nkeynes@361 | 605 | store_spreg( R_EAX, R_M );
|
nkeynes@361 | 606 | store_spreg( R_EAX, R_T );
|
nkeynes@361 | 607 | :}
|
nkeynes@386 | 608 | DIV1 Rm, Rn {:
|
nkeynes@386 | 609 | load_spreg( R_ECX, R_M );
|
nkeynes@386 | 610 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 611 | LDC_t();
|
nkeynes@386 | 612 | RCL1_r32( R_EAX );
|
nkeynes@386 | 613 | SETC_r8( R_DL ); // Q'
|
nkeynes@386 | 614 | CMP_sh4r_r32( R_Q, R_ECX );
|
nkeynes@386 | 615 | JE_rel8(5, mqequal);
|
nkeynes@386 | 616 | ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 617 | JMP_rel8(3, end);
|
nkeynes@380 | 618 | JMP_TARGET(mqequal);
|
nkeynes@386 | 619 | SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
|
nkeynes@386 | 620 | JMP_TARGET(end);
|
nkeynes@386 | 621 | store_reg( R_EAX, Rn ); // Done with Rn now
|
nkeynes@386 | 622 | SETC_r8(R_AL); // tmp1
|
nkeynes@386 | 623 | XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
|
nkeynes@386 | 624 | XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
|
nkeynes@386 | 625 | store_spreg( R_ECX, R_Q );
|
nkeynes@386 | 626 | XOR_imm8s_r32( 1, R_AL ); // T = !Q'
|
nkeynes@386 | 627 | MOVZX_r8_r32( R_AL, R_EAX );
|
nkeynes@386 | 628 | store_spreg( R_EAX, R_T );
|
nkeynes@374 | 629 | :}
|
nkeynes@361 | 630 | DMULS.L Rm, Rn {:
|
nkeynes@361 | 631 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 632 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 633 | IMUL_r32(R_ECX);
|
nkeynes@361 | 634 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 635 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 636 | :}
|
nkeynes@361 | 637 | DMULU.L Rm, Rn {:
|
nkeynes@361 | 638 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 639 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 640 | MUL_r32(R_ECX);
|
nkeynes@361 | 641 | store_spreg( R_EDX, R_MACH );
|
nkeynes@361 | 642 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 643 | :}
|
nkeynes@359 | 644 | DT Rn {:
|
nkeynes@359 | 645 | load_reg( R_EAX, Rn );
|
nkeynes@382 | 646 | ADD_imm8s_r32( -1, R_EAX );
|
nkeynes@359 | 647 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 648 | SETE_t();
|
nkeynes@359 | 649 | :}
|
nkeynes@359 | 650 | EXTS.B Rm, Rn {:
|
nkeynes@359 | 651 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 652 | MOVSX_r8_r32( R_EAX, R_EAX );
|
nkeynes@359 | 653 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 654 | :}
|
nkeynes@361 | 655 | EXTS.W Rm, Rn {:
|
nkeynes@361 | 656 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 657 | MOVSX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 658 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 659 | :}
|
nkeynes@361 | 660 | EXTU.B Rm, Rn {:
|
nkeynes@361 | 661 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 662 | MOVZX_r8_r32( R_EAX, R_EAX );
|
nkeynes@361 | 663 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 664 | :}
|
nkeynes@361 | 665 | EXTU.W Rm, Rn {:
|
nkeynes@361 | 666 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 667 | MOVZX_r16_r32( R_EAX, R_EAX );
|
nkeynes@361 | 668 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 669 | :}
|
nkeynes@386 | 670 | MAC.L @Rm+, @Rn+ {:
|
nkeynes@386 | 671 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 672 | check_ralign32( R_ECX );
|
nkeynes@386 | 673 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 674 | check_ralign32( R_ECX );
|
nkeynes@386 | 675 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 676 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 677 | PUSH_r32( R_EAX );
|
nkeynes@386 | 678 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 679 | ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 680 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 681 | POP_r32( R_ECX );
|
nkeynes@386 | 682 | IMUL_r32( R_ECX );
|
nkeynes@386 | 683 | ADD_r32_sh4r( R_EAX, R_MACL );
|
nkeynes@386 | 684 | ADC_r32_sh4r( R_EDX, R_MACH );
|
nkeynes@386 | 685 |
|
nkeynes@386 | 686 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 687 | TEST_r32_r32(R_ECX, R_ECX);
|
nkeynes@386 | 688 | JE_rel8( 7, nosat );
|
nkeynes@386 | 689 | call_func0( signsat48 );
|
nkeynes@386 | 690 | JMP_TARGET( nosat );
|
nkeynes@386 | 691 | :}
|
nkeynes@386 | 692 | MAC.W @Rm+, @Rn+ {:
|
nkeynes@386 | 693 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 694 | check_ralign16( R_ECX );
|
nkeynes@386 | 695 | load_reg( R_ECX, Rn );
|
nkeynes@386 | 696 | check_ralign16( R_ECX );
|
nkeynes@386 | 697 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
|
nkeynes@386 | 698 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 699 | PUSH_r32( R_EAX );
|
nkeynes@386 | 700 | load_reg( R_ECX, Rm );
|
nkeynes@386 | 701 | ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
|
nkeynes@386 | 702 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@386 | 703 | POP_r32( R_ECX );
|
nkeynes@386 | 704 | IMUL_r32( R_ECX );
|
nkeynes@386 | 705 |
|
nkeynes@386 | 706 | load_spreg( R_ECX, R_S );
|
nkeynes@386 | 707 | TEST_r32_r32( R_ECX, R_ECX );
|
nkeynes@386 | 708 | JE_rel8( 47, nosat );
|
nkeynes@386 | 709 |
|
nkeynes@386 | 710 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 711 | JNO_rel8( 51, end ); // 2
|
nkeynes@386 | 712 | load_imm32( R_EDX, 1 ); // 5
|
nkeynes@386 | 713 | store_spreg( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 714 | JS_rel8( 13, positive ); // 2
|
nkeynes@386 | 715 | load_imm32( R_EAX, 0x80000000 );// 5
|
nkeynes@386 | 716 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 717 | JMP_rel8( 25, end2 ); // 2
|
nkeynes@386 | 718 |
|
nkeynes@386 | 719 | JMP_TARGET(positive);
|
nkeynes@386 | 720 | load_imm32( R_EAX, 0x7FFFFFFF );// 5
|
nkeynes@386 | 721 | store_spreg( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 722 | JMP_rel8( 12, end3); // 2
|
nkeynes@386 | 723 |
|
nkeynes@386 | 724 | JMP_TARGET(nosat);
|
nkeynes@386 | 725 | ADD_r32_sh4r( R_EAX, R_MACL ); // 6
|
nkeynes@386 | 726 | ADC_r32_sh4r( R_EDX, R_MACH ); // 6
|
nkeynes@386 | 727 | JMP_TARGET(end);
|
nkeynes@386 | 728 | JMP_TARGET(end2);
|
nkeynes@386 | 729 | JMP_TARGET(end3);
|
nkeynes@386 | 730 | :}
|
nkeynes@359 | 731 | MOVT Rn {:
|
nkeynes@359 | 732 | load_spreg( R_EAX, R_T );
|
nkeynes@359 | 733 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 734 | :}
|
nkeynes@361 | 735 | MUL.L Rm, Rn {:
|
nkeynes@361 | 736 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 737 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 738 | MUL_r32( R_ECX );
|
nkeynes@361 | 739 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 740 | :}
|
nkeynes@374 | 741 | MULS.W Rm, Rn {:
|
nkeynes@374 | 742 | load_reg16s( R_EAX, Rm );
|
nkeynes@374 | 743 | load_reg16s( R_ECX, Rn );
|
nkeynes@374 | 744 | MUL_r32( R_ECX );
|
nkeynes@374 | 745 | store_spreg( R_EAX, R_MACL );
|
nkeynes@361 | 746 | :}
|
nkeynes@374 | 747 | MULU.W Rm, Rn {:
|
nkeynes@374 | 748 | load_reg16u( R_EAX, Rm );
|
nkeynes@374 | 749 | load_reg16u( R_ECX, Rn );
|
nkeynes@374 | 750 | MUL_r32( R_ECX );
|
nkeynes@374 | 751 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 752 | :}
|
nkeynes@359 | 753 | NEG Rm, Rn {:
|
nkeynes@359 | 754 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 755 | NEG_r32( R_EAX );
|
nkeynes@359 | 756 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 757 | :}
|
nkeynes@359 | 758 | NEGC Rm, Rn {:
|
nkeynes@359 | 759 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 760 | XOR_r32_r32( R_ECX, R_ECX );
|
nkeynes@359 | 761 | LDC_t();
|
nkeynes@359 | 762 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 763 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 764 | SETC_t();
|
nkeynes@359 | 765 | :}
|
nkeynes@359 | 766 | NOT Rm, Rn {:
|
nkeynes@359 | 767 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 768 | NOT_r32( R_EAX );
|
nkeynes@359 | 769 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 770 | :}
|
nkeynes@359 | 771 | OR Rm, Rn {:
|
nkeynes@359 | 772 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 773 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 774 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 775 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 776 | :}
|
nkeynes@359 | 777 | OR #imm, R0 {:
|
nkeynes@359 | 778 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 779 | OR_imm32_r32(imm, R_EAX);
|
nkeynes@359 | 780 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 781 | :}
|
nkeynes@374 | 782 | OR.B #imm, @(R0, GBR) {:
|
nkeynes@374 | 783 | load_reg( R_EAX, 0 );
|
nkeynes@374 | 784 | load_spreg( R_ECX, R_GBR );
|
nkeynes@374 | 785 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 786 | PUSH_r32(R_ECX);
|
nkeynes@386 | 787 | call_func0(sh4_read_byte);
|
nkeynes@386 | 788 | POP_r32(R_ECX);
|
nkeynes@386 | 789 | OR_imm32_r32(imm, R_EAX );
|
nkeynes@374 | 790 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@374 | 791 | :}
|
nkeynes@359 | 792 | ROTCL Rn {:
|
nkeynes@359 | 793 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 794 | LDC_t();
|
nkeynes@359 | 795 | RCL1_r32( R_EAX );
|
nkeynes@359 | 796 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 797 | SETC_t();
|
nkeynes@359 | 798 | :}
|
nkeynes@359 | 799 | ROTCR Rn {:
|
nkeynes@359 | 800 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 801 | LDC_t();
|
nkeynes@359 | 802 | RCR1_r32( R_EAX );
|
nkeynes@359 | 803 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 804 | SETC_t();
|
nkeynes@359 | 805 | :}
|
nkeynes@359 | 806 | ROTL Rn {:
|
nkeynes@359 | 807 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 808 | ROL1_r32( R_EAX );
|
nkeynes@359 | 809 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 810 | SETC_t();
|
nkeynes@359 | 811 | :}
|
nkeynes@359 | 812 | ROTR Rn {:
|
nkeynes@359 | 813 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 814 | ROR1_r32( R_EAX );
|
nkeynes@359 | 815 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 816 | SETC_t();
|
nkeynes@359 | 817 | :}
|
nkeynes@359 | 818 | SHAD Rm, Rn {:
|
nkeynes@359 | 819 | /* Annoyingly enough, not directly convertible */
|
nkeynes@361 | 820 | load_reg( R_EAX, Rn );
|
nkeynes@361 | 821 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 822 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 823 | JGE_rel8(16, doshl);
|
nkeynes@361 | 824 |
|
nkeynes@361 | 825 | NEG_r32( R_ECX ); // 2
|
nkeynes@361 | 826 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 827 | JE_rel8( 4, emptysar); // 2
|
nkeynes@361 | 828 | SAR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 829 | JMP_rel8(10, end); // 2
|
nkeynes@386 | 830 |
|
nkeynes@386 | 831 | JMP_TARGET(emptysar);
|
nkeynes@386 | 832 | SAR_imm8_r32(31, R_EAX ); // 3
|
nkeynes@386 | 833 | JMP_rel8(5, end2);
|
nkeynes@382 | 834 |
|
nkeynes@380 | 835 | JMP_TARGET(doshl);
|
nkeynes@361 | 836 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@361 | 837 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@380 | 838 | JMP_TARGET(end);
|
nkeynes@386 | 839 | JMP_TARGET(end2);
|
nkeynes@361 | 840 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 841 | :}
|
nkeynes@359 | 842 | SHLD Rm, Rn {:
|
nkeynes@368 | 843 | load_reg( R_EAX, Rn );
|
nkeynes@368 | 844 | load_reg( R_ECX, Rm );
|
nkeynes@382 | 845 | CMP_imm32_r32( 0, R_ECX );
|
nkeynes@386 | 846 | JGE_rel8(15, doshl);
|
nkeynes@368 | 847 |
|
nkeynes@382 | 848 | NEG_r32( R_ECX ); // 2
|
nkeynes@382 | 849 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@386 | 850 | JE_rel8( 4, emptyshr );
|
nkeynes@382 | 851 | SHR_r32_CL( R_EAX ); // 2
|
nkeynes@386 | 852 | JMP_rel8(9, end); // 2
|
nkeynes@386 | 853 |
|
nkeynes@386 | 854 | JMP_TARGET(emptyshr);
|
nkeynes@386 | 855 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@386 | 856 | JMP_rel8(5, end2);
|
nkeynes@382 | 857 |
|
nkeynes@382 | 858 | JMP_TARGET(doshl);
|
nkeynes@382 | 859 | AND_imm8_r8( 0x1F, R_CL ); // 3
|
nkeynes@382 | 860 | SHL_r32_CL( R_EAX ); // 2
|
nkeynes@382 | 861 | JMP_TARGET(end);
|
nkeynes@386 | 862 | JMP_TARGET(end2);
|
nkeynes@368 | 863 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 864 | :}
|
nkeynes@359 | 865 | SHAL Rn {:
|
nkeynes@359 | 866 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 867 | SHL1_r32( R_EAX );
|
nkeynes@397 | 868 | SETC_t();
|
nkeynes@359 | 869 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 870 | :}
|
nkeynes@359 | 871 | SHAR Rn {:
|
nkeynes@359 | 872 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 873 | SAR1_r32( R_EAX );
|
nkeynes@397 | 874 | SETC_t();
|
nkeynes@359 | 875 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 876 | :}
|
nkeynes@359 | 877 | SHLL Rn {:
|
nkeynes@359 | 878 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 879 | SHL1_r32( R_EAX );
|
nkeynes@397 | 880 | SETC_t();
|
nkeynes@359 | 881 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 882 | :}
|
nkeynes@359 | 883 | SHLL2 Rn {:
|
nkeynes@359 | 884 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 885 | SHL_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 886 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 887 | :}
|
nkeynes@359 | 888 | SHLL8 Rn {:
|
nkeynes@359 | 889 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 890 | SHL_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 891 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 892 | :}
|
nkeynes@359 | 893 | SHLL16 Rn {:
|
nkeynes@359 | 894 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 895 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 896 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 897 | :}
|
nkeynes@359 | 898 | SHLR Rn {:
|
nkeynes@359 | 899 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 900 | SHR1_r32( R_EAX );
|
nkeynes@397 | 901 | SETC_t();
|
nkeynes@359 | 902 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 903 | :}
|
nkeynes@359 | 904 | SHLR2 Rn {:
|
nkeynes@359 | 905 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 906 | SHR_imm8_r32( 2, R_EAX );
|
nkeynes@359 | 907 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 908 | :}
|
nkeynes@359 | 909 | SHLR8 Rn {:
|
nkeynes@359 | 910 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 911 | SHR_imm8_r32( 8, R_EAX );
|
nkeynes@359 | 912 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 913 | :}
|
nkeynes@359 | 914 | SHLR16 Rn {:
|
nkeynes@359 | 915 | load_reg( R_EAX, Rn );
|
nkeynes@359 | 916 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 917 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 918 | :}
|
nkeynes@359 | 919 | SUB Rm, Rn {:
|
nkeynes@359 | 920 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 921 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 922 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 923 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 924 | :}
|
nkeynes@359 | 925 | SUBC Rm, Rn {:
|
nkeynes@359 | 926 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 927 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 928 | LDC_t();
|
nkeynes@359 | 929 | SBB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 930 | store_reg( R_ECX, Rn );
|
nkeynes@394 | 931 | SETC_t();
|
nkeynes@359 | 932 | :}
|
nkeynes@359 | 933 | SUBV Rm, Rn {:
|
nkeynes@359 | 934 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 935 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 936 | SUB_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 937 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 938 | SETO_t();
|
nkeynes@359 | 939 | :}
|
nkeynes@359 | 940 | SWAP.B Rm, Rn {:
|
nkeynes@359 | 941 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 942 | XCHG_r8_r8( R_AL, R_AH );
|
nkeynes@359 | 943 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 944 | :}
|
nkeynes@359 | 945 | SWAP.W Rm, Rn {:
|
nkeynes@359 | 946 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 947 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 948 | SHL_imm8_r32( 16, R_ECX );
|
nkeynes@359 | 949 | SHR_imm8_r32( 16, R_EAX );
|
nkeynes@359 | 950 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 951 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 952 | :}
|
nkeynes@361 | 953 | TAS.B @Rn {:
|
nkeynes@361 | 954 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 955 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 956 | TEST_r8_r8( R_AL, R_AL );
|
nkeynes@361 | 957 | SETE_t();
|
nkeynes@361 | 958 | OR_imm8_r8( 0x80, R_AL );
|
nkeynes@386 | 959 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 960 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@361 | 961 | :}
|
nkeynes@361 | 962 | TST Rm, Rn {:
|
nkeynes@361 | 963 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 964 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 965 | TEST_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 966 | SETE_t();
|
nkeynes@361 | 967 | :}
|
nkeynes@368 | 968 | TST #imm, R0 {:
|
nkeynes@368 | 969 | load_reg( R_EAX, 0 );
|
nkeynes@368 | 970 | TEST_imm32_r32( imm, R_EAX );
|
nkeynes@368 | 971 | SETE_t();
|
nkeynes@368 | 972 | :}
|
nkeynes@368 | 973 | TST.B #imm, @(R0, GBR) {:
|
nkeynes@368 | 974 | load_reg( R_EAX, 0);
|
nkeynes@368 | 975 | load_reg( R_ECX, R_GBR);
|
nkeynes@368 | 976 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@368 | 977 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@394 | 978 | TEST_imm8_r8( imm, R_AL );
|
nkeynes@368 | 979 | SETE_t();
|
nkeynes@368 | 980 | :}
|
nkeynes@359 | 981 | XOR Rm, Rn {:
|
nkeynes@359 | 982 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 983 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 984 | XOR_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 985 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 986 | :}
|
nkeynes@359 | 987 | XOR #imm, R0 {:
|
nkeynes@359 | 988 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 989 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 990 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 991 | :}
|
nkeynes@359 | 992 | XOR.B #imm, @(R0, GBR) {:
|
nkeynes@359 | 993 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 994 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 995 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 996 | PUSH_r32(R_ECX);
|
nkeynes@386 | 997 | call_func0(sh4_read_byte);
|
nkeynes@386 | 998 | POP_r32(R_ECX);
|
nkeynes@359 | 999 | XOR_imm32_r32( imm, R_EAX );
|
nkeynes@359 | 1000 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1001 | :}
|
nkeynes@361 | 1002 | XTRCT Rm, Rn {:
|
nkeynes@361 | 1003 | load_reg( R_EAX, Rm );
|
nkeynes@394 | 1004 | load_reg( R_ECX, Rn );
|
nkeynes@394 | 1005 | SHL_imm8_r32( 16, R_EAX );
|
nkeynes@394 | 1006 | SHR_imm8_r32( 16, R_ECX );
|
nkeynes@361 | 1007 | OR_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1008 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1009 | :}
|
nkeynes@359 | 1010 |
|
nkeynes@359 | 1011 | /* Data move instructions */
|
nkeynes@359 | 1012 | MOV Rm, Rn {:
|
nkeynes@359 | 1013 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1014 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1015 | :}
|
nkeynes@359 | 1016 | MOV #imm, Rn {:
|
nkeynes@359 | 1017 | load_imm32( R_EAX, imm );
|
nkeynes@359 | 1018 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1019 | :}
|
nkeynes@359 | 1020 | MOV.B Rm, @Rn {:
|
nkeynes@359 | 1021 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1022 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1023 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1024 | :}
|
nkeynes@359 | 1025 | MOV.B Rm, @-Rn {:
|
nkeynes@359 | 1026 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1027 | load_reg( R_ECX, Rn );
|
nkeynes@382 | 1028 | ADD_imm8s_r32( -1, R_ECX );
|
nkeynes@359 | 1029 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 1030 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1031 | :}
|
nkeynes@359 | 1032 | MOV.B Rm, @(R0, Rn) {:
|
nkeynes@359 | 1033 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1034 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1035 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1036 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 1037 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1038 | :}
|
nkeynes@359 | 1039 | MOV.B R0, @(disp, GBR) {:
|
nkeynes@359 | 1040 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1041 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1042 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1043 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1044 | :}
|
nkeynes@359 | 1045 | MOV.B R0, @(disp, Rn) {:
|
nkeynes@359 | 1046 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1047 | load_reg( R_ECX, Rn );
|
nkeynes@359 | 1048 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1049 | MEM_WRITE_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1050 | :}
|
nkeynes@359 | 1051 | MOV.B @Rm, Rn {:
|
nkeynes@359 | 1052 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1053 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@386 | 1054 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1055 | :}
|
nkeynes@359 | 1056 | MOV.B @Rm+, Rn {:
|
nkeynes@359 | 1057 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1058 | MOV_r32_r32( R_ECX, R_EAX );
|
nkeynes@359 | 1059 | ADD_imm8s_r32( 1, R_EAX );
|
nkeynes@359 | 1060 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 1061 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1062 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1063 | :}
|
nkeynes@359 | 1064 | MOV.B @(R0, Rm), Rn {:
|
nkeynes@359 | 1065 | load_reg( R_EAX, 0 );
|
nkeynes@359 | 1066 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1067 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 1068 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1069 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 1070 | :}
|
nkeynes@359 | 1071 | MOV.B @(disp, GBR), R0 {:
|
nkeynes@359 | 1072 | load_spreg( R_ECX, R_GBR );
|
nkeynes@359 | 1073 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1074 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1075 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 1076 | :}
|
nkeynes@359 | 1077 | MOV.B @(disp, Rm), R0 {:
|
nkeynes@359 | 1078 | load_reg( R_ECX, Rm );
|
nkeynes@359 | 1079 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@359 | 1080 | MEM_READ_BYTE( R_ECX, R_EAX );
|
nkeynes@359 | 1081 | store_reg( R_EAX, 0 );
|
nkeynes@359 | 1082 | :}
|
nkeynes@374 | 1083 | MOV.L Rm, @Rn {:
|
nkeynes@361 | 1084 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1085 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1086 | check_walign32(R_ECX);
|
nkeynes@361 | 1087 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1088 | :}
|
nkeynes@361 | 1089 | MOV.L Rm, @-Rn {:
|
nkeynes@361 | 1090 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1091 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1092 | check_walign32( R_ECX );
|
nkeynes@361 | 1093 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@361 | 1094 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1095 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1096 | :}
|
nkeynes@361 | 1097 | MOV.L Rm, @(R0, Rn) {:
|
nkeynes@361 | 1098 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1099 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1100 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1101 | check_walign32( R_ECX );
|
nkeynes@361 | 1102 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1103 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1104 | :}
|
nkeynes@361 | 1105 | MOV.L R0, @(disp, GBR) {:
|
nkeynes@361 | 1106 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1107 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1108 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1109 | check_walign32( R_ECX );
|
nkeynes@361 | 1110 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1111 | :}
|
nkeynes@361 | 1112 | MOV.L Rm, @(disp, Rn) {:
|
nkeynes@361 | 1113 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1114 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1115 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1116 | check_walign32( R_ECX );
|
nkeynes@361 | 1117 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1118 | :}
|
nkeynes@361 | 1119 | MOV.L @Rm, Rn {:
|
nkeynes@361 | 1120 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 1121 | check_ralign32( R_ECX );
|
nkeynes@361 | 1122 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1123 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1124 | :}
|
nkeynes@361 | 1125 | MOV.L @Rm+, Rn {:
|
nkeynes@361 | 1126 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1127 | check_ralign32( R_EAX );
|
nkeynes@361 | 1128 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1129 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@361 | 1130 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1131 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1132 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1133 | :}
|
nkeynes@361 | 1134 | MOV.L @(R0, Rm), Rn {:
|
nkeynes@361 | 1135 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1136 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1137 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1138 | check_ralign32( R_ECX );
|
nkeynes@361 | 1139 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1140 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1141 | :}
|
nkeynes@361 | 1142 | MOV.L @(disp, GBR), R0 {:
|
nkeynes@361 | 1143 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1144 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1145 | check_ralign32( R_ECX );
|
nkeynes@361 | 1146 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1147 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1148 | :}
|
nkeynes@361 | 1149 | MOV.L @(disp, PC), Rn {:
|
nkeynes@374 | 1150 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1151 | SLOTILLEGAL();
|
nkeynes@374 | 1152 | } else {
|
nkeynes@388 | 1153 | uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
|
nkeynes@388 | 1154 | char *ptr = mem_get_region(target);
|
nkeynes@388 | 1155 | if( ptr != NULL ) {
|
nkeynes@388 | 1156 | MOV_moff32_EAX( (uint32_t)ptr );
|
nkeynes@388 | 1157 | } else {
|
nkeynes@388 | 1158 | load_imm32( R_ECX, target );
|
nkeynes@388 | 1159 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@388 | 1160 | }
|
nkeynes@382 | 1161 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1162 | }
|
nkeynes@361 | 1163 | :}
|
nkeynes@361 | 1164 | MOV.L @(disp, Rm), Rn {:
|
nkeynes@361 | 1165 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1166 | ADD_imm8s_r32( disp, R_ECX );
|
nkeynes@374 | 1167 | check_ralign32( R_ECX );
|
nkeynes@361 | 1168 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1169 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1170 | :}
|
nkeynes@361 | 1171 | MOV.W Rm, @Rn {:
|
nkeynes@361 | 1172 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1173 | check_walign16( R_ECX );
|
nkeynes@382 | 1174 | load_reg( R_EAX, Rm );
|
nkeynes@382 | 1175 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1176 | :}
|
nkeynes@361 | 1177 | MOV.W Rm, @-Rn {:
|
nkeynes@361 | 1178 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1179 | check_walign16( R_ECX );
|
nkeynes@361 | 1180 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1181 | ADD_imm8s_r32( -2, R_ECX );
|
nkeynes@382 | 1182 | store_reg( R_ECX, Rn );
|
nkeynes@361 | 1183 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1184 | :}
|
nkeynes@361 | 1185 | MOV.W Rm, @(R0, Rn) {:
|
nkeynes@361 | 1186 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1187 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1188 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1189 | check_walign16( R_ECX );
|
nkeynes@361 | 1190 | load_reg( R_EAX, Rm );
|
nkeynes@361 | 1191 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1192 | :}
|
nkeynes@361 | 1193 | MOV.W R0, @(disp, GBR) {:
|
nkeynes@361 | 1194 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1195 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1196 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1197 | check_walign16( R_ECX );
|
nkeynes@361 | 1198 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1199 | :}
|
nkeynes@361 | 1200 | MOV.W R0, @(disp, Rn) {:
|
nkeynes@361 | 1201 | load_reg( R_ECX, Rn );
|
nkeynes@361 | 1202 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1203 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1204 | check_walign16( R_ECX );
|
nkeynes@361 | 1205 | MEM_WRITE_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1206 | :}
|
nkeynes@361 | 1207 | MOV.W @Rm, Rn {:
|
nkeynes@361 | 1208 | load_reg( R_ECX, Rm );
|
nkeynes@374 | 1209 | check_ralign16( R_ECX );
|
nkeynes@361 | 1210 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1211 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1212 | :}
|
nkeynes@361 | 1213 | MOV.W @Rm+, Rn {:
|
nkeynes@361 | 1214 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 1215 | check_ralign16( R_EAX );
|
nkeynes@361 | 1216 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@361 | 1217 | ADD_imm8s_r32( 2, R_EAX );
|
nkeynes@361 | 1218 | store_reg( R_EAX, Rm );
|
nkeynes@361 | 1219 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1220 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1221 | :}
|
nkeynes@361 | 1222 | MOV.W @(R0, Rm), Rn {:
|
nkeynes@361 | 1223 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1224 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1225 | ADD_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 1226 | check_ralign16( R_ECX );
|
nkeynes@361 | 1227 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1228 | store_reg( R_EAX, Rn );
|
nkeynes@361 | 1229 | :}
|
nkeynes@361 | 1230 | MOV.W @(disp, GBR), R0 {:
|
nkeynes@361 | 1231 | load_spreg( R_ECX, R_GBR );
|
nkeynes@361 | 1232 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1233 | check_ralign16( R_ECX );
|
nkeynes@361 | 1234 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1235 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1236 | :}
|
nkeynes@361 | 1237 | MOV.W @(disp, PC), Rn {:
|
nkeynes@374 | 1238 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1239 | SLOTILLEGAL();
|
nkeynes@374 | 1240 | } else {
|
nkeynes@374 | 1241 | load_imm32( R_ECX, pc + disp + 4 );
|
nkeynes@374 | 1242 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@374 | 1243 | store_reg( R_EAX, Rn );
|
nkeynes@374 | 1244 | }
|
nkeynes@361 | 1245 | :}
|
nkeynes@361 | 1246 | MOV.W @(disp, Rm), R0 {:
|
nkeynes@361 | 1247 | load_reg( R_ECX, Rm );
|
nkeynes@361 | 1248 | ADD_imm32_r32( disp, R_ECX );
|
nkeynes@374 | 1249 | check_ralign16( R_ECX );
|
nkeynes@361 | 1250 | MEM_READ_WORD( R_ECX, R_EAX );
|
nkeynes@361 | 1251 | store_reg( R_EAX, 0 );
|
nkeynes@361 | 1252 | :}
|
nkeynes@361 | 1253 | MOVA @(disp, PC), R0 {:
|
nkeynes@374 | 1254 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1255 | SLOTILLEGAL();
|
nkeynes@374 | 1256 | } else {
|
nkeynes@374 | 1257 | load_imm32( R_ECX, (pc & 0xFFFFFFFC) + disp + 4 );
|
nkeynes@374 | 1258 | store_reg( R_ECX, 0 );
|
nkeynes@374 | 1259 | }
|
nkeynes@361 | 1260 | :}
|
nkeynes@361 | 1261 | MOVCA.L R0, @Rn {:
|
nkeynes@361 | 1262 | load_reg( R_EAX, 0 );
|
nkeynes@361 | 1263 | load_reg( R_ECX, Rn );
|
nkeynes@374 | 1264 | check_walign32( R_ECX );
|
nkeynes@361 | 1265 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@361 | 1266 | :}
|
nkeynes@359 | 1267 |
|
nkeynes@359 | 1268 | /* Control transfer instructions */
|
nkeynes@374 | 1269 | BF disp {:
|
nkeynes@374 | 1270 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1271 | SLOTILLEGAL();
|
nkeynes@374 | 1272 | } else {
|
nkeynes@374 | 1273 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1274 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 1275 | JNE_rel8( 5, nottaken );
|
nkeynes@374 | 1276 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 1277 | JMP_TARGET(nottaken);
|
nkeynes@374 | 1278 | INC_r32(R_ESI);
|
nkeynes@374 | 1279 | return 1;
|
nkeynes@374 | 1280 | }
|
nkeynes@374 | 1281 | :}
|
nkeynes@374 | 1282 | BF/S disp {:
|
nkeynes@374 | 1283 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1284 | SLOTILLEGAL();
|
nkeynes@374 | 1285 | } else {
|
nkeynes@386 | 1286 | load_imm32( R_EDI, pc + 4 );
|
nkeynes@374 | 1287 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 1288 | JNE_rel8( 5, nottaken );
|
nkeynes@374 | 1289 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 1290 | JMP_TARGET(nottaken);
|
nkeynes@374 | 1291 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1292 | return 0;
|
nkeynes@374 | 1293 | }
|
nkeynes@374 | 1294 | :}
|
nkeynes@374 | 1295 | BRA disp {:
|
nkeynes@374 | 1296 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1297 | SLOTILLEGAL();
|
nkeynes@374 | 1298 | } else {
|
nkeynes@374 | 1299 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1300 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1301 | return 0;
|
nkeynes@374 | 1302 | }
|
nkeynes@374 | 1303 | :}
|
nkeynes@374 | 1304 | BRAF Rn {:
|
nkeynes@374 | 1305 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1306 | SLOTILLEGAL();
|
nkeynes@374 | 1307 | } else {
|
nkeynes@374 | 1308 | load_reg( R_EDI, Rn );
|
nkeynes@382 | 1309 | ADD_imm32_r32( pc + 4, R_EDI );
|
nkeynes@374 | 1310 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1311 | return 0;
|
nkeynes@374 | 1312 | }
|
nkeynes@374 | 1313 | :}
|
nkeynes@374 | 1314 | BSR disp {:
|
nkeynes@374 | 1315 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1316 | SLOTILLEGAL();
|
nkeynes@374 | 1317 | } else {
|
nkeynes@374 | 1318 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1319 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1320 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@374 | 1321 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1322 | return 0;
|
nkeynes@374 | 1323 | }
|
nkeynes@374 | 1324 | :}
|
nkeynes@374 | 1325 | BSRF Rn {:
|
nkeynes@374 | 1326 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1327 | SLOTILLEGAL();
|
nkeynes@374 | 1328 | } else {
|
nkeynes@374 | 1329 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1330 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1331 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1332 | ADD_r32_r32( R_EAX, R_EDI );
|
nkeynes@374 | 1333 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1334 | return 0;
|
nkeynes@374 | 1335 | }
|
nkeynes@374 | 1336 | :}
|
nkeynes@374 | 1337 | BT disp {:
|
nkeynes@374 | 1338 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1339 | SLOTILLEGAL();
|
nkeynes@374 | 1340 | } else {
|
nkeynes@374 | 1341 | load_imm32( R_EDI, pc + 2 );
|
nkeynes@374 | 1342 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 1343 | JE_rel8( 5, nottaken );
|
nkeynes@374 | 1344 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 1345 | JMP_TARGET(nottaken);
|
nkeynes@374 | 1346 | INC_r32(R_ESI);
|
nkeynes@374 | 1347 | return 1;
|
nkeynes@374 | 1348 | }
|
nkeynes@374 | 1349 | :}
|
nkeynes@374 | 1350 | BT/S disp {:
|
nkeynes@374 | 1351 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1352 | SLOTILLEGAL();
|
nkeynes@374 | 1353 | } else {
|
nkeynes@386 | 1354 | load_imm32( R_EDI, pc + 4 );
|
nkeynes@374 | 1355 | CMP_imm8s_sh4r( 0, R_T );
|
nkeynes@380 | 1356 | JE_rel8( 5, nottaken );
|
nkeynes@374 | 1357 | load_imm32( R_EDI, disp + pc + 4 );
|
nkeynes@380 | 1358 | JMP_TARGET(nottaken);
|
nkeynes@374 | 1359 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1360 | return 0;
|
nkeynes@374 | 1361 | }
|
nkeynes@374 | 1362 | :}
|
nkeynes@374 | 1363 | JMP @Rn {:
|
nkeynes@374 | 1364 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1365 | SLOTILLEGAL();
|
nkeynes@374 | 1366 | } else {
|
nkeynes@374 | 1367 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1368 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1369 | return 0;
|
nkeynes@374 | 1370 | }
|
nkeynes@374 | 1371 | :}
|
nkeynes@374 | 1372 | JSR @Rn {:
|
nkeynes@374 | 1373 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1374 | SLOTILLEGAL();
|
nkeynes@374 | 1375 | } else {
|
nkeynes@374 | 1376 | load_imm32( R_EAX, pc + 4 );
|
nkeynes@374 | 1377 | store_spreg( R_EAX, R_PR );
|
nkeynes@374 | 1378 | load_reg( R_EDI, Rn );
|
nkeynes@374 | 1379 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1380 | return 0;
|
nkeynes@374 | 1381 | }
|
nkeynes@374 | 1382 | :}
|
nkeynes@374 | 1383 | RTE {:
|
nkeynes@374 | 1384 | check_priv();
|
nkeynes@374 | 1385 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1386 | SLOTILLEGAL();
|
nkeynes@374 | 1387 | } else {
|
nkeynes@386 | 1388 | load_spreg( R_EDI, R_SPC );
|
nkeynes@374 | 1389 | load_spreg( R_EAX, R_SSR );
|
nkeynes@374 | 1390 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@374 | 1391 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@377 | 1392 | sh4_x86.priv_checked = FALSE;
|
nkeynes@377 | 1393 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@374 | 1394 | return 0;
|
nkeynes@374 | 1395 | }
|
nkeynes@374 | 1396 | :}
|
nkeynes@374 | 1397 | RTS {:
|
nkeynes@374 | 1398 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1399 | SLOTILLEGAL();
|
nkeynes@374 | 1400 | } else {
|
nkeynes@374 | 1401 | load_spreg( R_EDI, R_PR );
|
nkeynes@374 | 1402 | sh4_x86.in_delay_slot = TRUE;
|
nkeynes@374 | 1403 | return 0;
|
nkeynes@374 | 1404 | }
|
nkeynes@374 | 1405 | :}
|
nkeynes@374 | 1406 | TRAPA #imm {:
|
nkeynes@374 | 1407 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@374 | 1408 | SLOTILLEGAL();
|
nkeynes@374 | 1409 | } else {
|
nkeynes@388 | 1410 | PUSH_imm32( imm );
|
nkeynes@388 | 1411 | call_func0( sh4_raise_trap );
|
nkeynes@388 | 1412 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@374 | 1413 | }
|
nkeynes@374 | 1414 | :}
|
nkeynes@374 | 1415 | UNDEF {:
|
nkeynes@374 | 1416 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@382 | 1417 | SLOTILLEGAL();
|
nkeynes@374 | 1418 | } else {
|
nkeynes@386 | 1419 | JMP_exit(EXIT_ILLEGAL);
|
nkeynes@382 | 1420 | return 1;
|
nkeynes@374 | 1421 | }
|
nkeynes@368 | 1422 | :}
|
nkeynes@374 | 1423 |
|
nkeynes@374 | 1424 | CLRMAC {:
|
nkeynes@374 | 1425 | XOR_r32_r32(R_EAX, R_EAX);
|
nkeynes@374 | 1426 | store_spreg( R_EAX, R_MACL );
|
nkeynes@374 | 1427 | store_spreg( R_EAX, R_MACH );
|
nkeynes@368 | 1428 | :}
|
nkeynes@374 | 1429 | CLRS {:
|
nkeynes@374 | 1430 | CLC();
|
nkeynes@374 | 1431 | SETC_sh4r(R_S);
|
nkeynes@368 | 1432 | :}
|
nkeynes@374 | 1433 | CLRT {:
|
nkeynes@374 | 1434 | CLC();
|
nkeynes@374 | 1435 | SETC_t();
|
nkeynes@359 | 1436 | :}
|
nkeynes@374 | 1437 | SETS {:
|
nkeynes@374 | 1438 | STC();
|
nkeynes@374 | 1439 | SETC_sh4r(R_S);
|
nkeynes@359 | 1440 | :}
|
nkeynes@374 | 1441 | SETT {:
|
nkeynes@374 | 1442 | STC();
|
nkeynes@374 | 1443 | SETC_t();
|
nkeynes@374 | 1444 | :}
|
nkeynes@359 | 1445 |
|
nkeynes@375 | 1446 | /* Floating point moves */
|
nkeynes@375 | 1447 | FMOV FRm, FRn {:
|
nkeynes@375 | 1448 | /* As horrible as this looks, it's actually covering 5 separate cases:
|
nkeynes@375 | 1449 | * 1. 32-bit fr-to-fr (PR=0)
|
nkeynes@375 | 1450 | * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
|
nkeynes@375 | 1451 | * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
|
nkeynes@375 | 1452 | * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
|
nkeynes@375 | 1453 | * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
|
nkeynes@375 | 1454 | */
|
nkeynes@377 | 1455 | check_fpuen();
|
nkeynes@375 | 1456 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1457 | load_fr_bank( R_EDX );
|
nkeynes@375 | 1458 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1459 | JNE_rel8(8, doublesize);
|
nkeynes@375 | 1460 | load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
|
nkeynes@375 | 1461 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1462 | if( FRm&1 ) {
|
nkeynes@386 | 1463 | JMP_rel8(24, end);
|
nkeynes@380 | 1464 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1465 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1466 | load_fr( R_ECX, R_EAX, FRm-1 );
|
nkeynes@375 | 1467 | if( FRn&1 ) {
|
nkeynes@375 | 1468 | load_fr( R_ECX, R_EDX, FRm );
|
nkeynes@375 | 1469 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1470 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@375 | 1471 | } else /* FRn&1 == 0 */ {
|
nkeynes@375 | 1472 | load_fr( R_ECX, R_ECX, FRm );
|
nkeynes@388 | 1473 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@388 | 1474 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@375 | 1475 | }
|
nkeynes@380 | 1476 | JMP_TARGET(end);
|
nkeynes@375 | 1477 | } else /* FRm&1 == 0 */ {
|
nkeynes@375 | 1478 | if( FRn&1 ) {
|
nkeynes@386 | 1479 | JMP_rel8(24, end);
|
nkeynes@375 | 1480 | load_xf_bank( R_ECX );
|
nkeynes@375 | 1481 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1482 | load_fr( R_EDX, R_EDX, FRm+1 );
|
nkeynes@375 | 1483 | store_fr( R_ECX, R_EAX, FRn-1 );
|
nkeynes@375 | 1484 | store_fr( R_ECX, R_EDX, FRn );
|
nkeynes@380 | 1485 | JMP_TARGET(end);
|
nkeynes@375 | 1486 | } else /* FRn&1 == 0 */ {
|
nkeynes@380 | 1487 | JMP_rel8(12, end);
|
nkeynes@375 | 1488 | load_fr( R_EDX, R_EAX, FRm );
|
nkeynes@375 | 1489 | load_fr( R_EDX, R_ECX, FRm+1 );
|
nkeynes@375 | 1490 | store_fr( R_EDX, R_EAX, FRn );
|
nkeynes@375 | 1491 | store_fr( R_EDX, R_ECX, FRn+1 );
|
nkeynes@380 | 1492 | JMP_TARGET(end);
|
nkeynes@375 | 1493 | }
|
nkeynes@375 | 1494 | }
|
nkeynes@375 | 1495 | :}
|
nkeynes@375 | 1496 | FMOV FRm, @Rn {:
|
nkeynes@377 | 1497 | check_fpuen();
|
nkeynes@375 | 1498 | load_reg( R_EDX, Rn );
|
nkeynes@375 | 1499 | check_walign32( R_EDX );
|
nkeynes@375 | 1500 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1501 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1502 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 1503 | load_fr_bank( R_ECX );
|
nkeynes@375 | 1504 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@375 | 1505 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@375 | 1506 | if( FRm&1 ) {
|
nkeynes@386 | 1507 | JMP_rel8( 48, end );
|
nkeynes@380 | 1508 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1509 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1510 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1511 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1512 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1513 | JMP_TARGET(end);
|
nkeynes@375 | 1514 | } else {
|
nkeynes@380 | 1515 | JMP_rel8( 39, end );
|
nkeynes@380 | 1516 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1517 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1518 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1519 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1520 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1521 | JMP_TARGET(end);
|
nkeynes@375 | 1522 | }
|
nkeynes@375 | 1523 | :}
|
nkeynes@375 | 1524 | FMOV @Rm, FRn {:
|
nkeynes@377 | 1525 | check_fpuen();
|
nkeynes@375 | 1526 | load_reg( R_EDX, Rm );
|
nkeynes@375 | 1527 | check_ralign32( R_EDX );
|
nkeynes@375 | 1528 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1529 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1530 | JNE_rel8(19, doublesize);
|
nkeynes@375 | 1531 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1532 | load_fr_bank( R_ECX );
|
nkeynes@375 | 1533 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@375 | 1534 | if( FRn&1 ) {
|
nkeynes@386 | 1535 | JMP_rel8(48, end);
|
nkeynes@380 | 1536 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1537 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@375 | 1538 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@375 | 1539 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1540 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1541 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1542 | JMP_TARGET(end);
|
nkeynes@375 | 1543 | } else {
|
nkeynes@380 | 1544 | JMP_rel8(36, end);
|
nkeynes@380 | 1545 | JMP_TARGET(doublesize);
|
nkeynes@375 | 1546 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1547 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1548 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1549 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1550 | JMP_TARGET(end);
|
nkeynes@375 | 1551 | }
|
nkeynes@375 | 1552 | :}
|
nkeynes@377 | 1553 | FMOV FRm, @-Rn {:
|
nkeynes@377 | 1554 | check_fpuen();
|
nkeynes@377 | 1555 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 1556 | check_walign32( R_EDX );
|
nkeynes@377 | 1557 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1558 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@382 | 1559 | JNE_rel8(26, doublesize);
|
nkeynes@377 | 1560 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1561 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1562 | ADD_imm8s_r32(-4,R_EDX);
|
nkeynes@377 | 1563 | store_reg( R_EDX, Rn );
|
nkeynes@377 | 1564 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 1565 | if( FRm&1 ) {
|
nkeynes@386 | 1566 | JMP_rel8( 54, end );
|
nkeynes@380 | 1567 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1568 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1569 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1570 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1571 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 1572 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 1573 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1574 | JMP_TARGET(end);
|
nkeynes@377 | 1575 | } else {
|
nkeynes@382 | 1576 | JMP_rel8( 45, end );
|
nkeynes@380 | 1577 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1578 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1579 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1580 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1581 | ADD_imm8s_r32(-8,R_EDX);
|
nkeynes@380 | 1582 | store_reg( R_EDX, Rn );
|
nkeynes@380 | 1583 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1584 | JMP_TARGET(end);
|
nkeynes@377 | 1585 | }
|
nkeynes@377 | 1586 | :}
|
nkeynes@377 | 1587 | FMOV @Rm+, FRn {:
|
nkeynes@377 | 1588 | check_fpuen();
|
nkeynes@377 | 1589 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 1590 | check_ralign32( R_EDX );
|
nkeynes@377 | 1591 | MOV_r32_r32( R_EDX, R_EAX );
|
nkeynes@377 | 1592 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1593 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1594 | JNE_rel8(25, doublesize);
|
nkeynes@377 | 1595 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@377 | 1596 | store_reg( R_EAX, Rm );
|
nkeynes@377 | 1597 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1598 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1599 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1600 | if( FRn&1 ) {
|
nkeynes@386 | 1601 | JMP_rel8(54, end);
|
nkeynes@380 | 1602 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1603 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 1604 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 1605 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1606 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 1607 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1608 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1609 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1610 | JMP_TARGET(end);
|
nkeynes@377 | 1611 | } else {
|
nkeynes@380 | 1612 | JMP_rel8(42, end);
|
nkeynes@377 | 1613 | ADD_imm8s_r32( 8, R_EAX );
|
nkeynes@377 | 1614 | store_reg(R_EAX, Rm);
|
nkeynes@377 | 1615 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1616 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1617 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1618 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1619 | JMP_TARGET(end);
|
nkeynes@377 | 1620 | }
|
nkeynes@377 | 1621 | :}
|
nkeynes@377 | 1622 | FMOV FRm, @(R0, Rn) {:
|
nkeynes@377 | 1623 | check_fpuen();
|
nkeynes@377 | 1624 | load_reg( R_EDX, Rn );
|
nkeynes@377 | 1625 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@377 | 1626 | check_walign32( R_EDX );
|
nkeynes@377 | 1627 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1628 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1629 | JNE_rel8(20, doublesize);
|
nkeynes@377 | 1630 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1631 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1632 | MEM_WRITE_LONG( R_EDX, R_EAX ); // 12
|
nkeynes@377 | 1633 | if( FRm&1 ) {
|
nkeynes@386 | 1634 | JMP_rel8( 48, end );
|
nkeynes@380 | 1635 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1636 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1637 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1638 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1639 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1640 | JMP_TARGET(end);
|
nkeynes@377 | 1641 | } else {
|
nkeynes@380 | 1642 | JMP_rel8( 39, end );
|
nkeynes@380 | 1643 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1644 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1645 | load_fr( R_ECX, R_EAX, FRm&0x0E );
|
nkeynes@380 | 1646 | load_fr( R_ECX, R_ECX, FRm|0x01 );
|
nkeynes@380 | 1647 | MEM_WRITE_DOUBLE( R_EDX, R_EAX, R_ECX );
|
nkeynes@380 | 1648 | JMP_TARGET(end);
|
nkeynes@377 | 1649 | }
|
nkeynes@377 | 1650 | :}
|
nkeynes@377 | 1651 | FMOV @(R0, Rm), FRn {:
|
nkeynes@377 | 1652 | check_fpuen();
|
nkeynes@377 | 1653 | load_reg( R_EDX, Rm );
|
nkeynes@377 | 1654 | ADD_sh4r_r32( REG_OFFSET(r[0]), R_EDX );
|
nkeynes@377 | 1655 | check_ralign32( R_EDX );
|
nkeynes@377 | 1656 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1657 | TEST_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@380 | 1658 | JNE_rel8(19, doublesize);
|
nkeynes@377 | 1659 | MEM_READ_LONG( R_EDX, R_EAX );
|
nkeynes@377 | 1660 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1661 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1662 | if( FRn&1 ) {
|
nkeynes@386 | 1663 | JMP_rel8(48, end);
|
nkeynes@380 | 1664 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1665 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1666 | load_spreg( R_ECX, R_FPSCR ); // assume read_long clobbered it
|
nkeynes@377 | 1667 | load_xf_bank( R_ECX );
|
nkeynes@380 | 1668 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1669 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1670 | JMP_TARGET(end);
|
nkeynes@377 | 1671 | } else {
|
nkeynes@380 | 1672 | JMP_rel8(36, end);
|
nkeynes@380 | 1673 | JMP_TARGET(doublesize);
|
nkeynes@377 | 1674 | MEM_READ_DOUBLE( R_EDX, R_EAX, R_EDX );
|
nkeynes@377 | 1675 | load_fr_bank( R_ECX );
|
nkeynes@380 | 1676 | store_fr( R_ECX, R_EAX, FRn&0x0E );
|
nkeynes@380 | 1677 | store_fr( R_ECX, R_EDX, FRn|0x01 );
|
nkeynes@380 | 1678 | JMP_TARGET(end);
|
nkeynes@377 | 1679 | }
|
nkeynes@377 | 1680 | :}
|
nkeynes@377 | 1681 | FLDI0 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 1682 | check_fpuen();
|
nkeynes@377 | 1683 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1684 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1685 | JNE_rel8(8, end);
|
nkeynes@377 | 1686 | XOR_r32_r32( R_EAX, R_EAX );
|
nkeynes@377 | 1687 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 1688 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 1689 | JMP_TARGET(end);
|
nkeynes@377 | 1690 | :}
|
nkeynes@377 | 1691 | FLDI1 FRn {: /* IFF PR=0 */
|
nkeynes@377 | 1692 | check_fpuen();
|
nkeynes@377 | 1693 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1694 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1695 | JNE_rel8(11, end);
|
nkeynes@377 | 1696 | load_imm32(R_EAX, 0x3F800000);
|
nkeynes@377 | 1697 | load_spreg( R_ECX, REG_OFFSET(fr_bank) );
|
nkeynes@377 | 1698 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@380 | 1699 | JMP_TARGET(end);
|
nkeynes@377 | 1700 | :}
|
nkeynes@377 | 1701 |
|
nkeynes@377 | 1702 | FLOAT FPUL, FRn {:
|
nkeynes@377 | 1703 | check_fpuen();
|
nkeynes@377 | 1704 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1705 | load_spreg(R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@377 | 1706 | FILD_sh4r(R_FPUL);
|
nkeynes@377 | 1707 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1708 | JNE_rel8(5, doubleprec);
|
nkeynes@377 | 1709 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 1710 | JMP_rel8(3, end);
|
nkeynes@380 | 1711 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1712 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 1713 | JMP_TARGET(end);
|
nkeynes@377 | 1714 | :}
|
nkeynes@377 | 1715 | FTRC FRm, FPUL {:
|
nkeynes@377 | 1716 | check_fpuen();
|
nkeynes@388 | 1717 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 1718 | load_fr_bank( R_EDX );
|
nkeynes@388 | 1719 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 1720 | JNE_rel8(5, doubleprec);
|
nkeynes@388 | 1721 | push_fr( R_EDX, FRm );
|
nkeynes@388 | 1722 | JMP_rel8(3, doop);
|
nkeynes@388 | 1723 | JMP_TARGET(doubleprec);
|
nkeynes@388 | 1724 | push_dr( R_EDX, FRm );
|
nkeynes@388 | 1725 | JMP_TARGET( doop );
|
nkeynes@388 | 1726 | load_imm32( R_ECX, (uint32_t)&max_int );
|
nkeynes@388 | 1727 | FILD_r32ind( R_ECX );
|
nkeynes@388 | 1728 | FCOMIP_st(1);
|
nkeynes@394 | 1729 | JNA_rel8( 32, sat );
|
nkeynes@388 | 1730 | load_imm32( R_ECX, (uint32_t)&min_int ); // 5
|
nkeynes@388 | 1731 | FILD_r32ind( R_ECX ); // 2
|
nkeynes@388 | 1732 | FCOMIP_st(1); // 2
|
nkeynes@394 | 1733 | JAE_rel8( 21, sat2 ); // 2
|
nkeynes@394 | 1734 | load_imm32( R_EAX, (uint32_t)&save_fcw );
|
nkeynes@394 | 1735 | FNSTCW_r32ind( R_EAX );
|
nkeynes@394 | 1736 | load_imm32( R_EDX, (uint32_t)&trunc_fcw );
|
nkeynes@394 | 1737 | FLDCW_r32ind( R_EDX );
|
nkeynes@388 | 1738 | FISTP_sh4r(R_FPUL); // 3
|
nkeynes@394 | 1739 | FLDCW_r32ind( R_EAX );
|
nkeynes@388 | 1740 | JMP_rel8( 9, end ); // 2
|
nkeynes@388 | 1741 |
|
nkeynes@388 | 1742 | JMP_TARGET(sat);
|
nkeynes@388 | 1743 | JMP_TARGET(sat2);
|
nkeynes@388 | 1744 | MOV_r32ind_r32( R_ECX, R_ECX ); // 2
|
nkeynes@388 | 1745 | store_spreg( R_ECX, R_FPUL );
|
nkeynes@388 | 1746 | FPOP_st();
|
nkeynes@388 | 1747 | JMP_TARGET(end);
|
nkeynes@377 | 1748 | :}
|
nkeynes@377 | 1749 | FLDS FRm, FPUL {:
|
nkeynes@377 | 1750 | check_fpuen();
|
nkeynes@377 | 1751 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1752 | load_fr( R_ECX, R_EAX, FRm );
|
nkeynes@377 | 1753 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 1754 | :}
|
nkeynes@377 | 1755 | FSTS FPUL, FRn {:
|
nkeynes@377 | 1756 | check_fpuen();
|
nkeynes@377 | 1757 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1758 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@377 | 1759 | store_fr( R_ECX, R_EAX, FRn );
|
nkeynes@377 | 1760 | :}
|
nkeynes@377 | 1761 | FCNVDS FRm, FPUL {:
|
nkeynes@377 | 1762 | check_fpuen();
|
nkeynes@377 | 1763 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1764 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1765 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 1766 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1767 | push_dr( R_ECX, FRm );
|
nkeynes@377 | 1768 | pop_fpul();
|
nkeynes@380 | 1769 | JMP_TARGET(end);
|
nkeynes@377 | 1770 | :}
|
nkeynes@377 | 1771 | FCNVSD FPUL, FRn {:
|
nkeynes@377 | 1772 | check_fpuen();
|
nkeynes@377 | 1773 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1774 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1775 | JE_rel8(9, end); // only when PR=1
|
nkeynes@377 | 1776 | load_fr_bank( R_ECX );
|
nkeynes@377 | 1777 | push_fpul();
|
nkeynes@377 | 1778 | pop_dr( R_ECX, FRn );
|
nkeynes@380 | 1779 | JMP_TARGET(end);
|
nkeynes@377 | 1780 | :}
|
nkeynes@375 | 1781 |
|
nkeynes@359 | 1782 | /* Floating point instructions */
|
nkeynes@374 | 1783 | FABS FRn {:
|
nkeynes@377 | 1784 | check_fpuen();
|
nkeynes@374 | 1785 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1786 | load_fr_bank( R_EDX );
|
nkeynes@374 | 1787 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1788 | JNE_rel8(10, doubleprec);
|
nkeynes@374 | 1789 | push_fr(R_EDX, FRn); // 3
|
nkeynes@374 | 1790 | FABS_st0(); // 2
|
nkeynes@374 | 1791 | pop_fr( R_EDX, FRn); //3
|
nkeynes@380 | 1792 | JMP_rel8(8,end); // 2
|
nkeynes@380 | 1793 | JMP_TARGET(doubleprec);
|
nkeynes@374 | 1794 | push_dr(R_EDX, FRn);
|
nkeynes@374 | 1795 | FABS_st0();
|
nkeynes@374 | 1796 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1797 | JMP_TARGET(end);
|
nkeynes@374 | 1798 | :}
|
nkeynes@377 | 1799 | FADD FRm, FRn {:
|
nkeynes@377 | 1800 | check_fpuen();
|
nkeynes@375 | 1801 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1802 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1803 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1804 | JNE_rel8(13,doubleprec);
|
nkeynes@377 | 1805 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1806 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1807 | FADDP_st(1);
|
nkeynes@377 | 1808 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1809 | JMP_rel8(11,end);
|
nkeynes@380 | 1810 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1811 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1812 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1813 | FADDP_st(1);
|
nkeynes@377 | 1814 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1815 | JMP_TARGET(end);
|
nkeynes@375 | 1816 | :}
|
nkeynes@377 | 1817 | FDIV FRm, FRn {:
|
nkeynes@377 | 1818 | check_fpuen();
|
nkeynes@375 | 1819 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1820 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1821 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1822 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1823 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1824 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1825 | FDIVP_st(1);
|
nkeynes@377 | 1826 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1827 | JMP_rel8(11, end);
|
nkeynes@380 | 1828 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1829 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1830 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1831 | FDIVP_st(1);
|
nkeynes@377 | 1832 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1833 | JMP_TARGET(end);
|
nkeynes@375 | 1834 | :}
|
nkeynes@375 | 1835 | FMAC FR0, FRm, FRn {:
|
nkeynes@377 | 1836 | check_fpuen();
|
nkeynes@375 | 1837 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@375 | 1838 | load_spreg( R_EDX, REG_OFFSET(fr_bank));
|
nkeynes@375 | 1839 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@380 | 1840 | JNE_rel8(18, doubleprec);
|
nkeynes@375 | 1841 | push_fr( R_EDX, 0 );
|
nkeynes@375 | 1842 | push_fr( R_EDX, FRm );
|
nkeynes@375 | 1843 | FMULP_st(1);
|
nkeynes@375 | 1844 | push_fr( R_EDX, FRn );
|
nkeynes@375 | 1845 | FADDP_st(1);
|
nkeynes@375 | 1846 | pop_fr( R_EDX, FRn );
|
nkeynes@380 | 1847 | JMP_rel8(16, end);
|
nkeynes@380 | 1848 | JMP_TARGET(doubleprec);
|
nkeynes@375 | 1849 | push_dr( R_EDX, 0 );
|
nkeynes@375 | 1850 | push_dr( R_EDX, FRm );
|
nkeynes@375 | 1851 | FMULP_st(1);
|
nkeynes@375 | 1852 | push_dr( R_EDX, FRn );
|
nkeynes@375 | 1853 | FADDP_st(1);
|
nkeynes@375 | 1854 | pop_dr( R_EDX, FRn );
|
nkeynes@380 | 1855 | JMP_TARGET(end);
|
nkeynes@375 | 1856 | :}
|
nkeynes@375 | 1857 |
|
nkeynes@377 | 1858 | FMUL FRm, FRn {:
|
nkeynes@377 | 1859 | check_fpuen();
|
nkeynes@377 | 1860 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1861 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1862 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1863 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1864 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1865 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1866 | FMULP_st(1);
|
nkeynes@377 | 1867 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1868 | JMP_rel8(11, end);
|
nkeynes@380 | 1869 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1870 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1871 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1872 | FMULP_st(1);
|
nkeynes@377 | 1873 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1874 | JMP_TARGET(end);
|
nkeynes@377 | 1875 | :}
|
nkeynes@377 | 1876 | FNEG FRn {:
|
nkeynes@377 | 1877 | check_fpuen();
|
nkeynes@377 | 1878 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1879 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1880 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1881 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 1882 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1883 | FCHS_st0();
|
nkeynes@377 | 1884 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1885 | JMP_rel8(8, end);
|
nkeynes@380 | 1886 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1887 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1888 | FCHS_st0();
|
nkeynes@377 | 1889 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1890 | JMP_TARGET(end);
|
nkeynes@377 | 1891 | :}
|
nkeynes@377 | 1892 | FSRRA FRn {:
|
nkeynes@377 | 1893 | check_fpuen();
|
nkeynes@377 | 1894 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1895 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1896 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1897 | JNE_rel8(12, end); // PR=0 only
|
nkeynes@377 | 1898 | FLD1_st0();
|
nkeynes@377 | 1899 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1900 | FSQRT_st0();
|
nkeynes@377 | 1901 | FDIVP_st(1);
|
nkeynes@377 | 1902 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1903 | JMP_TARGET(end);
|
nkeynes@377 | 1904 | :}
|
nkeynes@377 | 1905 | FSQRT FRn {:
|
nkeynes@377 | 1906 | check_fpuen();
|
nkeynes@377 | 1907 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1908 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1909 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1910 | JNE_rel8(10, doubleprec);
|
nkeynes@377 | 1911 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1912 | FSQRT_st0();
|
nkeynes@377 | 1913 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1914 | JMP_rel8(8, end);
|
nkeynes@380 | 1915 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1916 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1917 | FSQRT_st0();
|
nkeynes@377 | 1918 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1919 | JMP_TARGET(end);
|
nkeynes@377 | 1920 | :}
|
nkeynes@377 | 1921 | FSUB FRm, FRn {:
|
nkeynes@377 | 1922 | check_fpuen();
|
nkeynes@377 | 1923 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1924 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1925 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1926 | JNE_rel8(13, doubleprec);
|
nkeynes@377 | 1927 | push_fr(R_EDX, FRn);
|
nkeynes@377 | 1928 | push_fr(R_EDX, FRm);
|
nkeynes@388 | 1929 | FSUBP_st(1);
|
nkeynes@377 | 1930 | pop_fr(R_EDX, FRn);
|
nkeynes@380 | 1931 | JMP_rel8(11, end);
|
nkeynes@380 | 1932 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1933 | push_dr(R_EDX, FRn);
|
nkeynes@377 | 1934 | push_dr(R_EDX, FRm);
|
nkeynes@388 | 1935 | FSUBP_st(1);
|
nkeynes@377 | 1936 | pop_dr(R_EDX, FRn);
|
nkeynes@380 | 1937 | JMP_TARGET(end);
|
nkeynes@377 | 1938 | :}
|
nkeynes@377 | 1939 |
|
nkeynes@377 | 1940 | FCMP/EQ FRm, FRn {:
|
nkeynes@377 | 1941 | check_fpuen();
|
nkeynes@377 | 1942 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1943 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1944 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1945 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 1946 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1947 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 1948 | JMP_rel8(6, end);
|
nkeynes@380 | 1949 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1950 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1951 | push_dr(R_EDX, FRn);
|
nkeynes@382 | 1952 | JMP_TARGET(end);
|
nkeynes@377 | 1953 | FCOMIP_st(1);
|
nkeynes@377 | 1954 | SETE_t();
|
nkeynes@377 | 1955 | FPOP_st();
|
nkeynes@377 | 1956 | :}
|
nkeynes@377 | 1957 | FCMP/GT FRm, FRn {:
|
nkeynes@377 | 1958 | check_fpuen();
|
nkeynes@377 | 1959 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 1960 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@377 | 1961 | load_fr_bank( R_EDX );
|
nkeynes@380 | 1962 | JNE_rel8(8, doubleprec);
|
nkeynes@377 | 1963 | push_fr(R_EDX, FRm);
|
nkeynes@377 | 1964 | push_fr(R_EDX, FRn);
|
nkeynes@380 | 1965 | JMP_rel8(6, end);
|
nkeynes@380 | 1966 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1967 | push_dr(R_EDX, FRm);
|
nkeynes@377 | 1968 | push_dr(R_EDX, FRn);
|
nkeynes@380 | 1969 | JMP_TARGET(end);
|
nkeynes@377 | 1970 | FCOMIP_st(1);
|
nkeynes@377 | 1971 | SETA_t();
|
nkeynes@377 | 1972 | FPOP_st();
|
nkeynes@377 | 1973 | :}
|
nkeynes@377 | 1974 |
|
nkeynes@377 | 1975 | FSCA FPUL, FRn {:
|
nkeynes@377 | 1976 | check_fpuen();
|
nkeynes@388 | 1977 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 1978 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 1979 | JNE_rel8( 21, doubleprec );
|
nkeynes@388 | 1980 | load_fr_bank( R_ECX );
|
nkeynes@388 | 1981 | ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
|
nkeynes@388 | 1982 | load_spreg( R_EDX, R_FPUL );
|
nkeynes@388 | 1983 | call_func2( sh4_fsca, R_EDX, R_ECX );
|
nkeynes@388 | 1984 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 1985 | :}
|
nkeynes@377 | 1986 | FIPR FVm, FVn {:
|
nkeynes@377 | 1987 | check_fpuen();
|
nkeynes@388 | 1988 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 1989 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 1990 | JNE_rel8(44, doubleprec);
|
nkeynes@388 | 1991 |
|
nkeynes@388 | 1992 | load_fr_bank( R_ECX );
|
nkeynes@388 | 1993 | push_fr( R_ECX, FVm<<2 );
|
nkeynes@388 | 1994 | push_fr( R_ECX, FVn<<2 );
|
nkeynes@388 | 1995 | FMULP_st(1);
|
nkeynes@388 | 1996 | push_fr( R_ECX, (FVm<<2)+1);
|
nkeynes@388 | 1997 | push_fr( R_ECX, (FVn<<2)+1);
|
nkeynes@388 | 1998 | FMULP_st(1);
|
nkeynes@388 | 1999 | FADDP_st(1);
|
nkeynes@388 | 2000 | push_fr( R_ECX, (FVm<<2)+2);
|
nkeynes@388 | 2001 | push_fr( R_ECX, (FVn<<2)+2);
|
nkeynes@388 | 2002 | FMULP_st(1);
|
nkeynes@388 | 2003 | FADDP_st(1);
|
nkeynes@388 | 2004 | push_fr( R_ECX, (FVm<<2)+3);
|
nkeynes@388 | 2005 | push_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2006 | FMULP_st(1);
|
nkeynes@388 | 2007 | FADDP_st(1);
|
nkeynes@388 | 2008 | pop_fr( R_ECX, (FVn<<2)+3);
|
nkeynes@388 | 2009 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2010 | :}
|
nkeynes@377 | 2011 | FTRV XMTRX, FVn {:
|
nkeynes@377 | 2012 | check_fpuen();
|
nkeynes@388 | 2013 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@388 | 2014 | TEST_imm32_r32( FPSCR_PR, R_ECX );
|
nkeynes@388 | 2015 | JNE_rel8( 30, doubleprec );
|
nkeynes@388 | 2016 | load_fr_bank( R_EDX ); // 3
|
nkeynes@388 | 2017 | ADD_imm8s_r32( FVn<<4, R_EDX ); // 3
|
nkeynes@388 | 2018 | load_xf_bank( R_ECX ); // 12
|
nkeynes@388 | 2019 | call_func2( sh4_ftrv, R_EDX, R_ECX ); // 12
|
nkeynes@388 | 2020 | JMP_TARGET(doubleprec);
|
nkeynes@377 | 2021 | :}
|
nkeynes@377 | 2022 |
|
nkeynes@377 | 2023 | FRCHG {:
|
nkeynes@377 | 2024 | check_fpuen();
|
nkeynes@377 | 2025 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2026 | XOR_imm32_r32( FPSCR_FR, R_ECX );
|
nkeynes@377 | 2027 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@386 | 2028 | update_fr_bank( R_ECX );
|
nkeynes@377 | 2029 | :}
|
nkeynes@377 | 2030 | FSCHG {:
|
nkeynes@377 | 2031 | check_fpuen();
|
nkeynes@377 | 2032 | load_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2033 | XOR_imm32_r32( FPSCR_SZ, R_ECX );
|
nkeynes@377 | 2034 | store_spreg( R_ECX, R_FPSCR );
|
nkeynes@377 | 2035 | :}
|
nkeynes@359 | 2036 |
|
nkeynes@359 | 2037 | /* Processor control instructions */
|
nkeynes@368 | 2038 | LDC Rm, SR {:
|
nkeynes@386 | 2039 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2040 | SLOTILLEGAL();
|
nkeynes@386 | 2041 | } else {
|
nkeynes@386 | 2042 | check_priv();
|
nkeynes@386 | 2043 | load_reg( R_EAX, Rm );
|
nkeynes@386 | 2044 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2045 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2046 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 2047 | }
|
nkeynes@368 | 2048 | :}
|
nkeynes@359 | 2049 | LDC Rm, GBR {:
|
nkeynes@359 | 2050 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2051 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2052 | :}
|
nkeynes@359 | 2053 | LDC Rm, VBR {:
|
nkeynes@386 | 2054 | check_priv();
|
nkeynes@359 | 2055 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2056 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2057 | :}
|
nkeynes@359 | 2058 | LDC Rm, SSR {:
|
nkeynes@386 | 2059 | check_priv();
|
nkeynes@359 | 2060 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2061 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2062 | :}
|
nkeynes@359 | 2063 | LDC Rm, SGR {:
|
nkeynes@386 | 2064 | check_priv();
|
nkeynes@359 | 2065 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2066 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2067 | :}
|
nkeynes@359 | 2068 | LDC Rm, SPC {:
|
nkeynes@386 | 2069 | check_priv();
|
nkeynes@359 | 2070 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2071 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2072 | :}
|
nkeynes@359 | 2073 | LDC Rm, DBR {:
|
nkeynes@386 | 2074 | check_priv();
|
nkeynes@359 | 2075 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2076 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2077 | :}
|
nkeynes@374 | 2078 | LDC Rm, Rn_BANK {:
|
nkeynes@386 | 2079 | check_priv();
|
nkeynes@374 | 2080 | load_reg( R_EAX, Rm );
|
nkeynes@374 | 2081 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@374 | 2082 | :}
|
nkeynes@359 | 2083 | LDC.L @Rm+, GBR {:
|
nkeynes@359 | 2084 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2085 | check_ralign32( R_EAX );
|
nkeynes@359 | 2086 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2087 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2088 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2089 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2090 | store_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2091 | :}
|
nkeynes@368 | 2092 | LDC.L @Rm+, SR {:
|
nkeynes@386 | 2093 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2094 | SLOTILLEGAL();
|
nkeynes@386 | 2095 | } else {
|
nkeynes@386 | 2096 | check_priv();
|
nkeynes@386 | 2097 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2098 | check_ralign32( R_EAX );
|
nkeynes@386 | 2099 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@386 | 2100 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@386 | 2101 | store_reg( R_EAX, Rm );
|
nkeynes@386 | 2102 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@386 | 2103 | call_func1( sh4_write_sr, R_EAX );
|
nkeynes@386 | 2104 | sh4_x86.priv_checked = FALSE;
|
nkeynes@386 | 2105 | sh4_x86.fpuen_checked = FALSE;
|
nkeynes@386 | 2106 | }
|
nkeynes@359 | 2107 | :}
|
nkeynes@359 | 2108 | LDC.L @Rm+, VBR {:
|
nkeynes@386 | 2109 | check_priv();
|
nkeynes@359 | 2110 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2111 | check_ralign32( R_EAX );
|
nkeynes@359 | 2112 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2113 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2114 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2115 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2116 | store_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2117 | :}
|
nkeynes@359 | 2118 | LDC.L @Rm+, SSR {:
|
nkeynes@386 | 2119 | check_priv();
|
nkeynes@359 | 2120 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2121 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2122 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2123 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2124 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2125 | store_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2126 | :}
|
nkeynes@359 | 2127 | LDC.L @Rm+, SGR {:
|
nkeynes@386 | 2128 | check_priv();
|
nkeynes@359 | 2129 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2130 | check_ralign32( R_EAX );
|
nkeynes@359 | 2131 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2132 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2133 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2134 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2135 | store_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2136 | :}
|
nkeynes@359 | 2137 | LDC.L @Rm+, SPC {:
|
nkeynes@386 | 2138 | check_priv();
|
nkeynes@359 | 2139 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2140 | check_ralign32( R_EAX );
|
nkeynes@359 | 2141 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2142 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2143 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2144 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2145 | store_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2146 | :}
|
nkeynes@359 | 2147 | LDC.L @Rm+, DBR {:
|
nkeynes@386 | 2148 | check_priv();
|
nkeynes@359 | 2149 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2150 | check_ralign32( R_EAX );
|
nkeynes@359 | 2151 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2152 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2153 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2154 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2155 | store_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2156 | :}
|
nkeynes@359 | 2157 | LDC.L @Rm+, Rn_BANK {:
|
nkeynes@386 | 2158 | check_priv();
|
nkeynes@374 | 2159 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2160 | check_ralign32( R_EAX );
|
nkeynes@374 | 2161 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@374 | 2162 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@374 | 2163 | store_reg( R_EAX, Rm );
|
nkeynes@374 | 2164 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 2165 | store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
|
nkeynes@359 | 2166 | :}
|
nkeynes@359 | 2167 | LDS Rm, FPSCR {:
|
nkeynes@359 | 2168 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2169 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2170 | update_fr_bank( R_EAX );
|
nkeynes@359 | 2171 | :}
|
nkeynes@359 | 2172 | LDS.L @Rm+, FPSCR {:
|
nkeynes@359 | 2173 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2174 | check_ralign32( R_EAX );
|
nkeynes@359 | 2175 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2176 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2177 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2178 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2179 | store_spreg( R_EAX, R_FPSCR );
|
nkeynes@386 | 2180 | update_fr_bank( R_EAX );
|
nkeynes@359 | 2181 | :}
|
nkeynes@359 | 2182 | LDS Rm, FPUL {:
|
nkeynes@359 | 2183 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2184 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2185 | :}
|
nkeynes@359 | 2186 | LDS.L @Rm+, FPUL {:
|
nkeynes@359 | 2187 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2188 | check_ralign32( R_EAX );
|
nkeynes@359 | 2189 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2190 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2191 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2192 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2193 | store_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2194 | :}
|
nkeynes@359 | 2195 | LDS Rm, MACH {:
|
nkeynes@359 | 2196 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2197 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2198 | :}
|
nkeynes@359 | 2199 | LDS.L @Rm+, MACH {:
|
nkeynes@359 | 2200 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2201 | check_ralign32( R_EAX );
|
nkeynes@359 | 2202 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2203 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2204 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2205 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2206 | store_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2207 | :}
|
nkeynes@359 | 2208 | LDS Rm, MACL {:
|
nkeynes@359 | 2209 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2210 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2211 | :}
|
nkeynes@359 | 2212 | LDS.L @Rm+, MACL {:
|
nkeynes@359 | 2213 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2214 | check_ralign32( R_EAX );
|
nkeynes@359 | 2215 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2216 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2217 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2218 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2219 | store_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2220 | :}
|
nkeynes@359 | 2221 | LDS Rm, PR {:
|
nkeynes@359 | 2222 | load_reg( R_EAX, Rm );
|
nkeynes@359 | 2223 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2224 | :}
|
nkeynes@359 | 2225 | LDS.L @Rm+, PR {:
|
nkeynes@359 | 2226 | load_reg( R_EAX, Rm );
|
nkeynes@395 | 2227 | check_ralign32( R_EAX );
|
nkeynes@359 | 2228 | MOV_r32_r32( R_EAX, R_ECX );
|
nkeynes@359 | 2229 | ADD_imm8s_r32( 4, R_EAX );
|
nkeynes@359 | 2230 | store_reg( R_EAX, Rm );
|
nkeynes@359 | 2231 | MEM_READ_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2232 | store_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2233 | :}
|
nkeynes@359 | 2234 | LDTLB {: :}
|
nkeynes@359 | 2235 | OCBI @Rn {: :}
|
nkeynes@359 | 2236 | OCBP @Rn {: :}
|
nkeynes@359 | 2237 | OCBWB @Rn {: :}
|
nkeynes@374 | 2238 | PREF @Rn {:
|
nkeynes@374 | 2239 | load_reg( R_EAX, Rn );
|
nkeynes@374 | 2240 | PUSH_r32( R_EAX );
|
nkeynes@374 | 2241 | AND_imm32_r32( 0xFC000000, R_EAX );
|
nkeynes@374 | 2242 | CMP_imm32_r32( 0xE0000000, R_EAX );
|
nkeynes@380 | 2243 | JNE_rel8(7, end);
|
nkeynes@374 | 2244 | call_func0( sh4_flush_store_queue );
|
nkeynes@380 | 2245 | JMP_TARGET(end);
|
nkeynes@377 | 2246 | ADD_imm8s_r32( 4, R_ESP );
|
nkeynes@374 | 2247 | :}
|
nkeynes@388 | 2248 | SLEEP {:
|
nkeynes@388 | 2249 | check_priv();
|
nkeynes@388 | 2250 | call_func0( sh4_sleep );
|
nkeynes@388 | 2251 | sh4_x86.exit_code = 0;
|
nkeynes@388 | 2252 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@394 | 2253 | INC_r32(R_ESI);
|
nkeynes@388 | 2254 | return 1;
|
nkeynes@388 | 2255 | :}
|
nkeynes@386 | 2256 | STC SR, Rn {:
|
nkeynes@386 | 2257 | check_priv();
|
nkeynes@386 | 2258 | call_func0(sh4_read_sr);
|
nkeynes@386 | 2259 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2260 | :}
|
nkeynes@359 | 2261 | STC GBR, Rn {:
|
nkeynes@359 | 2262 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2263 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2264 | :}
|
nkeynes@359 | 2265 | STC VBR, Rn {:
|
nkeynes@386 | 2266 | check_priv();
|
nkeynes@359 | 2267 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2268 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2269 | :}
|
nkeynes@359 | 2270 | STC SSR, Rn {:
|
nkeynes@386 | 2271 | check_priv();
|
nkeynes@359 | 2272 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2273 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2274 | :}
|
nkeynes@359 | 2275 | STC SPC, Rn {:
|
nkeynes@386 | 2276 | check_priv();
|
nkeynes@359 | 2277 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2278 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2279 | :}
|
nkeynes@359 | 2280 | STC SGR, Rn {:
|
nkeynes@386 | 2281 | check_priv();
|
nkeynes@359 | 2282 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2283 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2284 | :}
|
nkeynes@359 | 2285 | STC DBR, Rn {:
|
nkeynes@386 | 2286 | check_priv();
|
nkeynes@359 | 2287 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2288 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2289 | :}
|
nkeynes@374 | 2290 | STC Rm_BANK, Rn {:
|
nkeynes@386 | 2291 | check_priv();
|
nkeynes@374 | 2292 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2293 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2294 | :}
|
nkeynes@374 | 2295 | STC.L SR, @-Rn {:
|
nkeynes@386 | 2296 | check_priv();
|
nkeynes@395 | 2297 | call_func0( sh4_read_sr );
|
nkeynes@368 | 2298 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2299 | check_walign32( R_ECX );
|
nkeynes@382 | 2300 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@368 | 2301 | store_reg( R_ECX, Rn );
|
nkeynes@368 | 2302 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2303 | :}
|
nkeynes@359 | 2304 | STC.L VBR, @-Rn {:
|
nkeynes@386 | 2305 | check_priv();
|
nkeynes@359 | 2306 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2307 | check_walign32( R_ECX );
|
nkeynes@382 | 2308 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2309 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2310 | load_spreg( R_EAX, R_VBR );
|
nkeynes@359 | 2311 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2312 | :}
|
nkeynes@359 | 2313 | STC.L SSR, @-Rn {:
|
nkeynes@386 | 2314 | check_priv();
|
nkeynes@359 | 2315 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2316 | check_walign32( R_ECX );
|
nkeynes@382 | 2317 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2318 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2319 | load_spreg( R_EAX, R_SSR );
|
nkeynes@359 | 2320 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2321 | :}
|
nkeynes@359 | 2322 | STC.L SPC, @-Rn {:
|
nkeynes@386 | 2323 | check_priv();
|
nkeynes@359 | 2324 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2325 | check_walign32( R_ECX );
|
nkeynes@382 | 2326 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2327 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2328 | load_spreg( R_EAX, R_SPC );
|
nkeynes@359 | 2329 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2330 | :}
|
nkeynes@359 | 2331 | STC.L SGR, @-Rn {:
|
nkeynes@386 | 2332 | check_priv();
|
nkeynes@359 | 2333 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2334 | check_walign32( R_ECX );
|
nkeynes@382 | 2335 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2336 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2337 | load_spreg( R_EAX, R_SGR );
|
nkeynes@359 | 2338 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2339 | :}
|
nkeynes@359 | 2340 | STC.L DBR, @-Rn {:
|
nkeynes@386 | 2341 | check_priv();
|
nkeynes@359 | 2342 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2343 | check_walign32( R_ECX );
|
nkeynes@382 | 2344 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2345 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2346 | load_spreg( R_EAX, R_DBR );
|
nkeynes@359 | 2347 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2348 | :}
|
nkeynes@374 | 2349 | STC.L Rm_BANK, @-Rn {:
|
nkeynes@386 | 2350 | check_priv();
|
nkeynes@374 | 2351 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2352 | check_walign32( R_ECX );
|
nkeynes@382 | 2353 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@374 | 2354 | store_reg( R_ECX, Rn );
|
nkeynes@374 | 2355 | load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
|
nkeynes@374 | 2356 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@374 | 2357 | :}
|
nkeynes@359 | 2358 | STC.L GBR, @-Rn {:
|
nkeynes@359 | 2359 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2360 | check_walign32( R_ECX );
|
nkeynes@382 | 2361 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2362 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2363 | load_spreg( R_EAX, R_GBR );
|
nkeynes@359 | 2364 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2365 | :}
|
nkeynes@359 | 2366 | STS FPSCR, Rn {:
|
nkeynes@359 | 2367 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 2368 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2369 | :}
|
nkeynes@359 | 2370 | STS.L FPSCR, @-Rn {:
|
nkeynes@359 | 2371 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2372 | check_walign32( R_ECX );
|
nkeynes@382 | 2373 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2374 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2375 | load_spreg( R_EAX, R_FPSCR );
|
nkeynes@359 | 2376 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2377 | :}
|
nkeynes@359 | 2378 | STS FPUL, Rn {:
|
nkeynes@359 | 2379 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2380 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2381 | :}
|
nkeynes@359 | 2382 | STS.L FPUL, @-Rn {:
|
nkeynes@359 | 2383 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2384 | check_walign32( R_ECX );
|
nkeynes@382 | 2385 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2386 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2387 | load_spreg( R_EAX, R_FPUL );
|
nkeynes@359 | 2388 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2389 | :}
|
nkeynes@359 | 2390 | STS MACH, Rn {:
|
nkeynes@359 | 2391 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2392 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2393 | :}
|
nkeynes@359 | 2394 | STS.L MACH, @-Rn {:
|
nkeynes@359 | 2395 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2396 | check_walign32( R_ECX );
|
nkeynes@382 | 2397 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2398 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2399 | load_spreg( R_EAX, R_MACH );
|
nkeynes@359 | 2400 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2401 | :}
|
nkeynes@359 | 2402 | STS MACL, Rn {:
|
nkeynes@359 | 2403 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2404 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2405 | :}
|
nkeynes@359 | 2406 | STS.L MACL, @-Rn {:
|
nkeynes@359 | 2407 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2408 | check_walign32( R_ECX );
|
nkeynes@382 | 2409 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2410 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2411 | load_spreg( R_EAX, R_MACL );
|
nkeynes@359 | 2412 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2413 | :}
|
nkeynes@359 | 2414 | STS PR, Rn {:
|
nkeynes@359 | 2415 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2416 | store_reg( R_EAX, Rn );
|
nkeynes@359 | 2417 | :}
|
nkeynes@359 | 2418 | STS.L PR, @-Rn {:
|
nkeynes@359 | 2419 | load_reg( R_ECX, Rn );
|
nkeynes@395 | 2420 | check_walign32( R_ECX );
|
nkeynes@382 | 2421 | ADD_imm8s_r32( -4, R_ECX );
|
nkeynes@359 | 2422 | store_reg( R_ECX, Rn );
|
nkeynes@359 | 2423 | load_spreg( R_EAX, R_PR );
|
nkeynes@359 | 2424 | MEM_WRITE_LONG( R_ECX, R_EAX );
|
nkeynes@359 | 2425 | :}
|
nkeynes@359 | 2426 |
|
nkeynes@359 | 2427 | NOP {: /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ :}
|
nkeynes@359 | 2428 | %%
|
nkeynes@374 | 2429 | if( sh4_x86.in_delay_slot ) {
|
nkeynes@386 | 2430 | ADD_imm8s_r32(2,R_ESI);
|
nkeynes@374 | 2431 | sh4_x86.in_delay_slot = FALSE;
|
nkeynes@374 | 2432 | return 1;
|
nkeynes@386 | 2433 | } else {
|
nkeynes@386 | 2434 | INC_r32(R_ESI);
|
nkeynes@374 | 2435 | }
|
nkeynes@359 | 2436 | return 0;
|
nkeynes@359 | 2437 | }
|