filename | src/asic.c |
changeset | 430:467519b050f4 |
prev | 422:61a0598e07ff |
next | 549:828d103ad115 |
author | nkeynes |
date | Wed Oct 17 11:26:45 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Split config management out to config.[ch] Manage config filename Check home dir + sysconfdir for conf file Initial work on a path settings dialog |
file | annotate | diff | log | raw |
nkeynes@31 | 1 | /** |
nkeynes@430 | 2 | * $Id: asic.c,v 1.30 2007-10-08 12:06:01 nkeynes Exp $ |
nkeynes@31 | 3 | * |
nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing, |
nkeynes@31 | 5 | * and DMA). |
nkeynes@31 | 6 | * |
nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes. |
nkeynes@31 | 8 | * |
nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify |
nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by |
nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or |
nkeynes@31 | 12 | * (at your option) any later version. |
nkeynes@31 | 13 | * |
nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful, |
nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
nkeynes@31 | 17 | * GNU General Public License for more details. |
nkeynes@31 | 18 | */ |
nkeynes@35 | 19 | |
nkeynes@35 | 20 | #define MODULE asic_module |
nkeynes@35 | 21 | |
nkeynes@1 | 22 | #include <assert.h> |
nkeynes@137 | 23 | #include <stdlib.h> |
nkeynes@1 | 24 | #include "dream.h" |
nkeynes@1 | 25 | #include "mem.h" |
nkeynes@1 | 26 | #include "sh4/intc.h" |
nkeynes@56 | 27 | #include "sh4/dmac.h" |
nkeynes@422 | 28 | #include "sh4/sh4core.h" |
nkeynes@2 | 29 | #include "dreamcast.h" |
nkeynes@25 | 30 | #include "maple/maple.h" |
nkeynes@25 | 31 | #include "gdrom/ide.h" |
nkeynes@422 | 32 | #include "pvr2/pvr2.h" |
nkeynes@15 | 33 | #include "asic.h" |
nkeynes@1 | 34 | #define MMIO_IMPL |
nkeynes@1 | 35 | #include "asic.h" |
nkeynes@1 | 36 | /* |
nkeynes@1 | 37 | * Open questions: |
nkeynes@1 | 38 | * 1) Does changing the mask after event occurance result in the |
nkeynes@1 | 39 | * interrupt being delivered immediately? |
nkeynes@1 | 40 | * TODO: Logic diagram of ASIC event/interrupt logic. |
nkeynes@1 | 41 | * |
nkeynes@1 | 42 | * ... don't even get me started on the "EXTDMA" page, about which, apparently, |
nkeynes@1 | 43 | * practically nothing is publicly known... |
nkeynes@1 | 44 | */ |
nkeynes@1 | 45 | |
nkeynes@155 | 46 | static void asic_check_cleared_events( void ); |
nkeynes@155 | 47 | static void asic_init( void ); |
nkeynes@155 | 48 | static void asic_reset( void ); |
nkeynes@302 | 49 | static uint32_t asic_run_slice( uint32_t nanosecs ); |
nkeynes@155 | 50 | static void asic_save_state( FILE *f ); |
nkeynes@155 | 51 | static int asic_load_state( FILE *f ); |
nkeynes@302 | 52 | static uint32_t g2_update_fifo_status( uint32_t slice_cycle ); |
nkeynes@155 | 53 | |
nkeynes@302 | 54 | struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice, |
nkeynes@155 | 55 | NULL, asic_save_state, asic_load_state }; |
nkeynes@15 | 56 | |
nkeynes@302 | 57 | #define G2_BIT5_TICKS 60 |
nkeynes@302 | 58 | #define G2_BIT4_TICKS 160 |
nkeynes@302 | 59 | #define G2_BIT0_ON_TICKS 120 |
nkeynes@302 | 60 | #define G2_BIT0_OFF_TICKS 420 |
nkeynes@137 | 61 | |
nkeynes@137 | 62 | struct asic_g2_state { |
nkeynes@302 | 63 | int bit5_off_timer; |
nkeynes@302 | 64 | int bit4_on_timer; |
nkeynes@302 | 65 | int bit4_off_timer; |
nkeynes@302 | 66 | int bit0_on_timer; |
nkeynes@302 | 67 | int bit0_off_timer; |
nkeynes@155 | 68 | }; |
nkeynes@155 | 69 | |
nkeynes@155 | 70 | static struct asic_g2_state g2_state; |
nkeynes@155 | 71 | |
nkeynes@302 | 72 | static uint32_t asic_run_slice( uint32_t nanosecs ) |
nkeynes@302 | 73 | { |
nkeynes@302 | 74 | g2_update_fifo_status(nanosecs); |
nkeynes@302 | 75 | if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) { |
nkeynes@302 | 76 | g2_state.bit5_off_timer = -1; |
nkeynes@302 | 77 | } else { |
nkeynes@302 | 78 | g2_state.bit5_off_timer -= nanosecs; |
nkeynes@302 | 79 | } |
nkeynes@302 | 80 | |
nkeynes@302 | 81 | if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) { |
nkeynes@302 | 82 | g2_state.bit4_off_timer = -1; |
nkeynes@302 | 83 | } else { |
nkeynes@302 | 84 | g2_state.bit4_off_timer -= nanosecs; |
nkeynes@302 | 85 | } |
nkeynes@302 | 86 | if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) { |
nkeynes@302 | 87 | g2_state.bit4_on_timer = -1; |
nkeynes@302 | 88 | } else { |
nkeynes@302 | 89 | g2_state.bit4_on_timer -= nanosecs; |
nkeynes@302 | 90 | } |
nkeynes@302 | 91 | |
nkeynes@302 | 92 | if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) { |
nkeynes@302 | 93 | g2_state.bit0_off_timer = -1; |
nkeynes@302 | 94 | } else { |
nkeynes@302 | 95 | g2_state.bit0_off_timer -= nanosecs; |
nkeynes@302 | 96 | } |
nkeynes@302 | 97 | if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) { |
nkeynes@302 | 98 | g2_state.bit0_on_timer = -1; |
nkeynes@302 | 99 | } else { |
nkeynes@302 | 100 | g2_state.bit0_on_timer -= nanosecs; |
nkeynes@302 | 101 | } |
nkeynes@302 | 102 | |
nkeynes@302 | 103 | return nanosecs; |
nkeynes@302 | 104 | } |
nkeynes@302 | 105 | |
nkeynes@155 | 106 | static void asic_init( void ) |
nkeynes@155 | 107 | { |
nkeynes@155 | 108 | register_io_region( &mmio_region_ASIC ); |
nkeynes@155 | 109 | register_io_region( &mmio_region_EXTDMA ); |
nkeynes@155 | 110 | asic_reset(); |
nkeynes@155 | 111 | } |
nkeynes@155 | 112 | |
nkeynes@155 | 113 | static void asic_reset( void ) |
nkeynes@155 | 114 | { |
nkeynes@302 | 115 | memset( &g2_state, 0xFF, sizeof(g2_state) ); |
nkeynes@155 | 116 | } |
nkeynes@155 | 117 | |
nkeynes@155 | 118 | static void asic_save_state( FILE *f ) |
nkeynes@155 | 119 | { |
nkeynes@155 | 120 | fwrite( &g2_state, sizeof(g2_state), 1, f ); |
nkeynes@155 | 121 | } |
nkeynes@155 | 122 | |
nkeynes@155 | 123 | static int asic_load_state( FILE *f ) |
nkeynes@155 | 124 | { |
nkeynes@155 | 125 | if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 ) |
nkeynes@155 | 126 | return 1; |
nkeynes@155 | 127 | else |
nkeynes@155 | 128 | return 0; |
nkeynes@155 | 129 | } |
nkeynes@155 | 130 | |
nkeynes@137 | 131 | |
nkeynes@302 | 132 | /** |
nkeynes@302 | 133 | * Setup the timers for the 3 FIFO status bits following a write through the G2 |
nkeynes@302 | 134 | * bus from the SH4 side. The timing is roughly as follows: (times are |
nkeynes@302 | 135 | * approximate based on software readings - I wouldn't take this as gospel but |
nkeynes@302 | 136 | * it seems to be enough to fool most programs). |
nkeynes@302 | 137 | * 0ns: Bit 5 (Input fifo?) goes high immediately on the write |
nkeynes@302 | 138 | * 40ns: Bit 5 goes low and bit 4 goes high |
nkeynes@302 | 139 | * 120ns: Bit 4 goes low, bit 0 goes high |
nkeynes@302 | 140 | * 240ns: Bit 0 goes low. |
nkeynes@302 | 141 | * |
nkeynes@302 | 142 | * Additional writes while the FIFO is in operation extend the time that the |
nkeynes@302 | 143 | * bits remain high as one might expect, without altering the time at which |
nkeynes@302 | 144 | * they initially go high. |
nkeynes@302 | 145 | */ |
nkeynes@137 | 146 | void asic_g2_write_word() |
nkeynes@137 | 147 | { |
nkeynes@302 | 148 | if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) { |
nkeynes@302 | 149 | g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS; |
nkeynes@302 | 150 | } else { |
nkeynes@302 | 151 | g2_state.bit5_off_timer += G2_BIT5_TICKS; |
nkeynes@302 | 152 | } |
nkeynes@302 | 153 | |
nkeynes@302 | 154 | if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) { |
nkeynes@302 | 155 | g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS; |
nkeynes@302 | 156 | } |
nkeynes@302 | 157 | |
nkeynes@302 | 158 | if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) { |
nkeynes@302 | 159 | g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS; |
nkeynes@302 | 160 | } else { |
nkeynes@302 | 161 | g2_state.bit4_off_timer += G2_BIT4_TICKS; |
nkeynes@302 | 162 | } |
nkeynes@302 | 163 | |
nkeynes@302 | 164 | if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) { |
nkeynes@302 | 165 | g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS; |
nkeynes@302 | 166 | } |
nkeynes@302 | 167 | |
nkeynes@302 | 168 | if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) { |
nkeynes@137 | 169 | g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS; |
nkeynes@137 | 170 | } else { |
nkeynes@137 | 171 | g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS; |
nkeynes@137 | 172 | } |
nkeynes@302 | 173 | |
nkeynes@137 | 174 | MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 ); |
nkeynes@137 | 175 | } |
nkeynes@137 | 176 | |
nkeynes@302 | 177 | static uint32_t g2_update_fifo_status( uint32_t nanos ) |
nkeynes@137 | 178 | { |
nkeynes@302 | 179 | uint32_t val = MMIO_READ( ASIC, G2STATUS ); |
nkeynes@302 | 180 | if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) { |
nkeynes@302 | 181 | val = val & (~0x20); |
nkeynes@302 | 182 | g2_state.bit5_off_timer = -1; |
nkeynes@163 | 183 | } |
nkeynes@302 | 184 | if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) { |
nkeynes@302 | 185 | val = val | 0x10; |
nkeynes@302 | 186 | g2_state.bit4_on_timer = -1; |
nkeynes@302 | 187 | } |
nkeynes@302 | 188 | if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) { |
nkeynes@137 | 189 | val = val & (~0x10); |
nkeynes@302 | 190 | g2_state.bit4_off_timer = -1; |
nkeynes@302 | 191 | } |
nkeynes@302 | 192 | |
nkeynes@302 | 193 | if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) { |
nkeynes@302 | 194 | val = val | 0x01; |
nkeynes@302 | 195 | g2_state.bit0_on_timer = -1; |
nkeynes@302 | 196 | } |
nkeynes@302 | 197 | if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) { |
nkeynes@137 | 198 | val = val & (~0x01); |
nkeynes@302 | 199 | g2_state.bit0_off_timer = -1; |
nkeynes@302 | 200 | } |
nkeynes@302 | 201 | |
nkeynes@302 | 202 | MMIO_WRITE( ASIC, G2STATUS, val ); |
nkeynes@302 | 203 | return val; |
nkeynes@137 | 204 | } |
nkeynes@137 | 205 | |
nkeynes@302 | 206 | static int g2_read_status() { |
nkeynes@302 | 207 | return g2_update_fifo_status( sh4r.slice_cycle ); |
nkeynes@302 | 208 | } |
nkeynes@302 | 209 | |
nkeynes@20 | 210 | |
nkeynes@155 | 211 | void asic_event( int event ) |
nkeynes@1 | 212 | { |
nkeynes@155 | 213 | int offset = ((event&0x60)>>3); |
nkeynes@155 | 214 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F)); |
nkeynes@155 | 215 | |
nkeynes@155 | 216 | if( result & MMIO_READ(ASIC, IRQA0 + offset) ) |
nkeynes@155 | 217 | intc_raise_interrupt( INT_IRQ13 ); |
nkeynes@155 | 218 | if( result & MMIO_READ(ASIC, IRQB0 + offset) ) |
nkeynes@155 | 219 | intc_raise_interrupt( INT_IRQ11 ); |
nkeynes@155 | 220 | if( result & MMIO_READ(ASIC, IRQC0 + offset) ) |
nkeynes@155 | 221 | intc_raise_interrupt( INT_IRQ9 ); |
nkeynes@305 | 222 | |
nkeynes@305 | 223 | if( event >= 64 ) { /* Third word */ |
nkeynes@305 | 224 | asic_event( EVENT_CASCADE2 ); |
nkeynes@305 | 225 | } else if( event >= 32 ) { /* Second word */ |
nkeynes@305 | 226 | asic_event( EVENT_CASCADE1 ); |
nkeynes@305 | 227 | } |
nkeynes@1 | 228 | } |
nkeynes@1 | 229 | |
nkeynes@155 | 230 | void asic_clear_event( int event ) { |
nkeynes@155 | 231 | int offset = ((event&0x60)>>3); |
nkeynes@155 | 232 | uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F))); |
nkeynes@155 | 233 | MMIO_WRITE( ASIC, PIRQ0 + offset, result ); |
nkeynes@305 | 234 | if( result == 0 ) { |
nkeynes@305 | 235 | /* clear cascades if necessary */ |
nkeynes@305 | 236 | if( event >= 64 ) { |
nkeynes@305 | 237 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF ); |
nkeynes@305 | 238 | } else if( event >= 32 ) { |
nkeynes@305 | 239 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF ); |
nkeynes@305 | 240 | } |
nkeynes@305 | 241 | } |
nkeynes@305 | 242 | |
nkeynes@155 | 243 | asic_check_cleared_events(); |
nkeynes@155 | 244 | } |
nkeynes@155 | 245 | |
nkeynes@155 | 246 | void asic_check_cleared_events( ) |
nkeynes@155 | 247 | { |
nkeynes@155 | 248 | int i, setA = 0, setB = 0, setC = 0; |
nkeynes@155 | 249 | uint32_t bits; |
nkeynes@155 | 250 | for( i=0; i<3; i++ ) { |
nkeynes@155 | 251 | bits = MMIO_READ( ASIC, PIRQ0 + i ); |
nkeynes@155 | 252 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i )); |
nkeynes@155 | 253 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i )); |
nkeynes@155 | 254 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i )); |
nkeynes@155 | 255 | } |
nkeynes@155 | 256 | if( setA == 0 ) |
nkeynes@155 | 257 | intc_clear_interrupt( INT_IRQ13 ); |
nkeynes@155 | 258 | if( setB == 0 ) |
nkeynes@155 | 259 | intc_clear_interrupt( INT_IRQ11 ); |
nkeynes@155 | 260 | if( setC == 0 ) |
nkeynes@155 | 261 | intc_clear_interrupt( INT_IRQ9 ); |
nkeynes@155 | 262 | } |
nkeynes@155 | 263 | |
nkeynes@279 | 264 | void g2_dma_transfer( int channel ) |
nkeynes@279 | 265 | { |
nkeynes@279 | 266 | uint32_t offset = channel << 5; |
nkeynes@279 | 267 | |
nkeynes@302 | 268 | if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) { |
nkeynes@302 | 269 | if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) { |
nkeynes@302 | 270 | uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset ); |
nkeynes@302 | 271 | uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset ); |
nkeynes@302 | 272 | uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF; |
nkeynes@302 | 273 | uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset ); |
nkeynes@422 | 274 | // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset ); |
nkeynes@430 | 275 | unsigned char buf[length]; |
nkeynes@279 | 276 | if( dir == 0 ) { /* SH4 to device */ |
nkeynes@279 | 277 | mem_copy_from_sh4( buf, sh4addr, length ); |
nkeynes@279 | 278 | mem_copy_to_sh4( extaddr, buf, length ); |
nkeynes@279 | 279 | } else { /* Device to SH4 */ |
nkeynes@279 | 280 | mem_copy_from_sh4( buf, extaddr, length ); |
nkeynes@279 | 281 | mem_copy_to_sh4( sh4addr, buf, length ); |
nkeynes@279 | 282 | } |
nkeynes@302 | 283 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 ); |
nkeynes@302 | 284 | asic_event( EVENT_G2_DMA0 + channel ); |
nkeynes@279 | 285 | } else { |
nkeynes@302 | 286 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 ); |
nkeynes@279 | 287 | } |
nkeynes@279 | 288 | } |
nkeynes@279 | 289 | } |
nkeynes@155 | 290 | |
nkeynes@155 | 291 | void asic_ide_dma_transfer( ) |
nkeynes@155 | 292 | { |
nkeynes@158 | 293 | if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) { |
nkeynes@158 | 294 | if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) { |
nkeynes@158 | 295 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 ); |
nkeynes@158 | 296 | |
nkeynes@158 | 297 | uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 ); |
nkeynes@158 | 298 | uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ ); |
nkeynes@422 | 299 | // int dir = MMIO_READ( EXTDMA, IDEDMADIR ); |
nkeynes@158 | 300 | |
nkeynes@158 | 301 | uint32_t xfer = ide_read_data_dma( addr, length ); |
nkeynes@158 | 302 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer ); |
nkeynes@158 | 303 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 ); |
nkeynes@158 | 304 | } else { /* 0 */ |
nkeynes@158 | 305 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 ); |
nkeynes@155 | 306 | } |
nkeynes@155 | 307 | } |
nkeynes@155 | 308 | } |
nkeynes@155 | 309 | |
nkeynes@325 | 310 | void pvr_dma_transfer( ) |
nkeynes@325 | 311 | { |
nkeynes@325 | 312 | sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0; |
nkeynes@325 | 313 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT ); |
nkeynes@430 | 314 | unsigned char *data = alloca( count ); |
nkeynes@325 | 315 | uint32_t rcount = DMAC_get_buffer( 2, data, count ); |
nkeynes@325 | 316 | if( rcount != count ) |
nkeynes@325 | 317 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count ); |
nkeynes@325 | 318 | |
nkeynes@325 | 319 | pvr2_dma_write( destaddr, data, rcount ); |
nkeynes@325 | 320 | |
nkeynes@325 | 321 | MMIO_WRITE( ASIC, PVRDMACTL, 0 ); |
nkeynes@325 | 322 | MMIO_WRITE( ASIC, PVRDMACNT, 0 ); |
nkeynes@325 | 323 | if( destaddr & 0x01000000 ) { /* Write to texture RAM */ |
nkeynes@325 | 324 | MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount ); |
nkeynes@325 | 325 | } |
nkeynes@325 | 326 | asic_event( EVENT_PVR_DMA ); |
nkeynes@325 | 327 | } |
nkeynes@155 | 328 | |
nkeynes@1 | 329 | void mmio_region_ASIC_write( uint32_t reg, uint32_t val ) |
nkeynes@1 | 330 | { |
nkeynes@1 | 331 | switch( reg ) { |
nkeynes@125 | 332 | case PIRQ1: |
nkeynes@305 | 333 | break; /* Treat this as read-only for the moment */ |
nkeynes@56 | 334 | case PIRQ0: |
nkeynes@305 | 335 | val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */ |
nkeynes@305 | 336 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val ); |
nkeynes@305 | 337 | asic_check_cleared_events(); |
nkeynes@305 | 338 | break; |
nkeynes@56 | 339 | case PIRQ2: |
nkeynes@305 | 340 | /* Clear any events */ |
nkeynes@305 | 341 | val = MMIO_READ(ASIC, reg)&(~val); |
nkeynes@305 | 342 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@305 | 343 | if( val == 0 ) { /* all clear - clear the cascade bit */ |
nkeynes@305 | 344 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF ); |
nkeynes@305 | 345 | } |
nkeynes@56 | 346 | asic_check_cleared_events(); |
nkeynes@56 | 347 | break; |
nkeynes@244 | 348 | case SYSRESET: |
nkeynes@244 | 349 | if( val == 0x7611 ) { |
nkeynes@244 | 350 | dreamcast_reset(); |
nkeynes@255 | 351 | sh4r.new_pc = sh4r.pc; |
nkeynes@244 | 352 | } else { |
nkeynes@244 | 353 | WARN( "Unknown value %08X written to SYSRESET port", val ); |
nkeynes@244 | 354 | } |
nkeynes@244 | 355 | break; |
nkeynes@56 | 356 | case MAPLE_STATE: |
nkeynes@56 | 357 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@56 | 358 | if( val & 1 ) { |
nkeynes@56 | 359 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0; |
nkeynes@56 | 360 | maple_handle_buffer( maple_addr ); |
nkeynes@56 | 361 | MMIO_WRITE( ASIC, reg, 0 ); |
nkeynes@56 | 362 | } |
nkeynes@56 | 363 | break; |
nkeynes@325 | 364 | case PVRDMADEST: |
nkeynes@325 | 365 | MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 ); |
nkeynes@325 | 366 | break; |
nkeynes@325 | 367 | case PVRDMACNT: |
nkeynes@325 | 368 | MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 ); |
nkeynes@325 | 369 | break; |
nkeynes@56 | 370 | case PVRDMACTL: /* Initiate PVR DMA transfer */ |
nkeynes@325 | 371 | val = val & 0x01; |
nkeynes@94 | 372 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@325 | 373 | if( val == 1 ) { |
nkeynes@325 | 374 | pvr_dma_transfer(); |
nkeynes@56 | 375 | } |
nkeynes@56 | 376 | break; |
nkeynes@325 | 377 | case MAPLE_DMA: |
nkeynes@158 | 378 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@158 | 379 | break; |
nkeynes@56 | 380 | default: |
nkeynes@56 | 381 | MMIO_WRITE( ASIC, reg, val ); |
nkeynes@1 | 382 | } |
nkeynes@1 | 383 | } |
nkeynes@1 | 384 | |
nkeynes@1 | 385 | int32_t mmio_region_ASIC_read( uint32_t reg ) |
nkeynes@1 | 386 | { |
nkeynes@1 | 387 | int32_t val; |
nkeynes@1 | 388 | switch( reg ) { |
nkeynes@2 | 389 | /* |
nkeynes@2 | 390 | case 0x89C: |
nkeynes@2 | 391 | sh4_stop(); |
nkeynes@2 | 392 | return 0x000000B; |
nkeynes@2 | 393 | */ |
nkeynes@94 | 394 | case PIRQ0: |
nkeynes@94 | 395 | case PIRQ1: |
nkeynes@94 | 396 | case PIRQ2: |
nkeynes@94 | 397 | case IRQA0: |
nkeynes@94 | 398 | case IRQA1: |
nkeynes@94 | 399 | case IRQA2: |
nkeynes@94 | 400 | case IRQB0: |
nkeynes@94 | 401 | case IRQB1: |
nkeynes@94 | 402 | case IRQB2: |
nkeynes@94 | 403 | case IRQC0: |
nkeynes@94 | 404 | case IRQC1: |
nkeynes@94 | 405 | case IRQC2: |
nkeynes@158 | 406 | case MAPLE_STATE: |
nkeynes@94 | 407 | val = MMIO_READ(ASIC, reg); |
nkeynes@94 | 408 | return val; |
nkeynes@94 | 409 | case G2STATUS: |
nkeynes@137 | 410 | return g2_read_status(); |
nkeynes@94 | 411 | default: |
nkeynes@94 | 412 | val = MMIO_READ(ASIC, reg); |
nkeynes@94 | 413 | return val; |
nkeynes@1 | 414 | } |
nkeynes@94 | 415 | |
nkeynes@1 | 416 | } |
nkeynes@1 | 417 | |
nkeynes@1 | 418 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val ) |
nkeynes@1 | 419 | { |
nkeynes@244 | 420 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) { |
nkeynes@244 | 421 | return; /* disabled */ |
nkeynes@244 | 422 | } |
nkeynes@244 | 423 | |
nkeynes@2 | 424 | switch( reg ) { |
nkeynes@125 | 425 | case IDEALTSTATUS: /* Device control */ |
nkeynes@125 | 426 | ide_write_control( val ); |
nkeynes@125 | 427 | break; |
nkeynes@125 | 428 | case IDEDATA: |
nkeynes@125 | 429 | ide_write_data_pio( val ); |
nkeynes@125 | 430 | break; |
nkeynes@125 | 431 | case IDEFEAT: |
nkeynes@125 | 432 | if( ide_can_write_regs() ) |
nkeynes@125 | 433 | idereg.feature = (uint8_t)val; |
nkeynes@125 | 434 | break; |
nkeynes@125 | 435 | case IDECOUNT: |
nkeynes@125 | 436 | if( ide_can_write_regs() ) |
nkeynes@125 | 437 | idereg.count = (uint8_t)val; |
nkeynes@125 | 438 | break; |
nkeynes@125 | 439 | case IDELBA0: |
nkeynes@125 | 440 | if( ide_can_write_regs() ) |
nkeynes@125 | 441 | idereg.lba0 = (uint8_t)val; |
nkeynes@125 | 442 | break; |
nkeynes@125 | 443 | case IDELBA1: |
nkeynes@125 | 444 | if( ide_can_write_regs() ) |
nkeynes@125 | 445 | idereg.lba1 = (uint8_t)val; |
nkeynes@125 | 446 | break; |
nkeynes@125 | 447 | case IDELBA2: |
nkeynes@125 | 448 | if( ide_can_write_regs() ) |
nkeynes@125 | 449 | idereg.lba2 = (uint8_t)val; |
nkeynes@125 | 450 | break; |
nkeynes@125 | 451 | case IDEDEV: |
nkeynes@125 | 452 | if( ide_can_write_regs() ) |
nkeynes@125 | 453 | idereg.device = (uint8_t)val; |
nkeynes@125 | 454 | break; |
nkeynes@125 | 455 | case IDECMD: |
nkeynes@240 | 456 | if( ide_can_write_regs() || val == IDE_CMD_NOP ) { |
nkeynes@125 | 457 | ide_write_command( (uint8_t)val ); |
nkeynes@125 | 458 | } |
nkeynes@125 | 459 | break; |
nkeynes@334 | 460 | case IDEDMASH4: |
nkeynes@334 | 461 | MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 ); |
nkeynes@334 | 462 | break; |
nkeynes@334 | 463 | case IDEDMASIZ: |
nkeynes@334 | 464 | MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE ); |
nkeynes@334 | 465 | break; |
nkeynes@125 | 466 | case IDEDMACTL1: |
nkeynes@125 | 467 | case IDEDMACTL2: |
nkeynes@334 | 468 | MMIO_WRITE( EXTDMA, reg, val & 0x01 ); |
nkeynes@155 | 469 | asic_ide_dma_transfer( ); |
nkeynes@125 | 470 | break; |
nkeynes@244 | 471 | case IDEACTIVATE: |
nkeynes@244 | 472 | if( val == 0x001FFFFF ) { |
nkeynes@244 | 473 | idereg.interface_enabled = TRUE; |
nkeynes@244 | 474 | /* Conventional wisdom says that this is necessary but not |
nkeynes@244 | 475 | * sufficient to enable the IDE interface. |
nkeynes@244 | 476 | */ |
nkeynes@244 | 477 | } else if( val == 0x000042FE ) { |
nkeynes@244 | 478 | idereg.interface_enabled = FALSE; |
nkeynes@244 | 479 | } |
nkeynes@279 | 480 | break; |
nkeynes@302 | 481 | case G2DMA0CTL1: |
nkeynes@302 | 482 | case G2DMA0CTL2: |
nkeynes@279 | 483 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@279 | 484 | g2_dma_transfer( 0 ); |
nkeynes@279 | 485 | break; |
nkeynes@302 | 486 | case G2DMA0STOP: |
nkeynes@279 | 487 | break; |
nkeynes@302 | 488 | case G2DMA1CTL1: |
nkeynes@302 | 489 | case G2DMA1CTL2: |
nkeynes@279 | 490 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@279 | 491 | g2_dma_transfer( 1 ); |
nkeynes@279 | 492 | break; |
nkeynes@279 | 493 | |
nkeynes@302 | 494 | case G2DMA1STOP: |
nkeynes@279 | 495 | break; |
nkeynes@302 | 496 | case G2DMA2CTL1: |
nkeynes@302 | 497 | case G2DMA2CTL2: |
nkeynes@279 | 498 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@279 | 499 | g2_dma_transfer( 2 ); |
nkeynes@279 | 500 | break; |
nkeynes@302 | 501 | case G2DMA2STOP: |
nkeynes@279 | 502 | break; |
nkeynes@302 | 503 | case G2DMA3CTL1: |
nkeynes@302 | 504 | case G2DMA3CTL2: |
nkeynes@279 | 505 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@279 | 506 | g2_dma_transfer( 3 ); |
nkeynes@279 | 507 | break; |
nkeynes@302 | 508 | case G2DMA3STOP: |
nkeynes@279 | 509 | break; |
nkeynes@279 | 510 | case PVRDMA2CTL1: |
nkeynes@279 | 511 | case PVRDMA2CTL2: |
nkeynes@279 | 512 | if( val != 0 ) { |
nkeynes@279 | 513 | ERROR( "Write to unimplemented DMA control register %08X", reg ); |
nkeynes@279 | 514 | //dreamcast_stop(); |
nkeynes@279 | 515 | //sh4_stop(); |
nkeynes@279 | 516 | } |
nkeynes@279 | 517 | break; |
nkeynes@125 | 518 | default: |
nkeynes@2 | 519 | MMIO_WRITE( EXTDMA, reg, val ); |
nkeynes@2 | 520 | } |
nkeynes@1 | 521 | } |
nkeynes@1 | 522 | |
nkeynes@1 | 523 | MMIO_REGION_READ_FN( EXTDMA, reg ) |
nkeynes@1 | 524 | { |
nkeynes@56 | 525 | uint32_t val; |
nkeynes@244 | 526 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) { |
nkeynes@244 | 527 | return 0xFFFFFFFF; /* disabled */ |
nkeynes@244 | 528 | } |
nkeynes@244 | 529 | |
nkeynes@1 | 530 | switch( reg ) { |
nkeynes@158 | 531 | case IDEALTSTATUS: |
nkeynes@158 | 532 | val = idereg.status; |
nkeynes@158 | 533 | return val; |
nkeynes@158 | 534 | case IDEDATA: return ide_read_data_pio( ); |
nkeynes@158 | 535 | case IDEFEAT: return idereg.error; |
nkeynes@158 | 536 | case IDECOUNT:return idereg.count; |
nkeynes@342 | 537 | case IDELBA0: return ide_get_drive_status(); |
nkeynes@158 | 538 | case IDELBA1: return idereg.lba1; |
nkeynes@158 | 539 | case IDELBA2: return idereg.lba2; |
nkeynes@158 | 540 | case IDEDEV: return idereg.device; |
nkeynes@158 | 541 | case IDECMD: |
nkeynes@158 | 542 | val = ide_read_status(); |
nkeynes@158 | 543 | return val; |
nkeynes@158 | 544 | default: |
nkeynes@158 | 545 | val = MMIO_READ( EXTDMA, reg ); |
nkeynes@158 | 546 | return val; |
nkeynes@1 | 547 | } |
nkeynes@1 | 548 | } |
nkeynes@1 | 549 |
.