nkeynes@31 | 1 | /**
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nkeynes@561 | 2 | * $Id$
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nkeynes@31 | 3 | *
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nkeynes@31 | 4 | * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
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nkeynes@31 | 5 | * and DMA).
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nkeynes@31 | 6 | *
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nkeynes@31 | 7 | * Copyright (c) 2005 Nathan Keynes.
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nkeynes@31 | 8 | *
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nkeynes@31 | 9 | * This program is free software; you can redistribute it and/or modify
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nkeynes@31 | 10 | * it under the terms of the GNU General Public License as published by
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nkeynes@31 | 11 | * the Free Software Foundation; either version 2 of the License, or
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nkeynes@31 | 12 | * (at your option) any later version.
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nkeynes@31 | 13 | *
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nkeynes@31 | 14 | * This program is distributed in the hope that it will be useful,
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nkeynes@31 | 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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nkeynes@31 | 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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nkeynes@31 | 17 | * GNU General Public License for more details.
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nkeynes@31 | 18 | */
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nkeynes@35 | 19 |
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nkeynes@35 | 20 | #define MODULE asic_module
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nkeynes@35 | 21 |
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nkeynes@1 | 22 | #include <assert.h>
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nkeynes@137 | 23 | #include <stdlib.h>
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nkeynes@1237 | 24 | #include "eventq.h"
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nkeynes@1 | 25 | #include "dream.h"
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nkeynes@1 | 26 | #include "mem.h"
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nkeynes@1 | 27 | #include "sh4/intc.h"
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nkeynes@56 | 28 | #include "sh4/dmac.h"
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nkeynes@564 | 29 | #include "sh4/sh4.h"
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nkeynes@2 | 30 | #include "dreamcast.h"
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nkeynes@25 | 31 | #include "maple/maple.h"
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nkeynes@25 | 32 | #include "gdrom/ide.h"
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nkeynes@422 | 33 | #include "pvr2/pvr2.h"
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nkeynes@15 | 34 | #include "asic.h"
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nkeynes@1 | 35 | #define MMIO_IMPL
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nkeynes@1 | 36 | #include "asic.h"
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nkeynes@1 | 37 | /*
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nkeynes@1 | 38 | * Open questions:
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nkeynes@1 | 39 | * 1) Does changing the mask after event occurance result in the
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nkeynes@1 | 40 | * interrupt being delivered immediately?
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nkeynes@1 | 41 | * TODO: Logic diagram of ASIC event/interrupt logic.
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nkeynes@1 | 42 | *
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nkeynes@1 | 43 | * ... don't even get me started on the "EXTDMA" page, about which, apparently,
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nkeynes@1 | 44 | * practically nothing is publicly known...
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nkeynes@1 | 45 | */
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nkeynes@1 | 46 |
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nkeynes@155 | 47 | static void asic_check_cleared_events( void );
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nkeynes@155 | 48 | static void asic_init( void );
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nkeynes@155 | 49 | static void asic_reset( void );
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nkeynes@302 | 50 | static uint32_t asic_run_slice( uint32_t nanosecs );
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nkeynes@155 | 51 | static void asic_save_state( FILE *f );
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nkeynes@155 | 52 | static int asic_load_state( FILE *f );
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nkeynes@302 | 53 | static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
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nkeynes@155 | 54 |
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nkeynes@302 | 55 | struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
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nkeynes@736 | 56 | NULL, asic_save_state, asic_load_state };
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nkeynes@15 | 57 |
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nkeynes@302 | 58 | #define G2_BIT5_TICKS 60
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nkeynes@302 | 59 | #define G2_BIT4_TICKS 160
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nkeynes@302 | 60 | #define G2_BIT0_ON_TICKS 120
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nkeynes@302 | 61 | #define G2_BIT0_OFF_TICKS 420
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nkeynes@137 | 62 |
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nkeynes@137 | 63 | struct asic_g2_state {
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nkeynes@302 | 64 | int bit5_off_timer;
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nkeynes@302 | 65 | int bit4_on_timer;
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nkeynes@302 | 66 | int bit4_off_timer;
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nkeynes@302 | 67 | int bit0_on_timer;
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nkeynes@302 | 68 | int bit0_off_timer;
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nkeynes@155 | 69 | };
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nkeynes@155 | 70 |
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nkeynes@155 | 71 | static struct asic_g2_state g2_state;
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nkeynes@155 | 72 |
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nkeynes@302 | 73 | static uint32_t asic_run_slice( uint32_t nanosecs )
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nkeynes@302 | 74 | {
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nkeynes@302 | 75 | g2_update_fifo_status(nanosecs);
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nkeynes@302 | 76 | if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
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nkeynes@736 | 77 | g2_state.bit5_off_timer = -1;
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nkeynes@302 | 78 | } else {
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nkeynes@736 | 79 | g2_state.bit5_off_timer -= nanosecs;
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nkeynes@302 | 80 | }
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nkeynes@302 | 81 |
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nkeynes@302 | 82 | if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
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nkeynes@736 | 83 | g2_state.bit4_off_timer = -1;
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nkeynes@302 | 84 | } else {
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nkeynes@736 | 85 | g2_state.bit4_off_timer -= nanosecs;
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nkeynes@302 | 86 | }
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nkeynes@302 | 87 | if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
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nkeynes@736 | 88 | g2_state.bit4_on_timer = -1;
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nkeynes@302 | 89 | } else {
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nkeynes@736 | 90 | g2_state.bit4_on_timer -= nanosecs;
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nkeynes@302 | 91 | }
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nkeynes@736 | 92 |
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nkeynes@302 | 93 | if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
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nkeynes@736 | 94 | g2_state.bit0_off_timer = -1;
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nkeynes@302 | 95 | } else {
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nkeynes@736 | 96 | g2_state.bit0_off_timer -= nanosecs;
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nkeynes@302 | 97 | }
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nkeynes@302 | 98 | if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
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nkeynes@736 | 99 | g2_state.bit0_on_timer = -1;
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nkeynes@302 | 100 | } else {
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nkeynes@736 | 101 | g2_state.bit0_on_timer -= nanosecs;
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nkeynes@302 | 102 | }
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nkeynes@736 | 103 |
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nkeynes@302 | 104 | return nanosecs;
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nkeynes@302 | 105 | }
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nkeynes@302 | 106 |
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nkeynes@155 | 107 | static void asic_init( void )
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nkeynes@155 | 108 | {
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nkeynes@155 | 109 | register_io_region( &mmio_region_ASIC );
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nkeynes@155 | 110 | register_io_region( &mmio_region_EXTDMA );
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nkeynes@155 | 111 | asic_reset();
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nkeynes@155 | 112 | }
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nkeynes@155 | 113 |
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nkeynes@155 | 114 | static void asic_reset( void )
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nkeynes@155 | 115 | {
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nkeynes@302 | 116 | memset( &g2_state, 0xFF, sizeof(g2_state) );
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nkeynes@155 | 117 | }
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nkeynes@155 | 118 |
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nkeynes@155 | 119 | static void asic_save_state( FILE *f )
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nkeynes@155 | 120 | {
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nkeynes@155 | 121 | fwrite( &g2_state, sizeof(g2_state), 1, f );
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nkeynes@155 | 122 | }
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nkeynes@155 | 123 |
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nkeynes@155 | 124 | static int asic_load_state( FILE *f )
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nkeynes@155 | 125 | {
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nkeynes@155 | 126 | if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
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nkeynes@736 | 127 | return 1;
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nkeynes@155 | 128 | else
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nkeynes@736 | 129 | return 0;
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nkeynes@155 | 130 | }
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nkeynes@155 | 131 |
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nkeynes@137 | 132 |
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nkeynes@302 | 133 | /**
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nkeynes@302 | 134 | * Setup the timers for the 3 FIFO status bits following a write through the G2
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nkeynes@302 | 135 | * bus from the SH4 side. The timing is roughly as follows: (times are
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nkeynes@302 | 136 | * approximate based on software readings - I wouldn't take this as gospel but
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nkeynes@302 | 137 | * it seems to be enough to fool most programs).
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nkeynes@302 | 138 | * 0ns: Bit 5 (Input fifo?) goes high immediately on the write
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nkeynes@302 | 139 | * 40ns: Bit 5 goes low and bit 4 goes high
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nkeynes@302 | 140 | * 120ns: Bit 4 goes low, bit 0 goes high
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nkeynes@302 | 141 | * 240ns: Bit 0 goes low.
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nkeynes@302 | 142 | *
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nkeynes@302 | 143 | * Additional writes while the FIFO is in operation extend the time that the
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nkeynes@302 | 144 | * bits remain high as one might expect, without altering the time at which
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nkeynes@302 | 145 | * they initially go high.
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nkeynes@302 | 146 | */
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nkeynes@137 | 147 | void asic_g2_write_word()
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nkeynes@137 | 148 | {
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nkeynes@302 | 149 | if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@736 | 150 | g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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nkeynes@302 | 151 | } else {
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nkeynes@736 | 152 | g2_state.bit5_off_timer += G2_BIT5_TICKS;
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nkeynes@302 | 153 | }
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nkeynes@302 | 154 |
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nkeynes@302 | 155 | if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@736 | 156 | g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
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nkeynes@302 | 157 | }
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nkeynes@302 | 158 |
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nkeynes@302 | 159 | if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@736 | 160 | g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
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nkeynes@302 | 161 | } else {
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nkeynes@736 | 162 | g2_state.bit4_off_timer += G2_BIT4_TICKS;
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nkeynes@302 | 163 | }
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nkeynes@302 | 164 |
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nkeynes@302 | 165 | if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@736 | 166 | g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
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nkeynes@302 | 167 | }
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nkeynes@302 | 168 |
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nkeynes@302 | 169 | if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
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nkeynes@736 | 170 | g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
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nkeynes@137 | 171 | } else {
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nkeynes@736 | 172 | g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
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nkeynes@137 | 173 | }
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nkeynes@302 | 174 |
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nkeynes@137 | 175 | MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
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nkeynes@137 | 176 | }
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nkeynes@137 | 177 |
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nkeynes@302 | 178 | static uint32_t g2_update_fifo_status( uint32_t nanos )
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nkeynes@137 | 179 | {
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nkeynes@302 | 180 | uint32_t val = MMIO_READ( ASIC, G2STATUS );
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nkeynes@302 | 181 | if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
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nkeynes@736 | 182 | val = val & (~0x20);
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nkeynes@736 | 183 | g2_state.bit5_off_timer = -1;
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nkeynes@163 | 184 | }
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nkeynes@302 | 185 | if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
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nkeynes@736 | 186 | val = val | 0x10;
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nkeynes@736 | 187 | g2_state.bit4_on_timer = -1;
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nkeynes@302 | 188 | }
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nkeynes@302 | 189 | if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
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nkeynes@736 | 190 | val = val & (~0x10);
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nkeynes@736 | 191 | g2_state.bit4_off_timer = -1;
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nkeynes@302 | 192 | }
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nkeynes@302 | 193 |
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nkeynes@302 | 194 | if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
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nkeynes@736 | 195 | val = val | 0x01;
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nkeynes@736 | 196 | g2_state.bit0_on_timer = -1;
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nkeynes@302 | 197 | }
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nkeynes@302 | 198 | if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
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nkeynes@736 | 199 | val = val & (~0x01);
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nkeynes@736 | 200 | g2_state.bit0_off_timer = -1;
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nkeynes@302 | 201 | }
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nkeynes@302 | 202 |
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nkeynes@302 | 203 | MMIO_WRITE( ASIC, G2STATUS, val );
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nkeynes@302 | 204 | return val;
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nkeynes@137 | 205 | }
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nkeynes@137 | 206 |
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nkeynes@302 | 207 | static int g2_read_status() {
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nkeynes@302 | 208 | return g2_update_fifo_status( sh4r.slice_cycle );
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nkeynes@302 | 209 | }
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nkeynes@302 | 210 |
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nkeynes@20 | 211 |
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nkeynes@155 | 212 | void asic_event( int event )
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nkeynes@1 | 213 | {
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nkeynes@155 | 214 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 215 | int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
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nkeynes@155 | 216 |
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nkeynes@155 | 217 | if( result & MMIO_READ(ASIC, IRQA0 + offset) )
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nkeynes@155 | 218 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@155 | 219 | if( result & MMIO_READ(ASIC, IRQB0 + offset) )
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nkeynes@155 | 220 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@155 | 221 | if( result & MMIO_READ(ASIC, IRQC0 + offset) )
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nkeynes@155 | 222 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@305 | 223 |
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nkeynes@305 | 224 | if( event >= 64 ) { /* Third word */
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nkeynes@736 | 225 | asic_event( EVENT_CASCADE2 );
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nkeynes@305 | 226 | } else if( event >= 32 ) { /* Second word */
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nkeynes@736 | 227 | asic_event( EVENT_CASCADE1 );
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nkeynes@305 | 228 | }
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nkeynes@1 | 229 | }
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nkeynes@1 | 230 |
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nkeynes@155 | 231 | void asic_clear_event( int event ) {
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nkeynes@155 | 232 | int offset = ((event&0x60)>>3);
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nkeynes@155 | 233 | uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
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nkeynes@155 | 234 | MMIO_WRITE( ASIC, PIRQ0 + offset, result );
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nkeynes@305 | 235 | if( result == 0 ) {
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nkeynes@736 | 236 | /* clear cascades if necessary */
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nkeynes@736 | 237 | if( event >= 64 ) {
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nkeynes@736 | 238 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
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nkeynes@736 | 239 | } else if( event >= 32 ) {
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nkeynes@736 | 240 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
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nkeynes@736 | 241 | }
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nkeynes@305 | 242 | }
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nkeynes@736 | 243 |
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nkeynes@155 | 244 | asic_check_cleared_events();
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nkeynes@155 | 245 | }
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nkeynes@155 | 246 |
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nkeynes@155 | 247 | void asic_check_cleared_events( )
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nkeynes@155 | 248 | {
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nkeynes@155 | 249 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@155 | 250 | uint32_t bits;
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nkeynes@594 | 251 | for( i=0; i<12; i+=4 ) {
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nkeynes@736 | 252 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@736 | 253 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@736 | 254 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@736 | 255 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@155 | 256 | }
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nkeynes@155 | 257 | if( setA == 0 )
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nkeynes@736 | 258 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@155 | 259 | if( setB == 0 )
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nkeynes@736 | 260 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@155 | 261 | if( setC == 0 )
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nkeynes@736 | 262 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@155 | 263 | }
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nkeynes@155 | 264 |
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nkeynes@594 | 265 | void asic_event_mask_changed( )
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nkeynes@594 | 266 | {
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nkeynes@594 | 267 | int i, setA = 0, setB = 0, setC = 0;
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nkeynes@594 | 268 | uint32_t bits;
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nkeynes@594 | 269 | for( i=0; i<12; i+=4 ) {
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nkeynes@736 | 270 | bits = MMIO_READ( ASIC, PIRQ0 + i );
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nkeynes@736 | 271 | setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
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nkeynes@736 | 272 | setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
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nkeynes@736 | 273 | setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
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nkeynes@594 | 274 | }
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nkeynes@594 | 275 | if( setA == 0 )
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nkeynes@736 | 276 | intc_clear_interrupt( INT_IRQ13 );
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nkeynes@594 | 277 | else
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nkeynes@736 | 278 | intc_raise_interrupt( INT_IRQ13 );
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nkeynes@594 | 279 | if( setB == 0 )
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nkeynes@736 | 280 | intc_clear_interrupt( INT_IRQ11 );
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nkeynes@594 | 281 | else
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nkeynes@736 | 282 | intc_raise_interrupt( INT_IRQ11 );
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nkeynes@594 | 283 | if( setC == 0 )
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nkeynes@736 | 284 | intc_clear_interrupt( INT_IRQ9 );
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nkeynes@594 | 285 | else
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nkeynes@736 | 286 | intc_raise_interrupt( INT_IRQ9 );
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nkeynes@155 | 287 | }
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nkeynes@155 | 288 |
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nkeynes@279 | 289 | void g2_dma_transfer( int channel )
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nkeynes@279 | 290 | {
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nkeynes@279 | 291 | uint32_t offset = channel << 5;
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nkeynes@279 | 292 |
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nkeynes@302 | 293 | if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
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nkeynes@736 | 294 | if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
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nkeynes@736 | 295 | uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
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nkeynes@736 | 296 | uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
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nkeynes@736 | 297 | uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
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nkeynes@736 | 298 | uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
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nkeynes@736 | 299 | // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
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nkeynes@736 | 300 | unsigned char buf[length];
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nkeynes@736 | 301 | if( dir == 0 ) { /* SH4 to device */
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nkeynes@736 | 302 | mem_copy_from_sh4( buf, sh4addr, length );
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nkeynes@736 | 303 | mem_copy_to_sh4( extaddr, buf, length );
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nkeynes@736 | 304 | } else { /* Device to SH4 */
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nkeynes@736 | 305 | mem_copy_from_sh4( buf, extaddr, length );
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nkeynes@736 | 306 | mem_copy_to_sh4( sh4addr, buf, length );
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nkeynes@736 | 307 | }
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nkeynes@736 | 308 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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nkeynes@736 | 309 | asic_event( EVENT_G2_DMA0 + channel );
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nkeynes@736 | 310 | } else {
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nkeynes@736 | 311 | MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
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nkeynes@736 | 312 | }
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nkeynes@279 | 313 | }
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nkeynes@279 | 314 | }
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nkeynes@155 | 315 |
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nkeynes@155 | 316 | void asic_ide_dma_transfer( )
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nkeynes@155 | 317 | {
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nkeynes@158 | 318 | if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
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nkeynes@736 | 319 | if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
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nkeynes@736 | 320 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
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nkeynes@736 | 321 |
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nkeynes@736 | 322 | uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
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nkeynes@736 | 323 | uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
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nkeynes@736 | 324 | // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
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nkeynes@736 | 325 |
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nkeynes@736 | 326 | uint32_t xfer = ide_read_data_dma( addr, length );
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nkeynes@736 | 327 | MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
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nkeynes@736 | 328 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@833 | 329 | asic_event( EVENT_IDE_DMA );
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nkeynes@736 | 330 | } else { /* 0 */
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nkeynes@736 | 331 | MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
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nkeynes@736 | 332 | }
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nkeynes@155 | 333 | }
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nkeynes@155 | 334 | }
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nkeynes@155 | 335 |
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nkeynes@325 | 336 | void pvr_dma_transfer( )
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nkeynes@325 | 337 | {
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nkeynes@325 | 338 | sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
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nkeynes@325 | 339 | uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
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nkeynes@1269 | 340 | unsigned char data[8192];
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nkeynes@1269 | 341 | uint32_t rcount;
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nkeynes@736 | 342 |
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nkeynes@1269 | 343 | while( count ) {
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nkeynes@1269 | 344 | uint32_t chunksize = (count < 8192) ? count : 8192;
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nkeynes@1269 | 345 | rcount = DMAC_get_buffer( 2, data, chunksize );
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nkeynes@1269 | 346 | pvr2_dma_write( destaddr, data, rcount );
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nkeynes@1269 | 347 | destaddr += rcount;
|
nkeynes@1269 | 348 | count -= rcount;
|
nkeynes@1269 | 349 | if( rcount != chunksize ) {
|
nkeynes@1269 | 350 | WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, chunksize );
|
nkeynes@1269 | 351 | break;
|
nkeynes@1269 | 352 | }
|
nkeynes@1269 | 353 | }
|
nkeynes@736 | 354 |
|
nkeynes@325 | 355 | MMIO_WRITE( ASIC, PVRDMACTL, 0 );
|
nkeynes@325 | 356 | MMIO_WRITE( ASIC, PVRDMACNT, 0 );
|
nkeynes@325 | 357 | if( destaddr & 0x01000000 ) { /* Write to texture RAM */
|
nkeynes@1269 | 358 | MMIO_WRITE( ASIC, PVRDMADEST, destaddr );
|
nkeynes@325 | 359 | }
|
nkeynes@325 | 360 | asic_event( EVENT_PVR_DMA );
|
nkeynes@325 | 361 | }
|
nkeynes@155 | 362 |
|
nkeynes@855 | 363 | void pvr_dma2_transfer()
|
nkeynes@1 | 364 | {
|
nkeynes@855 | 365 | if( MMIO_READ( EXTDMA, PVRDMA2CTL2 ) == 1 ) {
|
nkeynes@855 | 366 | if( MMIO_READ( EXTDMA, PVRDMA2CTL1 ) == 1 ) {
|
nkeynes@855 | 367 | sh4addr_t extaddr = MMIO_READ( EXTDMA, PVRDMA2EXT );
|
nkeynes@855 | 368 | sh4addr_t sh4addr = MMIO_READ( EXTDMA, PVRDMA2SH4 );
|
nkeynes@855 | 369 | int dir = MMIO_READ( EXTDMA, PVRDMA2DIR );
|
nkeynes@855 | 370 | uint32_t length = MMIO_READ( EXTDMA, PVRDMA2SIZ );
|
nkeynes@855 | 371 | unsigned char buf[length];
|
nkeynes@855 | 372 | if( dir == 0 ) { /* SH4 to PVR */
|
nkeynes@855 | 373 | mem_copy_from_sh4( buf, sh4addr, length );
|
nkeynes@855 | 374 | mem_copy_to_sh4( extaddr, buf, length );
|
nkeynes@855 | 375 | } else { /* PVR to SH4 */
|
nkeynes@855 | 376 | mem_copy_from_sh4( buf, extaddr, length );
|
nkeynes@855 | 377 | mem_copy_to_sh4( sh4addr, buf, length );
|
nkeynes@855 | 378 | }
|
nkeynes@855 | 379 | MMIO_WRITE( EXTDMA, PVRDMA2CTL2, 0 );
|
nkeynes@855 | 380 | asic_event( EVENT_PVR_DMA2 );
|
nkeynes@855 | 381 | }
|
nkeynes@1 | 382 | }
|
nkeynes@1 | 383 | }
|
nkeynes@1 | 384 |
|
nkeynes@728 | 385 | void sort_dma_transfer( )
|
nkeynes@728 | 386 | {
|
nkeynes@728 | 387 | sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
|
nkeynes@728 | 388 | sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
|
nkeynes@728 | 389 | int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
|
nkeynes@753 | 390 | int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
|
nkeynes@753 | 391 | int count = 1;
|
nkeynes@736 | 392 |
|
nkeynes@753 | 393 | uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
|
nkeynes@753 | 394 | uint16_t *table16 = (uint16_t *)table32;
|
nkeynes@753 | 395 | uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
|
nkeynes@753 | 396 | while(1) {
|
nkeynes@753 | 397 | next &= 0x07FFFFFF;
|
nkeynes@753 | 398 | if( next == 1 ) {
|
nkeynes@753 | 399 | next = table_size ? (*table32++) : (uint32_t)(*table16++);
|
nkeynes@753 | 400 | count++;
|
nkeynes@753 | 401 | continue;
|
nkeynes@753 | 402 | } else if( next == 2 ) {
|
nkeynes@753 | 403 | asic_event( EVENT_SORT_DMA );
|
nkeynes@753 | 404 | break;
|
nkeynes@753 | 405 | }
|
nkeynes@753 | 406 | uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
|
nkeynes@753 | 407 | if( data == NULL ) {
|
nkeynes@753 | 408 | break;
|
nkeynes@753 | 409 | }
|
nkeynes@753 | 410 |
|
nkeynes@753 | 411 | uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
|
nkeynes@753 | 412 | if( poly == NULL ) {
|
nkeynes@753 | 413 | asic_event( EVENT_SORT_DMA_ERR );
|
nkeynes@753 | 414 | break;
|
nkeynes@753 | 415 | }
|
nkeynes@753 | 416 | uint32_t size = poly[6] & 0xFF;
|
nkeynes@753 | 417 | if( size == 0 ) {
|
nkeynes@753 | 418 | size = 0x100;
|
nkeynes@753 | 419 | }
|
nkeynes@753 | 420 | next = poly[7];
|
nkeynes@753 | 421 | pvr2_ta_write( (unsigned char *)data, size<<5 );
|
nkeynes@753 | 422 | }
|
nkeynes@753 | 423 |
|
nkeynes@753 | 424 | MMIO_WRITE( ASIC, SORTDMACNT, count );
|
nkeynes@753 | 425 | MMIO_WRITE( ASIC, SORTDMACTL, 0 );
|
nkeynes@728 | 426 | }
|
nkeynes@728 | 427 |
|
nkeynes@1237 | 428 | void maple_set_dma_state( uint32_t val )
|
nkeynes@1237 | 429 | {
|
nkeynes@1237 | 430 | gboolean in_transfer = MMIO_READ( ASIC, MAPLE_STATE ) & 1;
|
nkeynes@1237 | 431 | gboolean transfer_requested = val & 1;
|
nkeynes@1237 | 432 | if( !in_transfer && transfer_requested ) {
|
nkeynes@1237 | 433 | /* Initiate new DMA transfer */
|
nkeynes@1237 | 434 | uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
|
nkeynes@1237 | 435 | maple_handle_buffer( maple_addr );
|
nkeynes@1237 | 436 | }
|
nkeynes@1237 | 437 | else if ( in_transfer && !transfer_requested ) {
|
nkeynes@1237 | 438 | /* Cancel current DMA transfer */
|
nkeynes@1237 | 439 | event_cancel( EVENT_MAPLE_DMA );
|
nkeynes@1237 | 440 | }
|
nkeynes@1237 | 441 | MMIO_WRITE( ASIC, MAPLE_STATE, val );
|
nkeynes@1237 | 442 | }
|
nkeynes@1237 | 443 |
|
nkeynes@1100 | 444 | gboolean asic_enable_ide_interface( gboolean enable )
|
nkeynes@1100 | 445 | {
|
nkeynes@1100 | 446 | gboolean oldval = idereg.interface_enabled;
|
nkeynes@1100 | 447 | idereg.interface_enabled = enable;
|
nkeynes@1100 | 448 | return oldval;
|
nkeynes@1100 | 449 | }
|
nkeynes@1100 | 450 |
|
nkeynes@929 | 451 | MMIO_REGION_READ_FN( ASIC, reg )
|
nkeynes@1 | 452 | {
|
nkeynes@1 | 453 | int32_t val;
|
nkeynes@929 | 454 | reg &= 0xFFF;
|
nkeynes@1 | 455 | switch( reg ) {
|
nkeynes@94 | 456 | case PIRQ0:
|
nkeynes@94 | 457 | case PIRQ1:
|
nkeynes@94 | 458 | case PIRQ2:
|
nkeynes@94 | 459 | case IRQA0:
|
nkeynes@94 | 460 | case IRQA1:
|
nkeynes@94 | 461 | case IRQA2:
|
nkeynes@94 | 462 | case IRQB0:
|
nkeynes@94 | 463 | case IRQB1:
|
nkeynes@94 | 464 | case IRQB2:
|
nkeynes@94 | 465 | case IRQC0:
|
nkeynes@94 | 466 | case IRQC1:
|
nkeynes@94 | 467 | case IRQC2:
|
nkeynes@158 | 468 | case MAPLE_STATE:
|
nkeynes@929 | 469 | val = MMIO_READ(ASIC, reg);
|
nkeynes@929 | 470 | return val;
|
nkeynes@94 | 471 | case G2STATUS:
|
nkeynes@929 | 472 | return g2_read_status();
|
nkeynes@94 | 473 | default:
|
nkeynes@929 | 474 | val = MMIO_READ(ASIC, reg);
|
nkeynes@929 | 475 | return val;
|
nkeynes@1 | 476 | }
|
nkeynes@929 | 477 |
|
nkeynes@1 | 478 | }
|
nkeynes@1 | 479 |
|
nkeynes@975 | 480 | MMIO_REGION_READ_DEFSUBFNS(ASIC)
|
nkeynes@975 | 481 |
|
nkeynes@929 | 482 | MMIO_REGION_WRITE_FN( ASIC, reg, val )
|
nkeynes@1 | 483 | {
|
nkeynes@929 | 484 | reg &= 0xFFF;
|
nkeynes@2 | 485 | switch( reg ) {
|
nkeynes@125 | 486 | case PIRQ1:
|
nkeynes@736 | 487 | break; /* Treat this as read-only for the moment */
|
nkeynes@56 | 488 | case PIRQ0:
|
nkeynes@736 | 489 | val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
|
nkeynes@736 | 490 | MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
|
nkeynes@736 | 491 | asic_check_cleared_events();
|
nkeynes@736 | 492 | break;
|
nkeynes@56 | 493 | case PIRQ2:
|
nkeynes@736 | 494 | /* Clear any events */
|
nkeynes@736 | 495 | val = MMIO_READ(ASIC, reg)&(~val);
|
nkeynes@736 | 496 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@736 | 497 | if( val == 0 ) { /* all clear - clear the cascade bit */
|
nkeynes@736 | 498 | MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
|
nkeynes@736 | 499 | }
|
nkeynes@736 | 500 | asic_check_cleared_events();
|
nkeynes@736 | 501 | break;
|
nkeynes@594 | 502 | case IRQA0:
|
nkeynes@594 | 503 | case IRQA1:
|
nkeynes@594 | 504 | case IRQA2:
|
nkeynes@594 | 505 | case IRQB0:
|
nkeynes@594 | 506 | case IRQB1:
|
nkeynes@594 | 507 | case IRQB2:
|
nkeynes@594 | 508 | case IRQC0:
|
nkeynes@594 | 509 | case IRQC1:
|
nkeynes@594 | 510 | case IRQC2:
|
nkeynes@736 | 511 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@736 | 512 | asic_event_mask_changed();
|
nkeynes@736 | 513 | break;
|
nkeynes@244 | 514 | case SYSRESET:
|
nkeynes@736 | 515 | if( val == 0x7611 ) {
|
nkeynes@736 | 516 | dreamcast_reset();
|
nkeynes@736 | 517 | } else {
|
nkeynes@736 | 518 | WARN( "Unknown value %08X written to SYSRESET port", val );
|
nkeynes@736 | 519 | }
|
nkeynes@736 | 520 | break;
|
nkeynes@56 | 521 | case MAPLE_STATE:
|
nkeynes@1237 | 522 | maple_set_dma_state( val );
|
nkeynes@736 | 523 | break;
|
nkeynes@325 | 524 | case PVRDMADEST:
|
nkeynes@736 | 525 | MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
|
nkeynes@736 | 526 | break;
|
nkeynes@325 | 527 | case PVRDMACNT:
|
nkeynes@736 | 528 | MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
|
nkeynes@736 | 529 | break;
|
nkeynes@56 | 530 | case PVRDMACTL: /* Initiate PVR DMA transfer */
|
nkeynes@736 | 531 | val = val & 0x01;
|
nkeynes@736 | 532 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@736 | 533 | if( val == 1 ) {
|
nkeynes@736 | 534 | pvr_dma_transfer();
|
nkeynes@736 | 535 | }
|
nkeynes@736 | 536 | break;
|
nkeynes@728 | 537 | case SORTDMATBL: case SORTDMADATA:
|
nkeynes@728 | 538 | MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
|
nkeynes@728 | 539 | break;
|
nkeynes@753 | 540 | case SORTDMATSIZ: case SORTDMAASIZ:
|
nkeynes@728 | 541 | MMIO_WRITE( ASIC, reg, (val & 1) );
|
nkeynes@728 | 542 | break;
|
nkeynes@728 | 543 | case SORTDMACTL:
|
nkeynes@728 | 544 | val = val & 1;
|
nkeynes@728 | 545 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@728 | 546 | if( val == 1 ) {
|
nkeynes@728 | 547 | sort_dma_transfer();
|
nkeynes@728 | 548 | }
|
nkeynes@728 | 549 | break;
|
nkeynes@325 | 550 | case MAPLE_DMA:
|
nkeynes@736 | 551 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@736 | 552 | break;
|
nkeynes@125 | 553 | default:
|
nkeynes@736 | 554 | MMIO_WRITE( ASIC, reg, val );
|
nkeynes@2 | 555 | }
|
nkeynes@1 | 556 | }
|
nkeynes@1 | 557 |
|
nkeynes@1 | 558 | MMIO_REGION_READ_FN( EXTDMA, reg )
|
nkeynes@1 | 559 | {
|
nkeynes@56 | 560 | uint32_t val;
|
nkeynes@929 | 561 | reg &= 0xFFF;
|
nkeynes@244 | 562 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
|
nkeynes@929 | 563 | return 0xFFFFFFFF; /* disabled */
|
nkeynes@244 | 564 | }
|
nkeynes@244 | 565 |
|
nkeynes@1 | 566 | switch( reg ) {
|
nkeynes@158 | 567 | case IDEALTSTATUS:
|
nkeynes@929 | 568 | val = idereg.status;
|
nkeynes@929 | 569 | return val;
|
nkeynes@158 | 570 | case IDEDATA: return ide_read_data_pio( );
|
nkeynes@158 | 571 | case IDEFEAT: return idereg.error;
|
nkeynes@158 | 572 | case IDECOUNT:return idereg.count;
|
nkeynes@342 | 573 | case IDELBA0: return ide_get_drive_status();
|
nkeynes@158 | 574 | case IDELBA1: return idereg.lba1;
|
nkeynes@158 | 575 | case IDELBA2: return idereg.lba2;
|
nkeynes@158 | 576 | case IDEDEV: return idereg.device;
|
nkeynes@158 | 577 | case IDECMD:
|
nkeynes@929 | 578 | val = ide_read_status();
|
nkeynes@929 | 579 | return val;
|
nkeynes@158 | 580 | default:
|
nkeynes@929 | 581 | val = MMIO_READ( EXTDMA, reg );
|
nkeynes@736 | 582 | return val;
|
nkeynes@1 | 583 | }
|
nkeynes@1 | 584 | }
|
nkeynes@975 | 585 | MMIO_REGION_READ_DEFSUBFNS(EXTDMA)
|
nkeynes@975 | 586 |
|
nkeynes@1 | 587 |
|
nkeynes@1 | 588 | MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
|
nkeynes@1 | 589 | {
|
nkeynes@929 | 590 | reg &= 0xFFF;
|
nkeynes@244 | 591 | if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
|
nkeynes@736 | 592 | return; /* disabled */
|
nkeynes@244 | 593 | }
|
nkeynes@244 | 594 |
|
nkeynes@2 | 595 | switch( reg ) {
|
nkeynes@125 | 596 | case IDEALTSTATUS: /* Device control */
|
nkeynes@736 | 597 | ide_write_control( val );
|
nkeynes@736 | 598 | break;
|
nkeynes@125 | 599 | case IDEDATA:
|
nkeynes@736 | 600 | ide_write_data_pio( val );
|
nkeynes@736 | 601 | break;
|
nkeynes@125 | 602 | case IDEFEAT:
|
nkeynes@736 | 603 | if( ide_can_write_regs() )
|
nkeynes@736 | 604 | idereg.feature = (uint8_t)val;
|
nkeynes@736 | 605 | break;
|
nkeynes@125 | 606 | case IDECOUNT:
|
nkeynes@736 | 607 | if( ide_can_write_regs() )
|
nkeynes@736 | 608 | idereg.count = (uint8_t)val;
|
nkeynes@736 | 609 | break;
|
nkeynes@125 | 610 | case IDELBA0:
|
nkeynes@736 | 611 | if( ide_can_write_regs() )
|
nkeynes@736 | 612 | idereg.lba0 = (uint8_t)val;
|
nkeynes@736 | 613 | break;
|
nkeynes@125 | 614 | case IDELBA1:
|
nkeynes@736 | 615 | if( ide_can_write_regs() )
|
nkeynes@736 | 616 | idereg.lba1 = (uint8_t)val;
|
nkeynes@736 | 617 | break;
|
nkeynes@125 | 618 | case IDELBA2:
|
nkeynes@736 | 619 | if( ide_can_write_regs() )
|
nkeynes@736 | 620 | idereg.lba2 = (uint8_t)val;
|
nkeynes@736 | 621 | break;
|
nkeynes@125 | 622 | case IDEDEV:
|
nkeynes@736 | 623 | if( ide_can_write_regs() )
|
nkeynes@736 | 624 | idereg.device = (uint8_t)val;
|
nkeynes@736 | 625 | break;
|
nkeynes@125 | 626 | case IDECMD:
|
nkeynes@736 | 627 | if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
|
nkeynes@736 | 628 | ide_write_command( (uint8_t)val );
|
nkeynes@736 | 629 | }
|
nkeynes@736 | 630 | break;
|
nkeynes@334 | 631 | case IDEDMASH4:
|
nkeynes@736 | 632 | MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
|
nkeynes@736 | 633 | break;
|
nkeynes@334 | 634 | case IDEDMASIZ:
|
nkeynes@736 | 635 | MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
|
nkeynes@736 | 636 | break;
|
nkeynes@549 | 637 | case IDEDMADIR:
|
nkeynes@736 | 638 | MMIO_WRITE( EXTDMA, reg, val & 1 );
|
nkeynes@736 | 639 | break;
|
nkeynes@125 | 640 | case IDEDMACTL1:
|
nkeynes@125 | 641 | case IDEDMACTL2:
|
nkeynes@736 | 642 | MMIO_WRITE( EXTDMA, reg, val & 0x01 );
|
nkeynes@736 | 643 | asic_ide_dma_transfer( );
|
nkeynes@736 | 644 | break;
|
nkeynes@244 | 645 | case IDEACTIVATE:
|
nkeynes@736 | 646 | if( val == 0x001FFFFF ) {
|
nkeynes@736 | 647 | idereg.interface_enabled = TRUE;
|
nkeynes@736 | 648 | /* Conventional wisdom says that this is necessary but not
|
nkeynes@736 | 649 | * sufficient to enable the IDE interface.
|
nkeynes@736 | 650 | */
|
nkeynes@736 | 651 | } else if( val == 0x000042FE ) {
|
nkeynes@736 | 652 | idereg.interface_enabled = FALSE;
|
nkeynes@736 | 653 | }
|
nkeynes@736 | 654 | break;
|
nkeynes@549 | 655 | case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
|
nkeynes@549 | 656 | case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
|
nkeynes@549 | 657 | case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
|
nkeynes@549 | 658 | case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
|
nkeynes@736 | 659 | MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
|
nkeynes@736 | 660 | break;
|
nkeynes@549 | 661 | case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
|
nkeynes@736 | 662 | MMIO_WRITE( EXTDMA, reg, val & 0x07 );
|
nkeynes@736 | 663 | break;
|
nkeynes@549 | 664 | case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
|
nkeynes@736 | 665 | MMIO_WRITE( EXTDMA, reg, val & 0x01 );
|
nkeynes@736 | 666 | break;
|
nkeynes@302 | 667 | case G2DMA0CTL1:
|
nkeynes@302 | 668 | case G2DMA0CTL2:
|
nkeynes@736 | 669 | MMIO_WRITE( EXTDMA, reg, val & 1);
|
nkeynes@736 | 670 | g2_dma_transfer( 0 );
|
nkeynes@736 | 671 | break;
|
nkeynes@302 | 672 | case G2DMA0STOP:
|
nkeynes@736 | 673 | MMIO_WRITE( EXTDMA, reg, val & 0x37 );
|
nkeynes@736 | 674 | break;
|
nkeynes@302 | 675 | case G2DMA1CTL1:
|
nkeynes@302 | 676 | case G2DMA1CTL2:
|
nkeynes@736 | 677 | MMIO_WRITE( EXTDMA, reg, val & 1);
|
nkeynes@736 | 678 | g2_dma_transfer( 1 );
|
nkeynes@736 | 679 | break;
|
nkeynes@279 | 680 |
|
nkeynes@302 | 681 | case G2DMA1STOP:
|
nkeynes@736 | 682 | MMIO_WRITE( EXTDMA, reg, val & 0x37 );
|
nkeynes@736 | 683 | break;
|
nkeynes@302 | 684 | case G2DMA2CTL1:
|
nkeynes@302 | 685 | case G2DMA2CTL2:
|
nkeynes@736 | 686 | MMIO_WRITE( EXTDMA, reg, val &1 );
|
nkeynes@736 | 687 | g2_dma_transfer( 2 );
|
nkeynes@736 | 688 | break;
|
nkeynes@302 | 689 | case G2DMA2STOP:
|
nkeynes@736 | 690 | MMIO_WRITE( EXTDMA, reg, val & 0x37 );
|
nkeynes@736 | 691 | break;
|
nkeynes@302 | 692 | case G2DMA3CTL1:
|
nkeynes@302 | 693 | case G2DMA3CTL2:
|
nkeynes@736 | 694 | MMIO_WRITE( EXTDMA, reg, val &1 );
|
nkeynes@736 | 695 | g2_dma_transfer( 3 );
|
nkeynes@736 | 696 | break;
|
nkeynes@302 | 697 | case G2DMA3STOP:
|
nkeynes@736 | 698 | MMIO_WRITE( EXTDMA, reg, val & 0x37 );
|
nkeynes@736 | 699 | break;
|
nkeynes@279 | 700 | case PVRDMA2CTL1:
|
nkeynes@279 | 701 | case PVRDMA2CTL2:
|
nkeynes@855 | 702 | MMIO_WRITE( EXTDMA, reg, val & 1 );
|
nkeynes@855 | 703 | pvr_dma2_transfer();
|
nkeynes@736 | 704 | break;
|
nkeynes@125 | 705 | default:
|
nkeynes@736 | 706 | MMIO_WRITE( EXTDMA, reg, val );
|
nkeynes@1 | 707 | }
|
nkeynes@1 | 708 | }
|
nkeynes@1 | 709 |
|