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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 929:fd8cb0c82f5f
prev921:6c0e9a8f5618
next931:430048ea8b71
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
file annotate diff log raw
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/**
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 * $Id$
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 *
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 * PVR2 (Video) Core module implementation and MMIO registers.
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 *
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 * Copyright (c) 2005 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#define MODULE pvr2_module
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#include <assert.h>
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#include "dream.h"
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#include "eventq.h"
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#include "display.h"
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#include "mem.h"
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#include "asic.h"
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#include "clock.h"
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#include "pvr2/pvr2.h"
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#include "pvr2/pvr2mmio.h"
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#include "pvr2/scene.h"
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#include "sh4/sh4.h"
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#define MMIO_IMPL
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#include "pvr2/pvr2mmio.h"
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unsigned char *video_base;
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#define MAX_RENDER_BUFFERS 4
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#define HPOS_PER_FRAME 0
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#define HPOS_PER_LINECOUNT 1
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static void pvr2_init( void );
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static void pvr2_reset( void );
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static uint32_t pvr2_run_slice( uint32_t );
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static void pvr2_save_state( FILE *f );
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static int pvr2_load_state( FILE *f );
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static void pvr2_update_raster_posn( uint32_t nanosecs );
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static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
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static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
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static render_buffer_t pvr2_next_render_buffer( );
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static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
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uint32_t pvr2_get_sync_status();
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void pvr2_display_frame( void );
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static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
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static int render_colour_formats[8] = {
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        COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
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        COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
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struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
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        pvr2_run_slice, NULL,
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        pvr2_save_state, pvr2_load_state };
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display_driver_t display_driver = NULL;
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struct pvr2_state {
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    uint32_t frame_count;
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    uint32_t line_count;
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    uint32_t line_remainder;
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    uint32_t cycles_run; /* Cycles already executed prior to main time slice */
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    uint32_t irq_hpos_line;
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    uint32_t irq_hpos_line_count;
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    uint32_t irq_hpos_mode;
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    uint32_t irq_hpos_time_ns; /* Time within the line */
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    uint32_t irq_vpos1;
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    uint32_t irq_vpos2;
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    uint32_t odd_even_field; /* 1 = odd, 0 = even */
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    int32_t palette_changed; /* TRUE if palette has changed since last render */
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    /* timing */
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    uint32_t dot_clock;
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    uint32_t total_lines;
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    uint32_t line_size;
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    uint32_t line_time_ns;
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    uint32_t vsync_lines;
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    uint32_t hsync_width_ns;
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    uint32_t front_porch_ns;
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    uint32_t back_porch_ns;
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    uint32_t retrace_start_line;
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    uint32_t retrace_end_line;
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    int32_t interlaced;
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} pvr2_state;
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static gchar *save_next_render_filename;
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static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
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static uint32_t render_buffer_count = 0;
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static render_buffer_t displayed_render_buffer = NULL;
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static uint32_t displayed_border_colour = 0;
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/**
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 * Event handler for the hpos callback
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 */
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static void pvr2_hpos_callback( int eventid ) {
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
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        pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
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        while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
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            pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
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        }
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    }
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    pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
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                                  pvr2_state.irq_hpos_time_ns );
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}
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/**
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 * Event handler for the scanline callbacks. Fires the corresponding
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 * ASIC event, and resets the timer for the next field.
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 */
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static void pvr2_scanline_callback( int eventid ) 
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{
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    asic_event( eventid );
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    if( eventid == EVENT_SCANLINE1 ) {
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        pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
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    } else {
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        pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
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    }
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}
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static void pvr2_gunpos_callback( int eventid ) 
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{
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    pvr2_update_raster_posn(sh4r.slice_cycle);
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    int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
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    MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
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    asic_event( EVENT_MAPLE_DMA );
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}
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static void pvr2_init( void )
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{
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    int i;
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    register_io_region( &mmio_region_PVR2 );
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    register_io_region( &mmio_region_PVR2PAL );
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    register_io_region( &mmio_region_PVR2TA );
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    register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
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    register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
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    register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
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    register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
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    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
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    texcache_init();
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    pvr2_reset();
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    pvr2_ta_reset();
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    save_next_render_filename = NULL;
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    for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
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        render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    displayed_render_buffer = NULL;
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    displayed_border_colour = 0;
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}
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static void pvr2_reset( void )
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{
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    int i;
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    pvr2_state.line_count = 0;
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    pvr2_state.line_remainder = 0;
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    pvr2_state.cycles_run = 0;
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    pvr2_state.irq_vpos1 = 0;
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    pvr2_state.irq_vpos2 = 0;
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    pvr2_state.dot_clock = PVR2_DOT_CLOCK;
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    pvr2_state.back_porch_ns = 4000;
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    pvr2_state.palette_changed = FALSE;
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    mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
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    mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
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    mmio_region_PVR2_write( YUV_ADDR, 0 );
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    mmio_region_PVR2_write( YUV_CFG, 0 );
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    pvr2_ta_init();
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    texcache_flush();
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    if( display_driver ) {
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        display_driver->display_blank(0);
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        for( i=0; i<render_buffer_count; i++ ) {
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            display_driver->destroy_render_buffer(render_buffers[i]);
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            render_buffers[i] = NULL;
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        }
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        render_buffer_count = 0;
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    }
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}
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void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
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{
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    struct frame_buffer fbuf;
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    fbuf.width = buffer->width;
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    fbuf.height = buffer->height;
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    fbuf.rowstride = fbuf.width*3;
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    fbuf.colour_format = COLFMT_BGR888;
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    fbuf.inverted = buffer->inverted;
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    fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
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    display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
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    write_png_to_stream( f, &fbuf );
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    g_free( fbuf.data );
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    fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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    fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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    fwrite( &buffer->address, sizeof(buffer->address), 1, f );
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    fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
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    int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
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    fwrite( &flushed, sizeof(flushed), 1, f );
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}
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render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
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{
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    frame_buffer_t frame = read_png_from_stream( f );
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    if( frame == NULL ) {
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        *status = FALSE;
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        return NULL;
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    }
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    *status = TRUE;
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    render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
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    if( buffer != NULL ) {
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        int32_t flushed;
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        fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
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        fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
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        fread( &buffer->address, sizeof(buffer->address), 1, f );
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        fread( &buffer->scale, sizeof(buffer->scale), 1, f );
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        fread( &flushed, sizeof(flushed), 1, f );
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        buffer->flushed = (gboolean)flushed;
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    } else {
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        fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
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                sizeof(buffer->address)+sizeof(buffer->scale)+
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                sizeof(int32_t), SEEK_CUR );
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    }
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    return buffer;
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}
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void pvr2_save_render_buffers( FILE *f )
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{
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    int i;
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    uint32_t has_frontbuffer;
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    fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
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    if( displayed_render_buffer != NULL ) {
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        has_frontbuffer = 1;
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        fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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        pvr2_save_render_buffer( f, displayed_render_buffer );
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    } else {
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        has_frontbuffer = 0;
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        fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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    }
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    for( i=0; i<render_buffer_count; i++ ) {
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        if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
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            pvr2_save_render_buffer( f, render_buffers[i] );
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        }
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    }
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}
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gboolean pvr2_load_render_buffers( FILE *f )
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{
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    uint32_t count, has_frontbuffer;
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    gboolean loadok;
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    int i;
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    fread( &count, sizeof(count), 1, f );
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    if( count > MAX_RENDER_BUFFERS ) {
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        return FALSE;
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    }
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    fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
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    for( i=0; i<render_buffer_count; i++ ) {
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        display_driver->destroy_render_buffer(render_buffers[i]);
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        render_buffers[i] = NULL;
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    }
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    render_buffer_count = 0;
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    if( has_frontbuffer ) {
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        displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
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        if( displayed_render_buffer != NULL )
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            display_driver->display_render_buffer( displayed_render_buffer );
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        else if( !loadok )
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            return FALSE;
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        count--;
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    }
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    for( i=0; i<count; i++ ) {
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        pvr2_load_render_buffer( f, &loadok );
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        if( !loadok )
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        	return FALSE;
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    }
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    return TRUE;
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}
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static void pvr2_save_state( FILE *f )
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{
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    pvr2_save_render_buffers( f );
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    fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
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    pvr2_ta_save_state( f );
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    pvr2_yuv_save_state( f );
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}
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   307
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   308
static int pvr2_load_state( FILE *f )
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   309
{
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    if( !pvr2_load_render_buffers(f) )
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        return 1;
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    if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
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        return 1;
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   314
    if( pvr2_ta_load_state(f) ) {
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   315
        return 1;
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   316
    }
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   317
    return pvr2_yuv_load_state(f);
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}
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/**
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 * Update the current raster position to the given number of nanoseconds,
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 * relative to the last time slice. (ie the raster will be adjusted forward
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 * by nanosecs - nanosecs_already_run_this_timeslice)
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 */
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static void pvr2_update_raster_posn( uint32_t nanosecs )
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   326
{
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    uint32_t old_line_count = pvr2_state.line_count;
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    if( pvr2_state.line_time_ns == 0 ) {
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   329
        return; /* do nothing */
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   330
    }
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   331
    pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
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    pvr2_state.cycles_run = nanosecs;
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    while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
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        pvr2_state.line_count ++;
nkeynes@736
   335
        pvr2_state.line_remainder -= pvr2_state.line_time_ns;
nkeynes@265
   336
    }
nkeynes@265
   337
nkeynes@265
   338
    if( pvr2_state.line_count >= pvr2_state.total_lines ) {
nkeynes@736
   339
        pvr2_state.line_count -= pvr2_state.total_lines;
nkeynes@736
   340
        if( pvr2_state.interlaced ) {
nkeynes@736
   341
            pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
nkeynes@736
   342
        }
nkeynes@265
   343
    }
nkeynes@265
   344
    if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
nkeynes@736
   345
            (old_line_count < pvr2_state.retrace_end_line ||
nkeynes@736
   346
                    old_line_count > pvr2_state.line_count) ) {
nkeynes@736
   347
        pvr2_state.frame_count++;
nkeynes@736
   348
        pvr2_display_frame();
nkeynes@265
   349
    }
nkeynes@265
   350
}
nkeynes@265
   351
nkeynes@133
   352
static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
nkeynes@133
   353
{
nkeynes@265
   354
    pvr2_update_raster_posn( nanosecs );
nkeynes@265
   355
    pvr2_state.cycles_run = 0;
nkeynes@133
   356
    return nanosecs;
nkeynes@133
   357
}
nkeynes@133
   358
nkeynes@133
   359
int pvr2_get_frame_count() 
nkeynes@133
   360
{
nkeynes@133
   361
    return pvr2_state.frame_count;
nkeynes@106
   362
}
nkeynes@106
   363
nkeynes@677
   364
void pvr2_redraw_display()
nkeynes@477
   365
{
nkeynes@677
   366
    if( display_driver != NULL ) {
nkeynes@677
   367
        if( displayed_render_buffer == NULL ) {
nkeynes@677
   368
            display_driver->display_blank(displayed_border_colour);
nkeynes@677
   369
        } else {
nkeynes@677
   370
            display_driver->display_render_buffer(displayed_render_buffer);
nkeynes@677
   371
        }
nkeynes@677
   372
    }
nkeynes@545
   373
}
nkeynes@545
   374
nkeynes@295
   375
gboolean pvr2_save_next_scene( const gchar *filename )
nkeynes@295
   376
{
nkeynes@674
   377
    if( save_next_render_filename != NULL ) {
nkeynes@736
   378
        g_free( save_next_render_filename );
nkeynes@295
   379
    } 
nkeynes@674
   380
    save_next_render_filename = g_strdup(filename);
nkeynes@295
   381
    return TRUE;
nkeynes@295
   382
}
nkeynes@295
   383
nkeynes@295
   384
nkeynes@295
   385
nkeynes@103
   386
/**
nkeynes@1
   387
 * Display the next frame, copying the current contents of video ram to
nkeynes@1
   388
 * the window. If the video configuration has changed, first recompute the
nkeynes@1
   389
 * new frame size/depth.
nkeynes@1
   390
 */
nkeynes@94
   391
void pvr2_display_frame( void )
nkeynes@1
   392
{
nkeynes@197
   393
    int dispmode = MMIO_READ( PVR2, DISP_MODE );
nkeynes@261
   394
    int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
nkeynes@335
   395
    gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
nkeynes@352
   396
nkeynes@352
   397
    if( display_driver == NULL ) {
nkeynes@736
   398
        return; /* can't really do anything much */
nkeynes@352
   399
    } else if( !bEnabled ) {
nkeynes@736
   400
        /* Output disabled == black */
nkeynes@736
   401
        displayed_render_buffer = NULL;
nkeynes@736
   402
        displayed_border_colour = 0;
nkeynes@736
   403
        display_driver->display_blank( 0 ); 
nkeynes@352
   404
    } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
nkeynes@736
   405
        /* Enabled but blanked - border colour */
nkeynes@736
   406
        displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
nkeynes@736
   407
        displayed_render_buffer = NULL;
nkeynes@736
   408
        display_driver->display_blank( displayed_border_colour );
nkeynes@352
   409
    } else {
nkeynes@736
   410
        /* Real output - determine dimensions etc */
nkeynes@736
   411
        struct frame_buffer fbuf;
nkeynes@736
   412
        uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
nkeynes@736
   413
        int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
nkeynes@736
   414
        int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
nkeynes@352
   415
nkeynes@736
   416
        fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
nkeynes@916
   417
        fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
nkeynes@736
   418
        fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
nkeynes@916
   419
        fbuf.size = (vid_ppl << 2) * fbuf.height;
nkeynes@736
   420
        fbuf.rowstride = (vid_ppl + vid_stride) << 2;
nkeynes@352
   421
nkeynes@736
   422
        /* Determine the field to display, and deinterlace if possible */
nkeynes@736
   423
        if( pvr2_state.interlaced ) {
nkeynes@736
   424
            if( vid_ppl == vid_stride ) { /* Magic deinterlace */
nkeynes@736
   425
                fbuf.height = fbuf.height << 1;
nkeynes@736
   426
                fbuf.rowstride = vid_ppl << 2;
nkeynes@736
   427
                fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   428
            } else { 
nkeynes@736
   429
                /* Just display the field as is, folks. This is slightly tricky -
nkeynes@736
   430
                 * we pick the field based on which frame is about to come through,
nkeynes@736
   431
                 * which may not be the same as the odd_even_field.
nkeynes@736
   432
                 */
nkeynes@736
   433
                gboolean oddfield = pvr2_state.odd_even_field;
nkeynes@736
   434
                if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
nkeynes@736
   435
                    oddfield = !oddfield;
nkeynes@736
   436
                }
nkeynes@736
   437
                if( oddfield ) {
nkeynes@736
   438
                    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   439
                } else {
nkeynes@736
   440
                    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@736
   441
                }
nkeynes@736
   442
            }
nkeynes@736
   443
        } else {
nkeynes@736
   444
            fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   445
        }
nkeynes@736
   446
        fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@736
   447
        fbuf.inverted = FALSE;
nkeynes@736
   448
        fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
nkeynes@352
   449
nkeynes@736
   450
        render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
nkeynes@736
   451
        if( rbuf == NULL ) {
nkeynes@736
   452
            rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
nkeynes@736
   453
        }
nkeynes@736
   454
        displayed_render_buffer = rbuf;
nkeynes@736
   455
        if( rbuf != NULL ) {
nkeynes@736
   456
            display_driver->display_render_buffer( rbuf );
nkeynes@736
   457
        }
nkeynes@1
   458
    }
nkeynes@1
   459
}
nkeynes@1
   460
nkeynes@197
   461
/**
nkeynes@197
   462
 * This has to handle every single register individually as they all get masked 
nkeynes@197
   463
 * off differently (and its easier to do it at write time)
nkeynes@197
   464
 */
nkeynes@929
   465
MMIO_REGION_WRITE_FN( PVR2, reg, val )
nkeynes@1
   466
{
nkeynes@929
   467
    reg &= 0xFFF;
nkeynes@1
   468
    if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
nkeynes@1
   469
        MMIO_WRITE( PVR2, reg, val );
nkeynes@1
   470
        return;
nkeynes@1
   471
    }
nkeynes@736
   472
nkeynes@1
   473
    switch(reg) {
nkeynes@189
   474
    case PVRID:
nkeynes@189
   475
    case PVRVER:
nkeynes@261
   476
    case GUNPOS: /* Read only registers */
nkeynes@736
   477
        break;
nkeynes@197
   478
    case PVRRESET:
nkeynes@736
   479
        val &= 0x00000007; /* Do stuff? */
nkeynes@736
   480
        MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   481
        break;
nkeynes@295
   482
    case RENDER_START: /* Don't really care what value */
nkeynes@736
   483
        if( save_next_render_filename != NULL ) {
nkeynes@736
   484
            if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
nkeynes@736
   485
                INFO( "Saved scene to %s", save_next_render_filename);
nkeynes@736
   486
            }
nkeynes@736
   487
            g_free( save_next_render_filename );
nkeynes@736
   488
            save_next_render_filename = NULL;
nkeynes@736
   489
        }
nkeynes@736
   490
        pvr2_scene_read();
nkeynes@736
   491
        render_buffer_t buffer = pvr2_next_render_buffer();
nkeynes@736
   492
        if( buffer != NULL ) {
nkeynes@736
   493
            pvr2_scene_render( buffer );
nkeynes@871
   494
            if( buffer->address < PVR2_RAM_BASE ) {
nkeynes@871
   495
                // Flush immediately - optimize this later. Otherwise this gets
nkeynes@871
   496
                // complicated very quickly trying to second-guess how it's
nkeynes@871
   497
                // going to be used as a texture.
nkeynes@921
   498
                pvr2_finish_render_buffer( buffer );
nkeynes@871
   499
                pvr2_render_buffer_copy_to_sh4( buffer );
nkeynes@871
   500
            }
nkeynes@736
   501
        }
nkeynes@736
   502
        asic_event( EVENT_PVR_RENDER_DONE );
nkeynes@736
   503
        break;
nkeynes@191
   504
    case RENDER_POLYBASE:
nkeynes@736
   505
        MMIO_WRITE( PVR2, reg, val&0x00F00000 );
nkeynes@736
   506
        break;
nkeynes@191
   507
    case RENDER_TSPCFG:
nkeynes@736
   508
        MMIO_WRITE( PVR2, reg, val&0x00010101 );
nkeynes@736
   509
        break;
nkeynes@197
   510
    case DISP_BORDER:
nkeynes@736
   511
        MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
nkeynes@736
   512
        break;
nkeynes@197
   513
    case DISP_MODE:
nkeynes@736
   514
        MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
nkeynes@736
   515
        break;
nkeynes@191
   516
    case RENDER_MODE:
nkeynes@736
   517
        MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
nkeynes@736
   518
        break;
nkeynes@191
   519
    case RENDER_SIZE:
nkeynes@736
   520
        MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@736
   521
        break;
nkeynes@197
   522
    case DISP_ADDR1:
nkeynes@736
   523
        val &= 0x00FFFFFC;
nkeynes@736
   524
        MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   525
        pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   526
        break;
nkeynes@197
   527
    case DISP_ADDR2:
nkeynes@736
   528
        MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@736
   529
        pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   530
        break;
nkeynes@197
   531
    case DISP_SIZE:
nkeynes@736
   532
        MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
nkeynes@736
   533
        break;
nkeynes@191
   534
    case RENDER_ADDR1:
nkeynes@191
   535
    case RENDER_ADDR2:
nkeynes@736
   536
        MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
nkeynes@736
   537
        break;
nkeynes@191
   538
    case RENDER_HCLIP:
nkeynes@736
   539
        MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
nkeynes@736
   540
        break;
nkeynes@191
   541
    case RENDER_VCLIP:
nkeynes@736
   542
        MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   543
        break;
nkeynes@197
   544
    case DISP_HPOSIRQ:
nkeynes@736
   545
        MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
nkeynes@736
   546
        pvr2_state.irq_hpos_line = val & 0x03FF;
nkeynes@736
   547
        pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
nkeynes@736
   548
        pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
nkeynes@736
   549
        switch( pvr2_state.irq_hpos_mode ) {
nkeynes@736
   550
        case 3: /* Reserved - treat as 0 */
nkeynes@736
   551
        case 0: /* Once per frame at specified line */
nkeynes@736
   552
            pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
nkeynes@736
   553
            break;
nkeynes@736
   554
        case 2: /* Once per line - as per-line-count */
nkeynes@736
   555
            pvr2_state.irq_hpos_line = 1;
nkeynes@736
   556
            pvr2_state.irq_hpos_mode = 1;
nkeynes@736
   557
        case 1: /* Once per N lines */
nkeynes@736
   558
            pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
nkeynes@736
   559
            pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
nkeynes@736
   560
            pvr2_state.irq_hpos_line_count;
nkeynes@736
   561
            while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
nkeynes@736
   562
                pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
nkeynes@736
   563
            }
nkeynes@736
   564
            pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
nkeynes@736
   565
        }
nkeynes@736
   566
        pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
nkeynes@736
   567
                                      pvr2_state.irq_hpos_time_ns );
nkeynes@736
   568
        break;
nkeynes@736
   569
        case DISP_VPOSIRQ:
nkeynes@736
   570
            val = val & 0x03FF03FF;
nkeynes@736
   571
            pvr2_state.irq_vpos1 = (val >> 16);
nkeynes@736
   572
            pvr2_state.irq_vpos2 = val & 0x03FF;
nkeynes@736
   573
            pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   574
            pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@736
   575
            pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@736
   576
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   577
            break;
nkeynes@736
   578
        case RENDER_NEARCLIP:
nkeynes@736
   579
            MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
nkeynes@736
   580
            break;
nkeynes@736
   581
        case RENDER_SHADOW:
nkeynes@736
   582
            MMIO_WRITE( PVR2, reg, val&0x000001FF );
nkeynes@736
   583
            break;
nkeynes@736
   584
        case RENDER_OBJCFG:
nkeynes@736
   585
            MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@736
   586
            break;
nkeynes@736
   587
        case RENDER_TSPCLIP:
nkeynes@736
   588
            MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
nkeynes@736
   589
            break;
nkeynes@736
   590
        case RENDER_FARCLIP:
nkeynes@736
   591
            MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
nkeynes@736
   592
            break;
nkeynes@736
   593
        case RENDER_BGPLANE:
nkeynes@736
   594
            MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@736
   595
            break;
nkeynes@736
   596
        case RENDER_ISPCFG:
nkeynes@736
   597
            MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
nkeynes@736
   598
            break;
nkeynes@736
   599
        case VRAM_CFG1:
nkeynes@736
   600
            MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@736
   601
            break;
nkeynes@736
   602
        case VRAM_CFG2:
nkeynes@736
   603
            MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
nkeynes@736
   604
            break;
nkeynes@736
   605
        case VRAM_CFG3:
nkeynes@736
   606
            MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
nkeynes@736
   607
            break;
nkeynes@736
   608
        case RENDER_FOGTBLCOL:
nkeynes@736
   609
        case RENDER_FOGVRTCOL:
nkeynes@736
   610
            MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
nkeynes@736
   611
            break;
nkeynes@736
   612
        case RENDER_FOGCOEFF:
nkeynes@736
   613
            MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@736
   614
            break;
nkeynes@736
   615
        case RENDER_CLAMPHI:
nkeynes@736
   616
        case RENDER_CLAMPLO:
nkeynes@736
   617
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   618
            break;
nkeynes@736
   619
        case RENDER_TEXSIZE:
nkeynes@736
   620
            MMIO_WRITE( PVR2, reg, val&0x00031F1F );
nkeynes@736
   621
            break;
nkeynes@736
   622
        case RENDER_PALETTE:
nkeynes@736
   623
            MMIO_WRITE( PVR2, reg, val&0x00000003 );
nkeynes@736
   624
            break;
nkeynes@736
   625
        case RENDER_ALPHA_REF:
nkeynes@736
   626
            MMIO_WRITE( PVR2, reg, val&0x000000FF );
nkeynes@736
   627
            break;
nkeynes@736
   628
            /********** CRTC registers *************/
nkeynes@736
   629
        case DISP_HBORDER:
nkeynes@736
   630
        case DISP_VBORDER:
nkeynes@736
   631
            MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   632
            break;
nkeynes@736
   633
        case DISP_TOTAL:
nkeynes@736
   634
            val = val & 0x03FF03FF;
nkeynes@736
   635
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   636
            pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@736
   637
            pvr2_state.total_lines = (val >> 16) + 1;
nkeynes@736
   638
            pvr2_state.line_size = (val & 0x03FF) + 1;
nkeynes@736
   639
            pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
nkeynes@736
   640
            pvr2_state.retrace_end_line = 0x2A;
nkeynes@736
   641
            pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
nkeynes@736
   642
            pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
nkeynes@736
   643
            pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
nkeynes@736
   644
            pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
nkeynes@736
   645
                                          pvr2_state.irq_hpos_time_ns );
nkeynes@736
   646
            break;
nkeynes@736
   647
        case DISP_SYNCCFG:
nkeynes@736
   648
            MMIO_WRITE( PVR2, reg, val&0x000003FF );
nkeynes@736
   649
            pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
nkeynes@736
   650
            break;
nkeynes@736
   651
        case DISP_SYNCTIME:
nkeynes@736
   652
            pvr2_state.vsync_lines = (val >> 8) & 0x0F;
nkeynes@736
   653
            pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
nkeynes@736
   654
            MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
nkeynes@736
   655
            break;
nkeynes@736
   656
        case DISP_CFG2:
nkeynes@736
   657
            MMIO_WRITE( PVR2, reg, val&0x003F01FF );
nkeynes@736
   658
            break;
nkeynes@736
   659
        case DISP_HPOS:
nkeynes@736
   660
            val = val & 0x03FF;
nkeynes@736
   661
            pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
nkeynes@736
   662
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   663
            break;
nkeynes@736
   664
        case DISP_VPOS:
nkeynes@736
   665
            MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
nkeynes@736
   666
            break;
nkeynes@261
   667
nkeynes@736
   668
            /*********** Tile accelerator registers ***********/
nkeynes@736
   669
        case TA_POLYPOS:
nkeynes@736
   670
        case TA_LISTPOS:
nkeynes@736
   671
            /* Readonly registers */
nkeynes@736
   672
            break;
nkeynes@736
   673
        case TA_TILEBASE:
nkeynes@736
   674
        case TA_LISTEND:
nkeynes@736
   675
        case TA_LISTBASE:
nkeynes@736
   676
            MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
nkeynes@736
   677
            break;
nkeynes@736
   678
        case RENDER_TILEBASE:
nkeynes@736
   679
        case TA_POLYBASE:
nkeynes@736
   680
        case TA_POLYEND:
nkeynes@736
   681
            MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
nkeynes@736
   682
            break;
nkeynes@736
   683
        case TA_TILESIZE:
nkeynes@736
   684
            MMIO_WRITE( PVR2, reg, val&0x000F003F );
nkeynes@736
   685
            break;
nkeynes@736
   686
        case TA_TILECFG:
nkeynes@736
   687
            MMIO_WRITE( PVR2, reg, val&0x00133333 );
nkeynes@736
   688
            break;
nkeynes@736
   689
        case TA_INIT:
nkeynes@736
   690
            if( val & 0x80000000 )
nkeynes@736
   691
                pvr2_ta_init();
nkeynes@736
   692
            break;
nkeynes@736
   693
        case TA_REINIT:
nkeynes@736
   694
            break;
nkeynes@736
   695
            /**************** Scaler registers? ****************/
nkeynes@736
   696
        case RENDER_SCALER:
nkeynes@736
   697
            MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
nkeynes@736
   698
            break;
nkeynes@261
   699
nkeynes@736
   700
        case YUV_ADDR:
nkeynes@736
   701
            val = val & 0x00FFFFF8;
nkeynes@736
   702
            MMIO_WRITE( PVR2, reg, val );
nkeynes@736
   703
            pvr2_yuv_init( val );
nkeynes@736
   704
            break;
nkeynes@736
   705
        case YUV_CFG:
nkeynes@736
   706
            MMIO_WRITE( PVR2, reg, val&0x01013F3F );
nkeynes@736
   707
            pvr2_yuv_set_config(val);
nkeynes@736
   708
            break;
nkeynes@261
   709
nkeynes@736
   710
            /**************** Unknowns ***************/
nkeynes@736
   711
        case PVRUNK1:
nkeynes@736
   712
            MMIO_WRITE( PVR2, reg, val&0x000007FF );
nkeynes@736
   713
            break;
nkeynes@736
   714
        case PVRUNK2:
nkeynes@736
   715
            MMIO_WRITE( PVR2, reg, val&0x00000007 );
nkeynes@736
   716
            break;
nkeynes@736
   717
        case PVRUNK3:
nkeynes@736
   718
            MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
nkeynes@736
   719
            break;
nkeynes@736
   720
        case PVRUNK5:
nkeynes@736
   721
            MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
nkeynes@736
   722
            break;
nkeynes@736
   723
        case PVRUNK7:
nkeynes@736
   724
            MMIO_WRITE( PVR2, reg, val&0x00000001 );
nkeynes@736
   725
            break;
nkeynes@736
   726
        case PVRUNK8:
nkeynes@736
   727
            MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
nkeynes@736
   728
            break;
nkeynes@1
   729
    }
nkeynes@1
   730
}
nkeynes@1
   731
nkeynes@261
   732
/**
nkeynes@261
   733
 * Calculate the current read value of the syncstat register, using
nkeynes@261
   734
 * the current SH4 clock time as an offset from the last timeslice.
nkeynes@261
   735
 * The register reads (LSB to MSB) as:
nkeynes@261
   736
 *     0..9  Current scan line
nkeynes@261
   737
 *     10    Odd/even field (1 = odd, 0 = even)
nkeynes@261
   738
 *     11    Display active (including border and overscan)
nkeynes@261
   739
 *     12    Horizontal sync off
nkeynes@261
   740
 *     13    Vertical sync off
nkeynes@261
   741
 * Note this method is probably incorrect for anything other than straight
nkeynes@265
   742
 * interlaced PAL/NTSC, and needs further testing. 
nkeynes@261
   743
 */
nkeynes@261
   744
uint32_t pvr2_get_sync_status()
nkeynes@261
   745
{
nkeynes@265
   746
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@265
   747
    uint32_t result = pvr2_state.line_count;
nkeynes@261
   748
nkeynes@265
   749
    if( pvr2_state.odd_even_field ) {
nkeynes@736
   750
        result |= 0x0400;
nkeynes@261
   751
    }
nkeynes@265
   752
    if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
nkeynes@736
   753
        if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
nkeynes@736
   754
            result |= 0x1000; /* !HSYNC */
nkeynes@736
   755
        }
nkeynes@736
   756
        if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@736
   757
            if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
nkeynes@736
   758
                result |= 0x2800; /* Display active */
nkeynes@736
   759
            } else {
nkeynes@736
   760
                result |= 0x2000; /* Front porch */
nkeynes@736
   761
            }
nkeynes@736
   762
        }
nkeynes@261
   763
    } else {
nkeynes@736
   764
        if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
nkeynes@736
   765
            if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
nkeynes@736
   766
                result |= 0x3800; /* Display active */
nkeynes@736
   767
            } else {
nkeynes@736
   768
                result |= 0x3000;
nkeynes@736
   769
            }
nkeynes@736
   770
        } else {
nkeynes@736
   771
            result |= 0x1000; /* Back porch */
nkeynes@736
   772
        }
nkeynes@261
   773
    }
nkeynes@261
   774
    return result;
nkeynes@261
   775
}
nkeynes@261
   776
nkeynes@265
   777
/**
nkeynes@265
   778
 * Schedule a "scanline" event. This actually goes off at
nkeynes@265
   779
 * 2 * line in even fields and 2 * line + 1 in odd fields.
nkeynes@265
   780
 * Otherwise this behaves as per pvr2_schedule_line_event().
nkeynes@265
   781
 * The raster position should be updated before calling this
nkeynes@265
   782
 * method.
nkeynes@304
   783
 * @param eventid Event to fire at the specified time
nkeynes@304
   784
 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
nkeynes@304
   785
 *  displays). 
nkeynes@304
   786
 * @param hpos_ns Nanoseconds into the line at which to fire.
nkeynes@265
   787
 */
nkeynes@304
   788
static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
nkeynes@265
   789
{
nkeynes@265
   790
    uint32_t field = pvr2_state.odd_even_field;
nkeynes@265
   791
    if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
nkeynes@736
   792
        field = !field;
nkeynes@265
   793
    }
nkeynes@304
   794
    if( hpos_ns > pvr2_state.line_time_ns ) {
nkeynes@736
   795
        hpos_ns = pvr2_state.line_time_ns;
nkeynes@304
   796
    }
nkeynes@265
   797
nkeynes@265
   798
    line <<= 1;
nkeynes@265
   799
    if( field ) {
nkeynes@736
   800
        line += 1;
nkeynes@265
   801
    }
nkeynes@736
   802
nkeynes@274
   803
    if( line < pvr2_state.total_lines ) {
nkeynes@736
   804
        uint32_t lines;
nkeynes@736
   805
        uint32_t time;
nkeynes@736
   806
        if( line <= pvr2_state.line_count ) {
nkeynes@736
   807
            lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
nkeynes@736
   808
        } else {
nkeynes@736
   809
            lines = (line - pvr2_state.line_count);
nkeynes@736
   810
        }
nkeynes@736
   811
        if( lines <= minimum_lines ) {
nkeynes@736
   812
            lines += pvr2_state.total_lines;
nkeynes@736
   813
        }
nkeynes@736
   814
        time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
nkeynes@736
   815
        event_schedule( eventid, time );
nkeynes@274
   816
    } else {
nkeynes@736
   817
        event_cancel( eventid );
nkeynes@274
   818
    }
nkeynes@265
   819
}
nkeynes@265
   820
nkeynes@850
   821
void pvr2_queue_gun_event( int xpos, int ypos )
nkeynes@850
   822
{
nkeynes@850
   823
    pvr2_update_raster_posn(sh4r.slice_cycle);
nkeynes@850
   824
    pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,  
nkeynes@850
   825
            (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns ); 
nkeynes@850
   826
}
nkeynes@850
   827
nkeynes@1
   828
MMIO_REGION_READ_FN( PVR2, reg )
nkeynes@1
   829
{
nkeynes@929
   830
    reg &= 0xFFF;
nkeynes@1
   831
    switch( reg ) {
nkeynes@736
   832
    case DISP_SYNCSTAT:
nkeynes@736
   833
        return pvr2_get_sync_status();
nkeynes@736
   834
    default:
nkeynes@736
   835
        return MMIO_READ( PVR2, reg );
nkeynes@1
   836
    }
nkeynes@1
   837
}
nkeynes@19
   838
nkeynes@337
   839
MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
nkeynes@337
   840
{
nkeynes@929
   841
    reg &= 0xFFF;
nkeynes@337
   842
    MMIO_WRITE( PVR2PAL, reg, val );
nkeynes@337
   843
    pvr2_state.palette_changed = TRUE;
nkeynes@337
   844
}
nkeynes@337
   845
nkeynes@337
   846
void pvr2_check_palette_changed()
nkeynes@337
   847
{
nkeynes@337
   848
    if( pvr2_state.palette_changed ) {
nkeynes@736
   849
        texcache_invalidate_palette();
nkeynes@736
   850
        pvr2_state.palette_changed = FALSE;
nkeynes@337
   851
    }
nkeynes@337
   852
}
nkeynes@337
   853
nkeynes@337
   854
MMIO_REGION_READ_DEFFN( PVR2PAL );
nkeynes@85
   855
nkeynes@19
   856
void pvr2_set_base_address( uint32_t base ) 
nkeynes@19
   857
{
nkeynes@197
   858
    mmio_region_PVR2_write( DISP_ADDR1, base );
nkeynes@19
   859
}
nkeynes@56
   860
nkeynes@56
   861
nkeynes@65
   862
nkeynes@98
   863
nkeynes@929
   864
MMIO_REGION_READ_FN( PVR2TA, reg )
nkeynes@56
   865
{
nkeynes@56
   866
    return 0xFFFFFFFF;
nkeynes@56
   867
}
nkeynes@56
   868
nkeynes@929
   869
MMIO_REGION_WRITE_FN( PVR2TA, reg, val )
nkeynes@56
   870
{
nkeynes@433
   871
    pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
nkeynes@56
   872
}
nkeynes@56
   873
nkeynes@856
   874
render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
nkeynes@856
   875
{
nkeynes@856
   876
    if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
nkeynes@856
   877
        render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
nkeynes@856
   878
        buffer->address = addr;
nkeynes@856
   879
        return buffer;
nkeynes@856
   880
    }
nkeynes@856
   881
    return NULL;
nkeynes@856
   882
}
nkeynes@856
   883
nkeynes@856
   884
void pvr2_destroy_render_buffer( render_buffer_t buffer )
nkeynes@856
   885
{
nkeynes@856
   886
    if( !buffer->flushed )
nkeynes@856
   887
        pvr2_render_buffer_copy_to_sh4( buffer );
nkeynes@856
   888
     display_driver->destroy_render_buffer( buffer );
nkeynes@856
   889
}
nkeynes@856
   890
nkeynes@856
   891
void pvr2_finish_render_buffer( render_buffer_t buffer )
nkeynes@856
   892
{
nkeynes@856
   893
    display_driver->finish_render( buffer );
nkeynes@856
   894
}
nkeynes@856
   895
nkeynes@352
   896
/**
nkeynes@352
   897
 * Find the render buffer corresponding to the requested output frame
nkeynes@352
   898
 * (does not consider texture renders). 
nkeynes@352
   899
 * @return the render_buffer if found, or null if no such buffer.
nkeynes@352
   900
 *
nkeynes@352
   901
 * Note: Currently does not consider "partial matches", ie partial
nkeynes@352
   902
 * frame overlap - it probably needs to do this.
nkeynes@352
   903
 */
nkeynes@352
   904
render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
nkeynes@352
   905
{
nkeynes@352
   906
    int i;
nkeynes@352
   907
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   908
        if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
nkeynes@736
   909
            return render_buffers[i];
nkeynes@736
   910
        }
nkeynes@352
   911
    }
nkeynes@352
   912
    return NULL;
nkeynes@352
   913
}
nkeynes@352
   914
nkeynes@352
   915
/**
nkeynes@477
   916
 * Allocate a render buffer with the requested parameters.
nkeynes@477
   917
 * The order of preference is:
nkeynes@352
   918
 *   1. An existing buffer with the same address. (not flushed unless the new
nkeynes@352
   919
 * size is smaller than the old one).
nkeynes@352
   920
 *   2. An existing buffer with the same size chosen by LRU order. Old buffer
nkeynes@352
   921
 *       is flushed to vram.
nkeynes@352
   922
 *   3. A new buffer if one can be created.
nkeynes@352
   923
 *   4. The current display buff
nkeynes@352
   924
 * Note: The current display field(s) will never be overwritten except as a last
nkeynes@352
   925
 * resort.
nkeynes@352
   926
 */
nkeynes@477
   927
render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
nkeynes@352
   928
{
nkeynes@477
   929
    int i;
nkeynes@352
   930
    render_buffer_t result = NULL;
nkeynes@352
   931
nkeynes@352
   932
    /* Check existing buffers for an available buffer */
nkeynes@352
   933
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   934
        if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
nkeynes@736
   935
            /* needs to be the right dimensions */
nkeynes@736
   936
            if( render_buffers[i]->address == render_addr ) {
nkeynes@736
   937
                if( displayed_render_buffer == render_buffers[i] ) {
nkeynes@736
   938
                    /* Same address, but we can't use it because the
nkeynes@736
   939
                     * display has it. Mark it as unaddressed for later.
nkeynes@736
   940
                     */
nkeynes@736
   941
                    render_buffers[i]->address = -1;
nkeynes@736
   942
                } else {
nkeynes@736
   943
                    /* perfect */
nkeynes@736
   944
                    result = render_buffers[i];
nkeynes@736
   945
                    break;
nkeynes@736
   946
                }
nkeynes@736
   947
            } else if( render_buffers[i]->address == -1 && result == NULL && 
nkeynes@736
   948
                    displayed_render_buffer != render_buffers[i] ) {
nkeynes@736
   949
                result = render_buffers[i];
nkeynes@736
   950
            }
nkeynes@736
   951
nkeynes@736
   952
        } else if( render_buffers[i]->address == render_addr ) {
nkeynes@736
   953
            /* right address, wrong size - if it's larger, flush it, otherwise 
nkeynes@736
   954
             * nuke it quietly */
nkeynes@736
   955
            if( render_buffers[i]->width * render_buffers[i]->height >
nkeynes@736
   956
            width*height ) {
nkeynes@736
   957
                pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@736
   958
            }
nkeynes@736
   959
            render_buffers[i]->address = -1;
nkeynes@736
   960
        }
nkeynes@352
   961
    }
nkeynes@352
   962
nkeynes@352
   963
    /* Nothing available - make one */
nkeynes@352
   964
    if( result == NULL ) {
nkeynes@736
   965
        if( render_buffer_count == MAX_RENDER_BUFFERS ) {
nkeynes@736
   966
            /* maximum buffers reached - need to throw one away */
nkeynes@736
   967
            uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
nkeynes@736
   968
            uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
nkeynes@736
   969
            for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
   970
                if( render_buffers[i]->address != field1_addr &&
nkeynes@736
   971
                        render_buffers[i]->address != field2_addr &&
nkeynes@736
   972
                        render_buffers[i] != displayed_render_buffer ) {
nkeynes@736
   973
                    /* Never throw away the current "front buffer(s)" */
nkeynes@736
   974
                    result = render_buffers[i];
nkeynes@871
   975
                    if( !result->flushed && result->address != -1 ) {
nkeynes@736
   976
                        pvr2_render_buffer_copy_to_sh4( result );
nkeynes@736
   977
                    }
nkeynes@736
   978
                    if( result->width != width || result->height != height ) {
nkeynes@736
   979
                        display_driver->destroy_render_buffer(render_buffers[i]);
nkeynes@805
   980
                        result = display_driver->create_render_buffer(width,height,0);
nkeynes@736
   981
                        render_buffers[i] = result;
nkeynes@736
   982
                    }
nkeynes@736
   983
                    break;
nkeynes@736
   984
                }
nkeynes@736
   985
            }
nkeynes@736
   986
        } else {
nkeynes@805
   987
            result = display_driver->create_render_buffer(width,height,0);
nkeynes@736
   988
            if( result != NULL ) { 
nkeynes@736
   989
                render_buffers[render_buffer_count++] = result;
nkeynes@736
   990
            }
nkeynes@736
   991
        }
nkeynes@352
   992
    }
nkeynes@352
   993
nkeynes@477
   994
    if( result != NULL ) {
nkeynes@736
   995
        result->address = render_addr;
nkeynes@477
   996
    }
nkeynes@352
   997
    return result;
nkeynes@352
   998
}
nkeynes@352
   999
nkeynes@352
  1000
/**
nkeynes@477
  1001
 * Allocate a render buffer based on the current rendering settings
nkeynes@477
  1002
 */
nkeynes@477
  1003
render_buffer_t pvr2_next_render_buffer()
nkeynes@477
  1004
{
nkeynes@477
  1005
    render_buffer_t result = NULL;
nkeynes@477
  1006
    uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
nkeynes@477
  1007
    uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
nkeynes@477
  1008
    uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
nkeynes@477
  1009
    uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
nkeynes@477
  1010
nkeynes@856
  1011
    int width = pvr2_scene_buffer_width();
nkeynes@856
  1012
    int height = pvr2_scene_buffer_height();
nkeynes@856
  1013
    int colour_format = render_colour_formats[render_mode&0x07];
nkeynes@856
  1014
nkeynes@477
  1015
    if( render_addr & 0x01000000 ) { /* vram64 */
nkeynes@736
  1016
        render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
nkeynes@477
  1017
    } else { /* vram32 */
nkeynes@736
  1018
        render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
nkeynes@477
  1019
    }
nkeynes@871
  1020
    result = pvr2_alloc_render_buffer( render_addr, width, height );
nkeynes@871
  1021
    
nkeynes@477
  1022
    /* Setup the buffer */
nkeynes@477
  1023
    if( result != NULL ) {
nkeynes@736
  1024
        result->rowstride = render_stride;
nkeynes@736
  1025
        result->colour_format = colour_format;
nkeynes@736
  1026
        result->scale = render_scale;
nkeynes@736
  1027
        result->size = width * height * colour_formats[colour_format].bpp;
nkeynes@736
  1028
        result->flushed = FALSE;
nkeynes@736
  1029
        result->inverted = TRUE; // render buffers are inverted normally
nkeynes@477
  1030
    }
nkeynes@477
  1031
    return result;
nkeynes@477
  1032
}
nkeynes@477
  1033
nkeynes@477
  1034
static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
nkeynes@477
  1035
{
nkeynes@477
  1036
    render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
nkeynes@477
  1037
    if( result != NULL ) {
nkeynes@736
  1038
        int bpp = colour_formats[frame->colour_format].bpp;
nkeynes@736
  1039
        result->rowstride = frame->rowstride;
nkeynes@736
  1040
        result->colour_format = frame->colour_format;
nkeynes@736
  1041
        result->scale = 0x400;
nkeynes@736
  1042
        result->size = frame->width * frame->height * bpp;
nkeynes@736
  1043
        result->flushed = TRUE;
nkeynes@736
  1044
        result->inverted = frame->inverted;
nkeynes@736
  1045
        display_driver->load_frame_buffer( frame, result );
nkeynes@477
  1046
    }
nkeynes@477
  1047
    return result;
nkeynes@477
  1048
}
nkeynes@736
  1049
nkeynes@477
  1050
nkeynes@477
  1051
/**
nkeynes@352
  1052
 * Invalidate any caching on the supplied address. Specifically, if it falls
nkeynes@352
  1053
 * within any of the render buffers, flush the buffer back to PVR2 ram.
nkeynes@352
  1054
 */
nkeynes@352
  1055
gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
nkeynes@352
  1056
{
nkeynes@352
  1057
    int i;
nkeynes@352
  1058
    address = address & 0x1FFFFFFF;
nkeynes@352
  1059
    for( i=0; i<render_buffer_count; i++ ) {
nkeynes@736
  1060
        uint32_t bufaddr = render_buffers[i]->address;
nkeynes@736
  1061
        if( bufaddr != -1 && bufaddr <= address && 
nkeynes@736
  1062
                (bufaddr + render_buffers[i]->size) > address ) {
nkeynes@736
  1063
            if( !render_buffers[i]->flushed ) {
nkeynes@736
  1064
                pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
nkeynes@736
  1065
            }
nkeynes@736
  1066
            if( isWrite ) {
nkeynes@736
  1067
                render_buffers[i]->address = -1; /* Invalid */
nkeynes@736
  1068
            }
nkeynes@736
  1069
            return TRUE; /* should never have overlapping buffers */
nkeynes@736
  1070
        }
nkeynes@352
  1071
    }
nkeynes@352
  1072
    return FALSE;
nkeynes@352
  1073
}
.