lxdream.org :: lxdream/src/sh4/sh4x86.in r974:16b079ed11bb (annotated)

tree revision 974:16b079ed11bb

filename	src/sh4/sh4x86.in
changeset	974:16b079ed11bb
prev	956:4c1ed9e03985
next	975:007bf7eb944f
author	nkeynes
date	Mon Jan 26 03:09:53 2009 +0000 (15 years ago)
permissions	-rw-r--r--
last change	Fix double-counting of instructions in delay slots in sh4_finalize_instruction Fix spc value when taking an exception in mmu_update_icache in a delay slot Fix under-counting of instructions in newpc delay slots in translated blocks

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nkeynes@359	1	/**
nkeynes@586	2	* $Id$
nkeynes@359	3	*
nkeynes@359	4	* SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359	5	* outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359	6	* to test the optimizing versions against.
nkeynes@359	7	*
nkeynes@359	8	* Copyright (c) 2007 Nathan Keynes.
nkeynes@359	9	*
nkeynes@359	10	* This program is free software; you can redistribute it and/or modify
nkeynes@359	11	* it under the terms of the GNU General Public License as published by
nkeynes@359	12	* the Free Software Foundation; either version 2 of the License, or
nkeynes@359	13	* (at your option) any later version.
nkeynes@359	14	*
nkeynes@359	15	* This program is distributed in the hope that it will be useful,
nkeynes@359	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
nkeynes@359	18	* GNU General Public License for more details.
nkeynes@359	19	*/
nkeynes@359	20
nkeynes@368	21	#include <assert.h>
nkeynes@388	22	#include <math.h>
nkeynes@368	23
nkeynes@380	24	#ifndef NDEBUG
nkeynes@380	25	#define DEBUG_JUMPS 1
nkeynes@380	26	#endif
nkeynes@380	27
nkeynes@905	28	#include "lxdream.h"
nkeynes@417	29	#include "sh4/xltcache.h"
nkeynes@368	30	#include "sh4/sh4core.h"
nkeynes@368	31	#include "sh4/sh4trans.h"
nkeynes@671	32	#include "sh4/sh4stat.h"
nkeynes@388	33	#include "sh4/sh4mmio.h"
nkeynes@368	34	#include "sh4/x86op.h"
nkeynes@953	35	#include "sh4/mmu.h"
nkeynes@368	36	#include "clock.h"
nkeynes@368	37
nkeynes@368	38	#define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368	39
nkeynes@586	40	struct backpatch_record {
nkeynes@604	41	uint32_t fixup_offset;
nkeynes@586	42	uint32_t fixup_icount;
nkeynes@596	43	int32_t exc_code;
nkeynes@586	44	};
nkeynes@586	45
nkeynes@590	46	#define DELAY_NONE 0
nkeynes@590	47	#define DELAY_PC 1
nkeynes@590	48	#define DELAY_PC_PR 2
nkeynes@590	49
nkeynes@368	50	/**
nkeynes@368	51	* Struct to manage internal translation state. This state is not saved -
nkeynes@368	52	* it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368	53	* sh4_translate_end_block()
nkeynes@368	54	*/
nkeynes@368	55	struct sh4_x86_state {
nkeynes@590	56	int in_delay_slot;
nkeynes@368	57	gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409	58	gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@901	59	gboolean double_prec; /* true if FPU is in double-precision mode */
nkeynes@903	60	gboolean double_size; /* true if FPU is in double-size mode */
nkeynes@903	61	gboolean sse3_enabled; /* true if host supports SSE3 instructions */
nkeynes@408	62	uint32_t block_start_pc;
nkeynes@547	63	uint32_t stack_posn; /* Trace stack height for alignment purposes */
nkeynes@417	64	int tstate;
nkeynes@368	65
nkeynes@586	66	/* mode flags */
nkeynes@586	67	gboolean tlb_on; /* True if tlb translation is active */
nkeynes@586	68
nkeynes@368	69	/* Allocated memory for the (block-wide) back-patch list */
nkeynes@586	70	struct backpatch_record *backpatch_list;
nkeynes@368	71	uint32_t backpatch_posn;
nkeynes@368	72	uint32_t backpatch_size;
nkeynes@368	73	};
nkeynes@368	74
nkeynes@417	75	#define TSTATE_NONE -1
nkeynes@417	76	#define TSTATE_O 0
nkeynes@417	77	#define TSTATE_C 2
nkeynes@417	78	#define TSTATE_E 4
nkeynes@417	79	#define TSTATE_NE 5
nkeynes@417	80	#define TSTATE_G 0xF
nkeynes@417	81	#define TSTATE_GE 0xD
nkeynes@417	82	#define TSTATE_A 7
nkeynes@417	83	#define TSTATE_AE 3
nkeynes@417	84
nkeynes@671	85	#ifdef ENABLE_SH4STATS
nkeynes@671	86	#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@671	87	#else
nkeynes@671	88	#define COUNT_INST(id)
nkeynes@671	89	#endif
nkeynes@671	90
nkeynes@417	91	/** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@669	92	#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417	93	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@669	94	OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
nkeynes@669	95
nkeynes@417	96	/** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@669	97	#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@417	98	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@669	99	OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
nkeynes@417	100
nkeynes@368	101	static struct sh4_x86_state sh4_x86;
nkeynes@368	102
nkeynes@388	103	static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388	104	static uint32_t min_int = 0x80000000;
nkeynes@394	105	static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394	106	static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386	107
nkeynes@903	108	gboolean is_sse3_supported()
nkeynes@903	109	{
nkeynes@903	110	uint32_t features;
nkeynes@903	111
nkeynes@903	112	__asm__ __volatile__(
nkeynes@903	113	"mov $0x01, %%eax\n\t"
nkeynes@908	114	"cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
nkeynes@903	115	return (features & 1) ? TRUE : FALSE;
nkeynes@903	116	}
nkeynes@903	117
nkeynes@669	118	void sh4_translate_init(void)
nkeynes@368	119	{
nkeynes@368	120	sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@586	121	sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@903	122	sh4_x86.sse3_enabled = is_sse3_supported();
nkeynes@368	123	}
nkeynes@368	124
nkeynes@368	125
nkeynes@586	126	static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368	127	{
nkeynes@368	128	if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368	129	sh4_x86.backpatch_size <<= 1;
nkeynes@586	130	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,
nkeynes@586	131	sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368	132	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368	133	}
nkeynes@586	134	if( sh4_x86.in_delay_slot ) {
nkeynes@586	135	fixup_pc -= 2;
nkeynes@586	136	}
nkeynes@604	137	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =
nkeynes@604	138	((uint8_t )fixup_addr) - ((uint8_t )xlat_current_block->code);
nkeynes@586	139	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@586	140	sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@586	141	sh4_x86.backpatch_posn++;
nkeynes@368	142	}
nkeynes@368	143
nkeynes@359	144	/**
nkeynes@359	145	* Emit an instruction to load an SH4 reg into a real register
nkeynes@359	146	*/
nkeynes@359	147	static inline void load_reg( int x86reg, int sh4reg )
nkeynes@359	148	{
nkeynes@359	149	/* mov [bp+n], reg */
nkeynes@361	150	OP(0x8B);
nkeynes@361	151	OP(0x45 + (x86reg<<3));
nkeynes@359	152	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	153	}
nkeynes@359	154
nkeynes@374	155	static inline void load_reg16s( int x86reg, int sh4reg )
nkeynes@368	156	{
nkeynes@374	157	OP(0x0F);
nkeynes@374	158	OP(0xBF);
nkeynes@374	159	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@368	160	}
nkeynes@368	161
nkeynes@374	162	static inline void load_reg16u( int x86reg, int sh4reg )
nkeynes@368	163	{
nkeynes@374	164	OP(0x0F);
nkeynes@374	165	OP(0xB7);
nkeynes@374	166	MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
nkeynes@374	167
nkeynes@368	168	}
nkeynes@368	169
nkeynes@380	170	#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
nkeynes@380	171	#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
nkeynes@359	172	/**
nkeynes@359	173	* Emit an instruction to load an immediate value into a register
nkeynes@359	174	*/
nkeynes@359	175	static inline void load_imm32( int x86reg, uint32_t value ) {
nkeynes@359	176	/* mov #value, reg */
nkeynes@359	177	OP(0xB8 + x86reg);
nkeynes@359	178	OP32(value);
nkeynes@359	179	}
nkeynes@359	180
nkeynes@953	181
nkeynes@359	182	/**
nkeynes@527	183	* Load an immediate 64-bit quantity (note: x86-64 only)
nkeynes@527	184	*/
nkeynes@800	185	static inline void load_imm64( int x86reg, uint64_t value ) {
nkeynes@527	186	/* mov #value, reg */
nkeynes@527	187	REXW();
nkeynes@527	188	OP(0xB8 + x86reg);
nkeynes@527	189	OP64(value);
nkeynes@527	190	}
nkeynes@527	191
nkeynes@527	192	/**
nkeynes@359	193	* Emit an instruction to store an SH4 reg (RN)
nkeynes@359	194	*/
nkeynes@359	195	void static inline store_reg( int x86reg, int sh4reg ) {
nkeynes@359	196	/* mov reg, [bp+n] */
nkeynes@361	197	OP(0x89);
nkeynes@361	198	OP(0x45 + (x86reg<<3));
nkeynes@359	199	OP(REG_OFFSET(r[sh4reg]));
nkeynes@359	200	}
nkeynes@374	201
nkeynes@375	202	/**
nkeynes@375	203	* Load an FR register (single-precision floating point) into an integer x86
nkeynes@375	204	* register (eg for register-to-register moves)
nkeynes@375	205	*/
nkeynes@669	206	#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@669	207	#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375	208
nkeynes@375	209	/**
nkeynes@669	210	* Load the low half of a DR register (DR or XD) into an integer x86 register
nkeynes@669	211	*/
nkeynes@669	212	#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm\|0x01]) )
nkeynes@669	213	#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@669	214
nkeynes@669	215	/**
nkeynes@669	216	* Store an FR register (single-precision floating point) from an integer x86+
nkeynes@375	217	* register (eg for register-to-register moves)
nkeynes@375	218	*/
nkeynes@669	219	#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@669	220	#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375	221
nkeynes@669	222	#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm\|0x01]) )
nkeynes@669	223	#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@375	224
nkeynes@374	225
nkeynes@669	226	#define push_fpul() FLDF_sh4r(R_FPUL)
nkeynes@669	227	#define pop_fpul() FSTPF_sh4r(R_FPUL)
nkeynes@669	228	#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@669	229	#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@669	230	#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@669	231	#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@669	232	#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@669	233	#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@669	234	#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@669	235	#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377	236
nkeynes@377	237
nkeynes@374	238
nkeynes@368	239	/* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416	240
nkeynes@416	241	#define check_priv( ) \
nkeynes@953	242	if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
nkeynes@953	243	if( sh4_x86.in_delay_slot ) { \
nkeynes@956	244	exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
nkeynes@953	245	} else { \
nkeynes@956	246	exit_block_exc(EXC_ILLEGAL, pc); \
nkeynes@953	247	} \
nkeynes@956	248	sh4_x86.branch_taken = TRUE; \
nkeynes@953	249	sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@953	250	return 2; \
nkeynes@953	251	}
nkeynes@416	252
nkeynes@416	253	#define check_fpuen( ) \
nkeynes@416	254	if( !sh4_x86.fpuen_checked ) {\
nkeynes@416	255	sh4_x86.fpuen_checked = TRUE;\
nkeynes@416	256	load_spreg( R_EAX, R_SR );\
nkeynes@416	257	AND_imm32_r32( SR_FD, R_EAX );\
nkeynes@416	258	if( sh4_x86.in_delay_slot ) {\
nkeynes@586	259	JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416	260	} else {\
nkeynes@586	261	JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416	262	}\
nkeynes@875	263	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416	264	}
nkeynes@416	265
nkeynes@586	266	#define check_ralign16( x86reg ) \
nkeynes@586	267	TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586	268	JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416	269
nkeynes@586	270	#define check_walign16( x86reg ) \
nkeynes@586	271	TEST_imm32_r32( 0x00000001, x86reg ); \
nkeynes@586	272	JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368	273
nkeynes@586	274	#define check_ralign32( x86reg ) \
nkeynes@586	275	TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586	276	JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368	277
nkeynes@586	278	#define check_walign32( x86reg ) \
nkeynes@586	279	TEST_imm32_r32( 0x00000003, x86reg ); \
nkeynes@586	280	JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368	281
nkeynes@732	282	#define check_ralign64( x86reg ) \
nkeynes@732	283	TEST_imm32_r32( 0x00000007, x86reg ); \
nkeynes@732	284	JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732	285
nkeynes@732	286	#define check_walign64( x86reg ) \
nkeynes@732	287	TEST_imm32_r32( 0x00000007, x86reg ); \
nkeynes@732	288	JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732	289
nkeynes@824	290	#define UNDEF(ir)
nkeynes@953	291	#define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@361	292	#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
nkeynes@953	293	/* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so
nkeynes@953	294	* don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@953	295	*/
nkeynes@953	296
nkeynes@953	297	#ifdef HAVE_FRAME_ADDRESS
nkeynes@953	298	#define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
nkeynes@953	299	call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
nkeynes@953	300	call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }
nkeynes@953	301	#define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
nkeynes@953	302	call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
nkeynes@953	303	call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
nkeynes@953	304	#else
nkeynes@953	305	#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)
nkeynes@953	306	#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
nkeynes@953	307	#endif
nkeynes@953	308
nkeynes@953	309	#define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
nkeynes@953	310	#define MEM_READ_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_word); MEM_RESULT(value_reg)
nkeynes@953	311	#define MEM_READ_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_long); MEM_RESULT(value_reg)
nkeynes@953	312	#define MEM_WRITE_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_byte)
nkeynes@953	313	#define MEM_WRITE_WORD( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_word)
nkeynes@953	314	#define MEM_WRITE_LONG( addr_reg, value_reg ) decode_address(addr_reg); _CALL_WRITE(addr_reg, value_reg, write_long)
nkeynes@953	315	#define MEM_PREFETCH( addr_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, prefetch)
nkeynes@361	316
nkeynes@956	317	#define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388	318
nkeynes@539	319	/**** Import appropriate calling conventions ****/
nkeynes@675	320	#if SIZEOF_VOID_P == 8
nkeynes@539	321	#include "sh4/ia64abi.h"
nkeynes@675	322	#else /* 32-bit system */
nkeynes@539	323	#include "sh4/ia32abi.h"
nkeynes@539	324	#endif
nkeynes@539	325
nkeynes@901	326	void sh4_translate_begin_block( sh4addr_t pc )
nkeynes@901	327	{
nkeynes@927	328	enter_block();
nkeynes@901	329	sh4_x86.in_delay_slot = FALSE;
nkeynes@901	330	sh4_x86.fpuen_checked = FALSE;
nkeynes@901	331	sh4_x86.branch_taken = FALSE;
nkeynes@901	332	sh4_x86.backpatch_posn = 0;
nkeynes@901	333	sh4_x86.block_start_pc = pc;
nkeynes@953	334	sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901	335	sh4_x86.tstate = TSTATE_NONE;
nkeynes@901	336	sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903	337	sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901	338	}
nkeynes@901	339
nkeynes@901	340
nkeynes@593	341	uint32_t sh4_translate_end_block_size()
nkeynes@593	342	{
nkeynes@596	343	if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901	344	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596	345	} else {
nkeynes@901	346	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596	347	}
nkeynes@593	348	}
nkeynes@593	349
nkeynes@593	350
nkeynes@590	351	/**
nkeynes@590	352	* Embed a breakpoint into the generated code
nkeynes@590	353	*/
nkeynes@586	354	void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586	355	{
nkeynes@591	356	load_imm32( R_EAX, pc );
nkeynes@591	357	call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875	358	sh4_x86.tstate = TSTATE_NONE;
nkeynes@586	359	}
nkeynes@590	360
nkeynes@601	361
nkeynes@601	362	#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601	363
nkeynes@590	364	/**
nkeynes@590	365	* Embed a call to sh4_execute_instruction for situations that we
nkeynes@601	366	* can't translate (just page-crossing delay slots at the moment).
nkeynes@601	367	* Caller is responsible for setting new_pc before calling this function.
nkeynes@601	368	*
nkeynes@601	369	* Performs:
nkeynes@601	370	* Set PC = endpc
nkeynes@601	371	* Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601	372	* Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601	373	* Call sh4_execute_instruction
nkeynes@601	374	* Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590	375	*/
nkeynes@601	376	void exit_block_emu( sh4vma_t endpc )
nkeynes@590	377	{
nkeynes@590	378	load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5
nkeynes@590	379	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586	380
nkeynes@601	381	load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590	382	ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6
nkeynes@590	383	load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590	384	store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590	385
nkeynes@590	386	call_func0( sh4_execute_instruction );
nkeynes@601	387	load_spreg( R_EAX, R_PC );
nkeynes@590	388	if( sh4_x86.tlb_on ) {
nkeynes@590	389	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590	390	} else {
nkeynes@590	391	call_func1(xlat_get_code,R_EAX);
nkeynes@590	392	}
nkeynes@926	393	exit_block();
nkeynes@590	394	}
nkeynes@539	395
nkeynes@359	396	/**
nkeynes@359	397	* Translate a single instruction. Delayed branches are handled specially
nkeynes@359	398	* by translating both branch and delayed instruction as a single unit (as
nkeynes@359	399	*
nkeynes@586	400	* The instruction MUST be in the icache (assert check)
nkeynes@359	401	*
nkeynes@359	402	* @return true if the instruction marks the end of a basic block
nkeynes@359	403	* (eg a branch or
nkeynes@359	404	*/
nkeynes@590	405	uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359	406	{
nkeynes@388	407	uint32_t ir;
nkeynes@586	408	/* Read instruction from icache */
nkeynes@586	409	assert( IS_IN_ICACHE(pc) );
nkeynes@586	410	ir = (uint16_t )GET_ICACHE_PTR(pc);
nkeynes@586	411
nkeynes@586	412	if( !sh4_x86.in_delay_slot ) {
nkeynes@596	413	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388	414	}
nkeynes@359	415	%%
nkeynes@359	416	/* ALU operations */
nkeynes@359	417	ADD Rm, Rn {:
nkeynes@671	418	COUNT_INST(I_ADD);
nkeynes@359	419	load_reg( R_EAX, Rm );
nkeynes@359	420	load_reg( R_ECX, Rn );
nkeynes@359	421	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	422	store_reg( R_ECX, Rn );
nkeynes@417	423	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	424	:}
nkeynes@359	425	ADD #imm, Rn {:
nkeynes@671	426	COUNT_INST(I_ADDI);
nkeynes@953	427	ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );
nkeynes@417	428	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	429	:}
nkeynes@359	430	ADDC Rm, Rn {:
nkeynes@671	431	COUNT_INST(I_ADDC);
nkeynes@417	432	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911	433	LDC_t();
nkeynes@417	434	}
nkeynes@359	435	load_reg( R_EAX, Rm );
nkeynes@359	436	load_reg( R_ECX, Rn );
nkeynes@359	437	ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359	438	store_reg( R_ECX, Rn );
nkeynes@359	439	SETC_t();
nkeynes@417	440	sh4_x86.tstate = TSTATE_C;
nkeynes@359	441	:}
nkeynes@359	442	ADDV Rm, Rn {:
nkeynes@671	443	COUNT_INST(I_ADDV);
nkeynes@359	444	load_reg( R_EAX, Rm );
nkeynes@359	445	load_reg( R_ECX, Rn );
nkeynes@359	446	ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359	447	store_reg( R_ECX, Rn );
nkeynes@359	448	SETO_t();
nkeynes@417	449	sh4_x86.tstate = TSTATE_O;
nkeynes@359	450	:}
nkeynes@359	451	AND Rm, Rn {:
nkeynes@671	452	COUNT_INST(I_AND);
nkeynes@359	453	load_reg( R_EAX, Rm );
nkeynes@359	454	load_reg( R_ECX, Rn );
nkeynes@359	455	AND_r32_r32( R_EAX, R_ECX );
nkeynes@359	456	store_reg( R_ECX, Rn );
nkeynes@417	457	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	458	:}
nkeynes@359	459	AND #imm, R0 {:
nkeynes@671	460	COUNT_INST(I_ANDI);
nkeynes@359	461	load_reg( R_EAX, 0 );
nkeynes@359	462	AND_imm32_r32(imm, R_EAX);
nkeynes@359	463	store_reg( R_EAX, 0 );
nkeynes@417	464	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	465	:}
nkeynes@359	466	AND.B #imm, @(R0, GBR) {:
nkeynes@671	467	COUNT_INST(I_ANDB);
nkeynes@359	468	load_reg( R_EAX, 0 );
nkeynes@953	469	ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@926	470	MOV_r32_esp8(R_EAX, 0);
nkeynes@905	471	MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926	472	MOV_esp8_r32(0, R_EAX);
nkeynes@905	473	AND_imm32_r32(imm, R_EDX );
nkeynes@905	474	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	475	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	476	:}
nkeynes@359	477	CMP/EQ Rm, Rn {:
nkeynes@671	478	COUNT_INST(I_CMPEQ);
nkeynes@359	479	load_reg( R_EAX, Rm );
nkeynes@359	480	load_reg( R_ECX, Rn );
nkeynes@359	481	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	482	SETE_t();
nkeynes@417	483	sh4_x86.tstate = TSTATE_E;
nkeynes@359	484	:}
nkeynes@359	485	CMP/EQ #imm, R0 {:
nkeynes@671	486	COUNT_INST(I_CMPEQI);
nkeynes@359	487	load_reg( R_EAX, 0 );
nkeynes@359	488	CMP_imm8s_r32(imm, R_EAX);
nkeynes@359	489	SETE_t();
nkeynes@417	490	sh4_x86.tstate = TSTATE_E;
nkeynes@359	491	:}
nkeynes@359	492	CMP/GE Rm, Rn {:
nkeynes@671	493	COUNT_INST(I_CMPGE);
nkeynes@359	494	load_reg( R_EAX, Rm );
nkeynes@359	495	load_reg( R_ECX, Rn );
nkeynes@359	496	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	497	SETGE_t();
nkeynes@417	498	sh4_x86.tstate = TSTATE_GE;
nkeynes@359	499	:}
nkeynes@359	500	CMP/GT Rm, Rn {:
nkeynes@671	501	COUNT_INST(I_CMPGT);
nkeynes@359	502	load_reg( R_EAX, Rm );
nkeynes@359	503	load_reg( R_ECX, Rn );
nkeynes@359	504	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	505	SETG_t();
nkeynes@417	506	sh4_x86.tstate = TSTATE_G;
nkeynes@359	507	:}
nkeynes@359	508	CMP/HI Rm, Rn {:
nkeynes@671	509	COUNT_INST(I_CMPHI);
nkeynes@359	510	load_reg( R_EAX, Rm );
nkeynes@359	511	load_reg( R_ECX, Rn );
nkeynes@359	512	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	513	SETA_t();
nkeynes@417	514	sh4_x86.tstate = TSTATE_A;
nkeynes@359	515	:}
nkeynes@359	516	CMP/HS Rm, Rn {:
nkeynes@671	517	COUNT_INST(I_CMPHS);
nkeynes@359	518	load_reg( R_EAX, Rm );
nkeynes@359	519	load_reg( R_ECX, Rn );
nkeynes@359	520	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359	521	SETAE_t();
nkeynes@417	522	sh4_x86.tstate = TSTATE_AE;
nkeynes@359	523	:}
nkeynes@359	524	CMP/PL Rn {:
nkeynes@671	525	COUNT_INST(I_CMPPL);
nkeynes@359	526	load_reg( R_EAX, Rn );
nkeynes@359	527	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	528	SETG_t();
nkeynes@417	529	sh4_x86.tstate = TSTATE_G;
nkeynes@359	530	:}
nkeynes@359	531	CMP/PZ Rn {:
nkeynes@671	532	COUNT_INST(I_CMPPZ);
nkeynes@359	533	load_reg( R_EAX, Rn );
nkeynes@359	534	CMP_imm8s_r32( 0, R_EAX );
nkeynes@359	535	SETGE_t();
nkeynes@417	536	sh4_x86.tstate = TSTATE_GE;
nkeynes@359	537	:}
nkeynes@361	538	CMP/STR Rm, Rn {:
nkeynes@671	539	COUNT_INST(I_CMPSTR);
nkeynes@368	540	load_reg( R_EAX, Rm );
nkeynes@368	541	load_reg( R_ECX, Rn );
nkeynes@368	542	XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368	543	TEST_r8_r8( R_AL, R_AL );
nkeynes@669	544	JE_rel8(target1);
nkeynes@669	545	TEST_r8_r8( R_AH, R_AH );
nkeynes@669	546	JE_rel8(target2);
nkeynes@669	547	SHR_imm8_r32( 16, R_EAX );
nkeynes@669	548	TEST_r8_r8( R_AL, R_AL );
nkeynes@669	549	JE_rel8(target3);
nkeynes@669	550	TEST_r8_r8( R_AH, R_AH );
nkeynes@380	551	JMP_TARGET(target1);
nkeynes@380	552	JMP_TARGET(target2);
nkeynes@380	553	JMP_TARGET(target3);
nkeynes@368	554	SETE_t();
nkeynes@417	555	sh4_x86.tstate = TSTATE_E;
nkeynes@361	556	:}
nkeynes@361	557	DIV0S Rm, Rn {:
nkeynes@671	558	COUNT_INST(I_DIV0S);
nkeynes@361	559	load_reg( R_EAX, Rm );
nkeynes@386	560	load_reg( R_ECX, Rn );
nkeynes@361	561	SHR_imm8_r32( 31, R_EAX );
nkeynes@361	562	SHR_imm8_r32( 31, R_ECX );
nkeynes@361	563	store_spreg( R_EAX, R_M );
nkeynes@361	564	store_spreg( R_ECX, R_Q );
nkeynes@361	565	CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386	566	SETNE_t();
nkeynes@417	567	sh4_x86.tstate = TSTATE_NE;
nkeynes@361	568	:}
nkeynes@361	569	DIV0U {:
nkeynes@671	570	COUNT_INST(I_DIV0U);
nkeynes@361	571	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361	572	store_spreg( R_EAX, R_Q );
nkeynes@361	573	store_spreg( R_EAX, R_M );
nkeynes@361	574	store_spreg( R_EAX, R_T );
nkeynes@417	575	sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361	576	:}
nkeynes@386	577	DIV1 Rm, Rn {:
nkeynes@671	578	COUNT_INST(I_DIV1);
nkeynes@386	579	load_spreg( R_ECX, R_M );
nkeynes@386	580	load_reg( R_EAX, Rn );
nkeynes@417	581	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	582	LDC_t();
nkeynes@417	583	}
nkeynes@386	584	RCL1_r32( R_EAX );
nkeynes@386	585	SETC_r8( R_DL ); // Q'
nkeynes@386	586	CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669	587	JE_rel8(mqequal);
nkeynes@386	588	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669	589	JMP_rel8(end);
nkeynes@380	590	JMP_TARGET(mqequal);
nkeynes@386	591	SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386	592	JMP_TARGET(end);
nkeynes@386	593	store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386	594	SETC_r8(R_AL); // tmp1
nkeynes@386	595	XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386	596	XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386	597	store_spreg( R_ECX, R_Q );
nkeynes@386	598	XOR_imm8s_r32( 1, R_AL ); // T = !Q'
nkeynes@386	599	MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386	600	store_spreg( R_EAX, R_T );
nkeynes@417	601	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	602	:}
nkeynes@361	603	DMULS.L Rm, Rn {:
nkeynes@671	604	COUNT_INST(I_DMULS);
nkeynes@361	605	load_reg( R_EAX, Rm );
nkeynes@361	606	load_reg( R_ECX, Rn );
nkeynes@361	607	IMUL_r32(R_ECX);
nkeynes@361	608	store_spreg( R_EDX, R_MACH );
nkeynes@361	609	store_spreg( R_EAX, R_MACL );
nkeynes@417	610	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	611	:}
nkeynes@361	612	DMULU.L Rm, Rn {:
nkeynes@671	613	COUNT_INST(I_DMULU);
nkeynes@361	614	load_reg( R_EAX, Rm );
nkeynes@361	615	load_reg( R_ECX, Rn );
nkeynes@361	616	MUL_r32(R_ECX);
nkeynes@361	617	store_spreg( R_EDX, R_MACH );
nkeynes@361	618	store_spreg( R_EAX, R_MACL );
nkeynes@417	619	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	620	:}
nkeynes@359	621	DT Rn {:
nkeynes@671	622	COUNT_INST(I_DT);
nkeynes@359	623	load_reg( R_EAX, Rn );
nkeynes@382	624	ADD_imm8s_r32( -1, R_EAX );
nkeynes@359	625	store_reg( R_EAX, Rn );
nkeynes@359	626	SETE_t();
nkeynes@417	627	sh4_x86.tstate = TSTATE_E;
nkeynes@359	628	:}
nkeynes@359	629	EXTS.B Rm, Rn {:
nkeynes@671	630	COUNT_INST(I_EXTSB);
nkeynes@359	631	load_reg( R_EAX, Rm );
nkeynes@359	632	MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359	633	store_reg( R_EAX, Rn );
nkeynes@359	634	:}
nkeynes@361	635	EXTS.W Rm, Rn {:
nkeynes@671	636	COUNT_INST(I_EXTSW);
nkeynes@361	637	load_reg( R_EAX, Rm );
nkeynes@361	638	MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361	639	store_reg( R_EAX, Rn );
nkeynes@361	640	:}
nkeynes@361	641	EXTU.B Rm, Rn {:
nkeynes@671	642	COUNT_INST(I_EXTUB);
nkeynes@361	643	load_reg( R_EAX, Rm );
nkeynes@361	644	MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361	645	store_reg( R_EAX, Rn );
nkeynes@361	646	:}
nkeynes@361	647	EXTU.W Rm, Rn {:
nkeynes@671	648	COUNT_INST(I_EXTUW);
nkeynes@361	649	load_reg( R_EAX, Rm );
nkeynes@361	650	MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361	651	store_reg( R_EAX, Rn );
nkeynes@361	652	:}
nkeynes@586	653	MAC.L @Rm+, @Rn+ {:
nkeynes@671	654	COUNT_INST(I_MACL);
nkeynes@586	655	if( Rm == Rn ) {
nkeynes@586	656	load_reg( R_EAX, Rm );
nkeynes@586	657	check_ralign32( R_EAX );
nkeynes@953	658	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926	659	MOV_r32_esp8(R_EAX, 0);
nkeynes@953	660	load_reg( R_EAX, Rm );
nkeynes@953	661	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	662	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	663	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586	664	} else {
nkeynes@586	665	load_reg( R_EAX, Rm );
nkeynes@586	666	check_ralign32( R_EAX );
nkeynes@953	667	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926	668	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926	669	load_reg( R_EAX, Rn );
nkeynes@926	670	check_ralign32( R_EAX );
nkeynes@953	671	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	672	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586	673	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586	674	}
nkeynes@953	675
nkeynes@953	676	IMUL_esp8( 0 );
nkeynes@386	677	ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386	678	ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386	679
nkeynes@386	680	load_spreg( R_ECX, R_S );
nkeynes@386	681	TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669	682	JE_rel8( nosat );
nkeynes@386	683	call_func0( signsat48 );
nkeynes@386	684	JMP_TARGET( nosat );
nkeynes@417	685	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386	686	:}
nkeynes@386	687	MAC.W @Rm+, @Rn+ {:
nkeynes@671	688	COUNT_INST(I_MACW);
nkeynes@586	689	if( Rm == Rn ) {
nkeynes@586	690	load_reg( R_EAX, Rm );
nkeynes@586	691	check_ralign16( R_EAX );
nkeynes@953	692	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926	693	MOV_r32_esp8( R_EAX, 0 );
nkeynes@953	694	load_reg( R_EAX, Rm );
nkeynes@953	695	LEA_r32disp8_r32( R_EAX, 2, R_EAX );
nkeynes@953	696	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586	697	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586	698	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586	699	// adding a page-boundary check to skip the second translation
nkeynes@586	700	} else {
nkeynes@586	701	load_reg( R_EAX, Rm );
nkeynes@586	702	check_ralign16( R_EAX );
nkeynes@953	703	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926	704	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926	705	load_reg( R_EAX, Rn );
nkeynes@926	706	check_ralign16( R_EAX );
nkeynes@953	707	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586	708	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586	709	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586	710	}
nkeynes@953	711	IMUL_esp8( 0 );
nkeynes@386	712	load_spreg( R_ECX, R_S );
nkeynes@386	713	TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669	714	JE_rel8( nosat );
nkeynes@386	715
nkeynes@386	716	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@669	717	JNO_rel8( end ); // 2
nkeynes@386	718	load_imm32( R_EDX, 1 ); // 5
nkeynes@386	719	store_spreg( R_EDX, R_MACH ); // 6
nkeynes@669	720	JS_rel8( positive ); // 2
nkeynes@386	721	load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386	722	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@669	723	JMP_rel8(end2); // 2
nkeynes@386	724
nkeynes@386	725	JMP_TARGET(positive);
nkeynes@386	726	load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386	727	store_spreg( R_EAX, R_MACL ); // 6
nkeynes@669	728	JMP_rel8(end3); // 2
nkeynes@386	729
nkeynes@386	730	JMP_TARGET(nosat);
nkeynes@386	731	ADD_r32_sh4r( R_EAX, R_MACL ); // 6
nkeynes@386	732	ADC_r32_sh4r( R_EDX, R_MACH ); // 6
nkeynes@386	733	JMP_TARGET(end);
nkeynes@386	734	JMP_TARGET(end2);
nkeynes@386	735	JMP_TARGET(end3);
nkeynes@417	736	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386	737	:}
nkeynes@359	738	MOVT Rn {:
nkeynes@671	739	COUNT_INST(I_MOVT);
nkeynes@359	740	load_spreg( R_EAX, R_T );
nkeynes@359	741	store_reg( R_EAX, Rn );
nkeynes@359	742	:}
nkeynes@361	743	MUL.L Rm, Rn {:
nkeynes@671	744	COUNT_INST(I_MULL);
nkeynes@361	745	load_reg( R_EAX, Rm );
nkeynes@361	746	load_reg( R_ECX, Rn );
nkeynes@361	747	MUL_r32( R_ECX );
nkeynes@361	748	store_spreg( R_EAX, R_MACL );
nkeynes@417	749	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	750	:}
nkeynes@374	751	MULS.W Rm, Rn {:
nkeynes@671	752	COUNT_INST(I_MULSW);
nkeynes@374	753	load_reg16s( R_EAX, Rm );
nkeynes@374	754	load_reg16s( R_ECX, Rn );
nkeynes@374	755	MUL_r32( R_ECX );
nkeynes@374	756	store_spreg( R_EAX, R_MACL );
nkeynes@417	757	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	758	:}
nkeynes@374	759	MULU.W Rm, Rn {:
nkeynes@671	760	COUNT_INST(I_MULUW);
nkeynes@374	761	load_reg16u( R_EAX, Rm );
nkeynes@374	762	load_reg16u( R_ECX, Rn );
nkeynes@374	763	MUL_r32( R_ECX );
nkeynes@374	764	store_spreg( R_EAX, R_MACL );
nkeynes@417	765	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	766	:}
nkeynes@359	767	NEG Rm, Rn {:
nkeynes@671	768	COUNT_INST(I_NEG);
nkeynes@359	769	load_reg( R_EAX, Rm );
nkeynes@359	770	NEG_r32( R_EAX );
nkeynes@359	771	store_reg( R_EAX, Rn );
nkeynes@417	772	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	773	:}
nkeynes@359	774	NEGC Rm, Rn {:
nkeynes@671	775	COUNT_INST(I_NEGC);
nkeynes@359	776	load_reg( R_EAX, Rm );
nkeynes@359	777	XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359	778	LDC_t();
nkeynes@359	779	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	780	store_reg( R_ECX, Rn );
nkeynes@359	781	SETC_t();
nkeynes@417	782	sh4_x86.tstate = TSTATE_C;
nkeynes@359	783	:}
nkeynes@359	784	NOT Rm, Rn {:
nkeynes@671	785	COUNT_INST(I_NOT);
nkeynes@359	786	load_reg( R_EAX, Rm );
nkeynes@359	787	NOT_r32( R_EAX );
nkeynes@359	788	store_reg( R_EAX, Rn );
nkeynes@417	789	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	790	:}
nkeynes@359	791	OR Rm, Rn {:
nkeynes@671	792	COUNT_INST(I_OR);
nkeynes@359	793	load_reg( R_EAX, Rm );
nkeynes@359	794	load_reg( R_ECX, Rn );
nkeynes@359	795	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	796	store_reg( R_ECX, Rn );
nkeynes@417	797	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	798	:}
nkeynes@359	799	OR #imm, R0 {:
nkeynes@671	800	COUNT_INST(I_ORI);
nkeynes@359	801	load_reg( R_EAX, 0 );
nkeynes@359	802	OR_imm32_r32(imm, R_EAX);
nkeynes@359	803	store_reg( R_EAX, 0 );
nkeynes@417	804	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	805	:}
nkeynes@374	806	OR.B #imm, @(R0, GBR) {:
nkeynes@671	807	COUNT_INST(I_ORB);
nkeynes@374	808	load_reg( R_EAX, 0 );
nkeynes@953	809	ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@926	810	MOV_r32_esp8( R_EAX, 0 );
nkeynes@905	811	MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926	812	MOV_esp8_r32( 0, R_EAX );
nkeynes@905	813	OR_imm32_r32(imm, R_EDX );
nkeynes@905	814	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	815	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	816	:}
nkeynes@359	817	ROTCL Rn {:
nkeynes@671	818	COUNT_INST(I_ROTCL);
nkeynes@359	819	load_reg( R_EAX, Rn );
nkeynes@417	820	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	821	LDC_t();
nkeynes@417	822	}
nkeynes@359	823	RCL1_r32( R_EAX );
nkeynes@359	824	store_reg( R_EAX, Rn );
nkeynes@359	825	SETC_t();
nkeynes@417	826	sh4_x86.tstate = TSTATE_C;
nkeynes@359	827	:}
nkeynes@359	828	ROTCR Rn {:
nkeynes@671	829	COUNT_INST(I_ROTCR);
nkeynes@359	830	load_reg( R_EAX, Rn );
nkeynes@417	831	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	832	LDC_t();
nkeynes@417	833	}
nkeynes@359	834	RCR1_r32( R_EAX );
nkeynes@359	835	store_reg( R_EAX, Rn );
nkeynes@359	836	SETC_t();
nkeynes@417	837	sh4_x86.tstate = TSTATE_C;
nkeynes@359	838	:}
nkeynes@359	839	ROTL Rn {:
nkeynes@671	840	COUNT_INST(I_ROTL);
nkeynes@359	841	load_reg( R_EAX, Rn );
nkeynes@359	842	ROL1_r32( R_EAX );
nkeynes@359	843	store_reg( R_EAX, Rn );
nkeynes@359	844	SETC_t();
nkeynes@417	845	sh4_x86.tstate = TSTATE_C;
nkeynes@359	846	:}
nkeynes@359	847	ROTR Rn {:
nkeynes@671	848	COUNT_INST(I_ROTR);
nkeynes@359	849	load_reg( R_EAX, Rn );
nkeynes@359	850	ROR1_r32( R_EAX );
nkeynes@359	851	store_reg( R_EAX, Rn );
nkeynes@359	852	SETC_t();
nkeynes@417	853	sh4_x86.tstate = TSTATE_C;
nkeynes@359	854	:}
nkeynes@359	855	SHAD Rm, Rn {:
nkeynes@671	856	COUNT_INST(I_SHAD);
nkeynes@359	857	/* Annoyingly enough, not directly convertible */
nkeynes@361	858	load_reg( R_EAX, Rn );
nkeynes@361	859	load_reg( R_ECX, Rm );
nkeynes@361	860	CMP_imm32_r32( 0, R_ECX );
nkeynes@669	861	JGE_rel8(doshl);
nkeynes@361	862
nkeynes@361	863	NEG_r32( R_ECX ); // 2
nkeynes@361	864	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669	865	JE_rel8(emptysar); // 2
nkeynes@361	866	SAR_r32_CL( R_EAX ); // 2
nkeynes@669	867	JMP_rel8(end); // 2
nkeynes@386	868
nkeynes@386	869	JMP_TARGET(emptysar);
nkeynes@386	870	SAR_imm8_r32(31, R_EAX ); // 3
nkeynes@669	871	JMP_rel8(end2);
nkeynes@382	872
nkeynes@380	873	JMP_TARGET(doshl);
nkeynes@361	874	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361	875	SHL_r32_CL( R_EAX ); // 2
nkeynes@380	876	JMP_TARGET(end);
nkeynes@386	877	JMP_TARGET(end2);
nkeynes@361	878	store_reg( R_EAX, Rn );
nkeynes@417	879	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	880	:}
nkeynes@359	881	SHLD Rm, Rn {:
nkeynes@671	882	COUNT_INST(I_SHLD);
nkeynes@368	883	load_reg( R_EAX, Rn );
nkeynes@368	884	load_reg( R_ECX, Rm );
nkeynes@382	885	CMP_imm32_r32( 0, R_ECX );
nkeynes@669	886	JGE_rel8(doshl);
nkeynes@368	887
nkeynes@382	888	NEG_r32( R_ECX ); // 2
nkeynes@382	889	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669	890	JE_rel8(emptyshr );
nkeynes@382	891	SHR_r32_CL( R_EAX ); // 2
nkeynes@669	892	JMP_rel8(end); // 2
nkeynes@386	893
nkeynes@386	894	JMP_TARGET(emptyshr);
nkeynes@386	895	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669	896	JMP_rel8(end2);
nkeynes@382	897
nkeynes@382	898	JMP_TARGET(doshl);
nkeynes@382	899	AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382	900	SHL_r32_CL( R_EAX ); // 2
nkeynes@382	901	JMP_TARGET(end);
nkeynes@386	902	JMP_TARGET(end2);
nkeynes@368	903	store_reg( R_EAX, Rn );
nkeynes@417	904	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	905	:}
nkeynes@359	906	SHAL Rn {:
nkeynes@671	907	COUNT_INST(I_SHAL);
nkeynes@359	908	load_reg( R_EAX, Rn );
nkeynes@359	909	SHL1_r32( R_EAX );
nkeynes@397	910	SETC_t();
nkeynes@359	911	store_reg( R_EAX, Rn );
nkeynes@417	912	sh4_x86.tstate = TSTATE_C;
nkeynes@359	913	:}
nkeynes@359	914	SHAR Rn {:
nkeynes@671	915	COUNT_INST(I_SHAR);
nkeynes@359	916	load_reg( R_EAX, Rn );
nkeynes@359	917	SAR1_r32( R_EAX );
nkeynes@397	918	SETC_t();
nkeynes@359	919	store_reg( R_EAX, Rn );
nkeynes@417	920	sh4_x86.tstate = TSTATE_C;
nkeynes@359	921	:}
nkeynes@359	922	SHLL Rn {:
nkeynes@671	923	COUNT_INST(I_SHLL);
nkeynes@359	924	load_reg( R_EAX, Rn );
nkeynes@359	925	SHL1_r32( R_EAX );
nkeynes@397	926	SETC_t();
nkeynes@359	927	store_reg( R_EAX, Rn );
nkeynes@417	928	sh4_x86.tstate = TSTATE_C;
nkeynes@359	929	:}
nkeynes@359	930	SHLL2 Rn {:
nkeynes@671	931	COUNT_INST(I_SHLL);
nkeynes@359	932	load_reg( R_EAX, Rn );
nkeynes@359	933	SHL_imm8_r32( 2, R_EAX );
nkeynes@359	934	store_reg( R_EAX, Rn );
nkeynes@417	935	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	936	:}
nkeynes@359	937	SHLL8 Rn {:
nkeynes@671	938	COUNT_INST(I_SHLL);
nkeynes@359	939	load_reg( R_EAX, Rn );
nkeynes@359	940	SHL_imm8_r32( 8, R_EAX );
nkeynes@359	941	store_reg( R_EAX, Rn );
nkeynes@417	942	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	943	:}
nkeynes@359	944	SHLL16 Rn {:
nkeynes@671	945	COUNT_INST(I_SHLL);
nkeynes@359	946	load_reg( R_EAX, Rn );
nkeynes@359	947	SHL_imm8_r32( 16, R_EAX );
nkeynes@359	948	store_reg( R_EAX, Rn );
nkeynes@417	949	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	950	:}
nkeynes@359	951	SHLR Rn {:
nkeynes@671	952	COUNT_INST(I_SHLR);
nkeynes@359	953	load_reg( R_EAX, Rn );
nkeynes@359	954	SHR1_r32( R_EAX );
nkeynes@397	955	SETC_t();
nkeynes@359	956	store_reg( R_EAX, Rn );
nkeynes@417	957	sh4_x86.tstate = TSTATE_C;
nkeynes@359	958	:}
nkeynes@359	959	SHLR2 Rn {:
nkeynes@671	960	COUNT_INST(I_SHLR);
nkeynes@359	961	load_reg( R_EAX, Rn );
nkeynes@359	962	SHR_imm8_r32( 2, R_EAX );
nkeynes@359	963	store_reg( R_EAX, Rn );
nkeynes@417	964	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	965	:}
nkeynes@359	966	SHLR8 Rn {:
nkeynes@671	967	COUNT_INST(I_SHLR);
nkeynes@359	968	load_reg( R_EAX, Rn );
nkeynes@359	969	SHR_imm8_r32( 8, R_EAX );
nkeynes@359	970	store_reg( R_EAX, Rn );
nkeynes@417	971	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	972	:}
nkeynes@359	973	SHLR16 Rn {:
nkeynes@671	974	COUNT_INST(I_SHLR);
nkeynes@359	975	load_reg( R_EAX, Rn );
nkeynes@359	976	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	977	store_reg( R_EAX, Rn );
nkeynes@417	978	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	979	:}
nkeynes@359	980	SUB Rm, Rn {:
nkeynes@671	981	COUNT_INST(I_SUB);
nkeynes@359	982	load_reg( R_EAX, Rm );
nkeynes@359	983	load_reg( R_ECX, Rn );
nkeynes@359	984	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	985	store_reg( R_ECX, Rn );
nkeynes@417	986	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	987	:}
nkeynes@359	988	SUBC Rm, Rn {:
nkeynes@671	989	COUNT_INST(I_SUBC);
nkeynes@359	990	load_reg( R_EAX, Rm );
nkeynes@359	991	load_reg( R_ECX, Rn );
nkeynes@417	992	if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417	993	LDC_t();
nkeynes@417	994	}
nkeynes@359	995	SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359	996	store_reg( R_ECX, Rn );
nkeynes@394	997	SETC_t();
nkeynes@417	998	sh4_x86.tstate = TSTATE_C;
nkeynes@359	999	:}
nkeynes@359	1000	SUBV Rm, Rn {:
nkeynes@671	1001	COUNT_INST(I_SUBV);
nkeynes@359	1002	load_reg( R_EAX, Rm );
nkeynes@359	1003	load_reg( R_ECX, Rn );
nkeynes@359	1004	SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359	1005	store_reg( R_ECX, Rn );
nkeynes@359	1006	SETO_t();
nkeynes@417	1007	sh4_x86.tstate = TSTATE_O;
nkeynes@359	1008	:}
nkeynes@359	1009	SWAP.B Rm, Rn {:
nkeynes@671	1010	COUNT_INST(I_SWAPB);
nkeynes@359	1011	load_reg( R_EAX, Rm );
nkeynes@601	1012	XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359	1013	store_reg( R_EAX, Rn );
nkeynes@359	1014	:}
nkeynes@359	1015	SWAP.W Rm, Rn {:
nkeynes@671	1016	COUNT_INST(I_SWAPB);
nkeynes@359	1017	load_reg( R_EAX, Rm );
nkeynes@359	1018	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359	1019	SHL_imm8_r32( 16, R_ECX );
nkeynes@359	1020	SHR_imm8_r32( 16, R_EAX );
nkeynes@359	1021	OR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1022	store_reg( R_ECX, Rn );
nkeynes@417	1023	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1024	:}
nkeynes@361	1025	TAS.B @Rn {:
nkeynes@671	1026	COUNT_INST(I_TASB);
nkeynes@586	1027	load_reg( R_EAX, Rn );
nkeynes@926	1028	MOV_r32_esp8( R_EAX, 0 );
nkeynes@905	1029	MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905	1030	TEST_r8_r8( R_DL, R_DL );
nkeynes@361	1031	SETE_t();
nkeynes@905	1032	OR_imm8_r8( 0x80, R_DL );
nkeynes@926	1033	MOV_esp8_r32( 0, R_EAX );
nkeynes@905	1034	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1035	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1036	:}
nkeynes@361	1037	TST Rm, Rn {:
nkeynes@671	1038	COUNT_INST(I_TST);
nkeynes@361	1039	load_reg( R_EAX, Rm );
nkeynes@361	1040	load_reg( R_ECX, Rn );
nkeynes@361	1041	TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361	1042	SETE_t();
nkeynes@417	1043	sh4_x86.tstate = TSTATE_E;
nkeynes@361	1044	:}
nkeynes@368	1045	TST #imm, R0 {:
nkeynes@671	1046	COUNT_INST(I_TSTI);
nkeynes@368	1047	load_reg( R_EAX, 0 );
nkeynes@368	1048	TEST_imm32_r32( imm, R_EAX );
nkeynes@368	1049	SETE_t();
nkeynes@417	1050	sh4_x86.tstate = TSTATE_E;
nkeynes@368	1051	:}
nkeynes@368	1052	TST.B #imm, @(R0, GBR) {:
nkeynes@671	1053	COUNT_INST(I_TSTB);
nkeynes@368	1054	load_reg( R_EAX, 0);
nkeynes@953	1055	ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@586	1056	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394	1057	TEST_imm8_r8( imm, R_AL );
nkeynes@368	1058	SETE_t();
nkeynes@417	1059	sh4_x86.tstate = TSTATE_E;
nkeynes@368	1060	:}
nkeynes@359	1061	XOR Rm, Rn {:
nkeynes@671	1062	COUNT_INST(I_XOR);
nkeynes@359	1063	load_reg( R_EAX, Rm );
nkeynes@359	1064	load_reg( R_ECX, Rn );
nkeynes@359	1065	XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359	1066	store_reg( R_ECX, Rn );
nkeynes@417	1067	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1068	:}
nkeynes@359	1069	XOR #imm, R0 {:
nkeynes@671	1070	COUNT_INST(I_XORI);
nkeynes@359	1071	load_reg( R_EAX, 0 );
nkeynes@359	1072	XOR_imm32_r32( imm, R_EAX );
nkeynes@359	1073	store_reg( R_EAX, 0 );
nkeynes@417	1074	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1075	:}
nkeynes@359	1076	XOR.B #imm, @(R0, GBR) {:
nkeynes@671	1077	COUNT_INST(I_XORB);
nkeynes@359	1078	load_reg( R_EAX, 0 );
nkeynes@953	1079	ADD_sh4r_r32( R_GBR, R_EAX );
nkeynes@926	1080	MOV_r32_esp8( R_EAX, 0 );
nkeynes@905	1081	MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@926	1082	MOV_esp8_r32( 0, R_EAX );
nkeynes@905	1083	XOR_imm32_r32( imm, R_EDX );
nkeynes@905	1084	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1085	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1086	:}
nkeynes@361	1087	XTRCT Rm, Rn {:
nkeynes@671	1088	COUNT_INST(I_XTRCT);
nkeynes@361	1089	load_reg( R_EAX, Rm );
nkeynes@394	1090	load_reg( R_ECX, Rn );
nkeynes@394	1091	SHL_imm8_r32( 16, R_EAX );
nkeynes@394	1092	SHR_imm8_r32( 16, R_ECX );
nkeynes@361	1093	OR_r32_r32( R_EAX, R_ECX );
nkeynes@361	1094	store_reg( R_ECX, Rn );
nkeynes@417	1095	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1096	:}
nkeynes@359	1097
nkeynes@359	1098	/* Data move instructions */
nkeynes@359	1099	MOV Rm, Rn {:
nkeynes@671	1100	COUNT_INST(I_MOV);
nkeynes@359	1101	load_reg( R_EAX, Rm );
nkeynes@359	1102	store_reg( R_EAX, Rn );
nkeynes@359	1103	:}
nkeynes@359	1104	MOV #imm, Rn {:
nkeynes@671	1105	COUNT_INST(I_MOVI);
nkeynes@359	1106	load_imm32( R_EAX, imm );
nkeynes@359	1107	store_reg( R_EAX, Rn );
nkeynes@359	1108	:}
nkeynes@359	1109	MOV.B Rm, @Rn {:
nkeynes@671	1110	COUNT_INST(I_MOVB);
nkeynes@586	1111	load_reg( R_EAX, Rn );
nkeynes@586	1112	load_reg( R_EDX, Rm );
nkeynes@586	1113	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1114	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1115	:}
nkeynes@359	1116	MOV.B Rm, @-Rn {:
nkeynes@671	1117	COUNT_INST(I_MOVB);
nkeynes@586	1118	load_reg( R_EAX, Rn );
nkeynes@953	1119	LEA_r32disp8_r32( R_EAX, -1, R_EAX );
nkeynes@586	1120	load_reg( R_EDX, Rm );
nkeynes@953	1121	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@586	1122	ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@417	1123	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1124	:}
nkeynes@359	1125	MOV.B Rm, @(R0, Rn) {:
nkeynes@671	1126	COUNT_INST(I_MOVB);
nkeynes@359	1127	load_reg( R_EAX, 0 );
nkeynes@953	1128	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586	1129	load_reg( R_EDX, Rm );
nkeynes@586	1130	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1131	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1132	:}
nkeynes@359	1133	MOV.B R0, @(disp, GBR) {:
nkeynes@671	1134	COUNT_INST(I_MOVB);
nkeynes@586	1135	load_spreg( R_EAX, R_GBR );
nkeynes@586	1136	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1137	load_reg( R_EDX, 0 );
nkeynes@586	1138	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1139	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1140	:}
nkeynes@359	1141	MOV.B R0, @(disp, Rn) {:
nkeynes@671	1142	COUNT_INST(I_MOVB);
nkeynes@586	1143	load_reg( R_EAX, Rn );
nkeynes@586	1144	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1145	load_reg( R_EDX, 0 );
nkeynes@586	1146	MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417	1147	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1148	:}
nkeynes@359	1149	MOV.B @Rm, Rn {:
nkeynes@671	1150	COUNT_INST(I_MOVB);
nkeynes@586	1151	load_reg( R_EAX, Rm );
nkeynes@586	1152	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386	1153	store_reg( R_EAX, Rn );
nkeynes@417	1154	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1155	:}
nkeynes@359	1156	MOV.B @Rm+, Rn {:
nkeynes@671	1157	COUNT_INST(I_MOVB);
nkeynes@586	1158	load_reg( R_EAX, Rm );
nkeynes@586	1159	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@953	1160	if( Rm != Rn ) {
nkeynes@953	1161	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@953	1162	}
nkeynes@359	1163	store_reg( R_EAX, Rn );
nkeynes@417	1164	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1165	:}
nkeynes@359	1166	MOV.B @(R0, Rm), Rn {:
nkeynes@671	1167	COUNT_INST(I_MOVB);
nkeynes@359	1168	load_reg( R_EAX, 0 );
nkeynes@953	1169	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586	1170	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	1171	store_reg( R_EAX, Rn );
nkeynes@417	1172	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1173	:}
nkeynes@359	1174	MOV.B @(disp, GBR), R0 {:
nkeynes@671	1175	COUNT_INST(I_MOVB);
nkeynes@586	1176	load_spreg( R_EAX, R_GBR );
nkeynes@586	1177	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1178	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	1179	store_reg( R_EAX, 0 );
nkeynes@417	1180	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1181	:}
nkeynes@359	1182	MOV.B @(disp, Rm), R0 {:
nkeynes@671	1183	COUNT_INST(I_MOVB);
nkeynes@586	1184	load_reg( R_EAX, Rm );
nkeynes@586	1185	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1186	MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359	1187	store_reg( R_EAX, 0 );
nkeynes@417	1188	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1189	:}
nkeynes@374	1190	MOV.L Rm, @Rn {:
nkeynes@671	1191	COUNT_INST(I_MOVL);
nkeynes@586	1192	load_reg( R_EAX, Rn );
nkeynes@586	1193	check_walign32(R_EAX);
nkeynes@953	1194	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@953	1195	AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@953	1196	CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@953	1197	JNE_rel8( notsq );
nkeynes@953	1198	AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@953	1199	load_reg( R_EDX, Rm );
nkeynes@953	1200	MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@953	1201	JMP_rel8(end);
nkeynes@953	1202	JMP_TARGET(notsq);
nkeynes@586	1203	load_reg( R_EDX, Rm );
nkeynes@586	1204	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953	1205	JMP_TARGET(end);
nkeynes@417	1206	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1207	:}
nkeynes@361	1208	MOV.L Rm, @-Rn {:
nkeynes@671	1209	COUNT_INST(I_MOVL);
nkeynes@586	1210	load_reg( R_EAX, Rn );
nkeynes@586	1211	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	1212	check_walign32( R_EAX );
nkeynes@586	1213	load_reg( R_EDX, Rm );
nkeynes@953	1214	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	1215	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	1216	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1217	:}
nkeynes@361	1218	MOV.L Rm, @(R0, Rn) {:
nkeynes@671	1219	COUNT_INST(I_MOVL);
nkeynes@361	1220	load_reg( R_EAX, 0 );
nkeynes@953	1221	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586	1222	check_walign32( R_EAX );
nkeynes@586	1223	load_reg( R_EDX, Rm );
nkeynes@586	1224	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1225	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1226	:}
nkeynes@361	1227	MOV.L R0, @(disp, GBR) {:
nkeynes@671	1228	COUNT_INST(I_MOVL);
nkeynes@586	1229	load_spreg( R_EAX, R_GBR );
nkeynes@586	1230	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1231	check_walign32( R_EAX );
nkeynes@586	1232	load_reg( R_EDX, 0 );
nkeynes@586	1233	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1234	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1235	:}
nkeynes@361	1236	MOV.L Rm, @(disp, Rn) {:
nkeynes@671	1237	COUNT_INST(I_MOVL);
nkeynes@586	1238	load_reg( R_EAX, Rn );
nkeynes@586	1239	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1240	check_walign32( R_EAX );
nkeynes@953	1241	MOV_r32_r32( R_EAX, R_ECX );
nkeynes@953	1242	AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@953	1243	CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@953	1244	JNE_rel8( notsq );
nkeynes@953	1245	AND_imm8s_r32( 0x3C, R_EAX );
nkeynes@953	1246	load_reg( R_EDX, Rm );
nkeynes@953	1247	MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
nkeynes@953	1248	JMP_rel8(end);
nkeynes@953	1249	JMP_TARGET(notsq);
nkeynes@586	1250	load_reg( R_EDX, Rm );
nkeynes@586	1251	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953	1252	JMP_TARGET(end);
nkeynes@417	1253	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1254	:}
nkeynes@361	1255	MOV.L @Rm, Rn {:
nkeynes@671	1256	COUNT_INST(I_MOVL);
nkeynes@586	1257	load_reg( R_EAX, Rm );
nkeynes@586	1258	check_ralign32( R_EAX );
nkeynes@586	1259	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	1260	store_reg( R_EAX, Rn );
nkeynes@417	1261	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1262	:}
nkeynes@361	1263	MOV.L @Rm+, Rn {:
nkeynes@671	1264	COUNT_INST(I_MOVL);
nkeynes@361	1265	load_reg( R_EAX, Rm );
nkeynes@382	1266	check_ralign32( R_EAX );
nkeynes@586	1267	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1268	if( Rm != Rn ) {
nkeynes@953	1269	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@953	1270	}
nkeynes@361	1271	store_reg( R_EAX, Rn );
nkeynes@417	1272	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1273	:}
nkeynes@361	1274	MOV.L @(R0, Rm), Rn {:
nkeynes@671	1275	COUNT_INST(I_MOVL);
nkeynes@361	1276	load_reg( R_EAX, 0 );
nkeynes@953	1277	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586	1278	check_ralign32( R_EAX );
nkeynes@586	1279	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	1280	store_reg( R_EAX, Rn );
nkeynes@417	1281	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1282	:}
nkeynes@361	1283	MOV.L @(disp, GBR), R0 {:
nkeynes@671	1284	COUNT_INST(I_MOVL);
nkeynes@586	1285	load_spreg( R_EAX, R_GBR );
nkeynes@586	1286	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1287	check_ralign32( R_EAX );
nkeynes@586	1288	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	1289	store_reg( R_EAX, 0 );
nkeynes@417	1290	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1291	:}
nkeynes@361	1292	MOV.L @(disp, PC), Rn {:
nkeynes@671	1293	COUNT_INST(I_MOVLPC);
nkeynes@374	1294	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1295	SLOTILLEGAL();
nkeynes@374	1296	} else {
nkeynes@388	1297	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586	1298	if( IS_IN_ICACHE(target) ) {
nkeynes@586	1299	// If the target address is in the same page as the code, it's
nkeynes@586	1300	// pretty safe to just ref it directly and circumvent the whole
nkeynes@586	1301	// memory subsystem. (this is a big performance win)
nkeynes@586	1302
nkeynes@586	1303	// FIXME: There's a corner-case that's not handled here when
nkeynes@586	1304	// the current code-page is in the ITLB but not in the UTLB.
nkeynes@586	1305	// (should generate a TLB miss although need to test SH4
nkeynes@586	1306	// behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586	1307	// behaviour though.
nkeynes@586	1308	sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527	1309	MOV_moff32_EAX( ptr );
nkeynes@388	1310	} else {
nkeynes@586	1311	// Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586	1312	// different virtual address than the translation was done with,
nkeynes@586	1313	// but we can safely assume that the low bits are the same.
nkeynes@586	1314	load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586	1315	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586	1316	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	1317	sh4_x86.tstate = TSTATE_NONE;
nkeynes@388	1318	}
nkeynes@382	1319	store_reg( R_EAX, Rn );
nkeynes@374	1320	}
nkeynes@361	1321	:}
nkeynes@361	1322	MOV.L @(disp, Rm), Rn {:
nkeynes@671	1323	COUNT_INST(I_MOVL);
nkeynes@586	1324	load_reg( R_EAX, Rm );
nkeynes@586	1325	ADD_imm8s_r32( disp, R_EAX );
nkeynes@586	1326	check_ralign32( R_EAX );
nkeynes@586	1327	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361	1328	store_reg( R_EAX, Rn );
nkeynes@417	1329	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1330	:}
nkeynes@361	1331	MOV.W Rm, @Rn {:
nkeynes@671	1332	COUNT_INST(I_MOVW);
nkeynes@586	1333	load_reg( R_EAX, Rn );
nkeynes@586	1334	check_walign16( R_EAX );
nkeynes@586	1335	load_reg( R_EDX, Rm );
nkeynes@586	1336	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	1337	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1338	:}
nkeynes@361	1339	MOV.W Rm, @-Rn {:
nkeynes@671	1340	COUNT_INST(I_MOVW);
nkeynes@586	1341	load_reg( R_EAX, Rn );
nkeynes@586	1342	check_walign16( R_EAX );
nkeynes@953	1343	LEA_r32disp8_r32( R_EAX, -2, R_EAX );
nkeynes@586	1344	load_reg( R_EDX, Rm );
nkeynes@953	1345	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@586	1346	ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@417	1347	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1348	:}
nkeynes@361	1349	MOV.W Rm, @(R0, Rn) {:
nkeynes@671	1350	COUNT_INST(I_MOVW);
nkeynes@361	1351	load_reg( R_EAX, 0 );
nkeynes@953	1352	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@586	1353	check_walign16( R_EAX );
nkeynes@586	1354	load_reg( R_EDX, Rm );
nkeynes@586	1355	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	1356	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1357	:}
nkeynes@361	1358	MOV.W R0, @(disp, GBR) {:
nkeynes@671	1359	COUNT_INST(I_MOVW);
nkeynes@586	1360	load_spreg( R_EAX, R_GBR );
nkeynes@586	1361	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1362	check_walign16( R_EAX );
nkeynes@586	1363	load_reg( R_EDX, 0 );
nkeynes@586	1364	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	1365	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1366	:}
nkeynes@361	1367	MOV.W R0, @(disp, Rn) {:
nkeynes@671	1368	COUNT_INST(I_MOVW);
nkeynes@586	1369	load_reg( R_EAX, Rn );
nkeynes@586	1370	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1371	check_walign16( R_EAX );
nkeynes@586	1372	load_reg( R_EDX, 0 );
nkeynes@586	1373	MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417	1374	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1375	:}
nkeynes@361	1376	MOV.W @Rm, Rn {:
nkeynes@671	1377	COUNT_INST(I_MOVW);
nkeynes@586	1378	load_reg( R_EAX, Rm );
nkeynes@586	1379	check_ralign16( R_EAX );
nkeynes@586	1380	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	1381	store_reg( R_EAX, Rn );
nkeynes@417	1382	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1383	:}
nkeynes@361	1384	MOV.W @Rm+, Rn {:
nkeynes@671	1385	COUNT_INST(I_MOVW);
nkeynes@361	1386	load_reg( R_EAX, Rm );
nkeynes@374	1387	check_ralign16( R_EAX );
nkeynes@586	1388	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@953	1389	if( Rm != Rn ) {
nkeynes@953	1390	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@953	1391	}
nkeynes@361	1392	store_reg( R_EAX, Rn );
nkeynes@417	1393	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1394	:}
nkeynes@361	1395	MOV.W @(R0, Rm), Rn {:
nkeynes@671	1396	COUNT_INST(I_MOVW);
nkeynes@361	1397	load_reg( R_EAX, 0 );
nkeynes@953	1398	ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@586	1399	check_ralign16( R_EAX );
nkeynes@586	1400	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	1401	store_reg( R_EAX, Rn );
nkeynes@417	1402	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1403	:}
nkeynes@361	1404	MOV.W @(disp, GBR), R0 {:
nkeynes@671	1405	COUNT_INST(I_MOVW);
nkeynes@586	1406	load_spreg( R_EAX, R_GBR );
nkeynes@586	1407	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1408	check_ralign16( R_EAX );
nkeynes@586	1409	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	1410	store_reg( R_EAX, 0 );
nkeynes@417	1411	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1412	:}
nkeynes@361	1413	MOV.W @(disp, PC), Rn {:
nkeynes@671	1414	COUNT_INST(I_MOVW);
nkeynes@374	1415	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1416	SLOTILLEGAL();
nkeynes@374	1417	} else {
nkeynes@586	1418	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586	1419	uint32_t target = pc + disp + 4;
nkeynes@586	1420	if( IS_IN_ICACHE(target) ) {
nkeynes@586	1421	sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586	1422	MOV_moff32_EAX( ptr );
nkeynes@586	1423	MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586	1424	} else {
nkeynes@586	1425	load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586	1426	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586	1427	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586	1428	sh4_x86.tstate = TSTATE_NONE;
nkeynes@586	1429	}
nkeynes@374	1430	store_reg( R_EAX, Rn );
nkeynes@374	1431	}
nkeynes@361	1432	:}
nkeynes@361	1433	MOV.W @(disp, Rm), R0 {:
nkeynes@671	1434	COUNT_INST(I_MOVW);
nkeynes@586	1435	load_reg( R_EAX, Rm );
nkeynes@586	1436	ADD_imm32_r32( disp, R_EAX );
nkeynes@586	1437	check_ralign16( R_EAX );
nkeynes@586	1438	MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361	1439	store_reg( R_EAX, 0 );
nkeynes@417	1440	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1441	:}
nkeynes@361	1442	MOVA @(disp, PC), R0 {:
nkeynes@671	1443	COUNT_INST(I_MOVA);
nkeynes@374	1444	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1445	SLOTILLEGAL();
nkeynes@374	1446	} else {
nkeynes@586	1447	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586	1448	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374	1449	store_reg( R_ECX, 0 );
nkeynes@586	1450	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	1451	}
nkeynes@361	1452	:}
nkeynes@361	1453	MOVCA.L R0, @Rn {:
nkeynes@671	1454	COUNT_INST(I_MOVCA);
nkeynes@586	1455	load_reg( R_EAX, Rn );
nkeynes@586	1456	check_walign32( R_EAX );
nkeynes@586	1457	load_reg( R_EDX, 0 );
nkeynes@586	1458	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417	1459	sh4_x86.tstate = TSTATE_NONE;
nkeynes@361	1460	:}
nkeynes@359	1461
nkeynes@359	1462	/* Control transfer instructions */
nkeynes@374	1463	BF disp {:
nkeynes@671	1464	COUNT_INST(I_BF);
nkeynes@374	1465	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1466	SLOTILLEGAL();
nkeynes@374	1467	} else {
nkeynes@586	1468	sh4vma_t target = disp + pc + 4;
nkeynes@669	1469	JT_rel8( nottaken );
nkeynes@586	1470	exit_block_rel(target, pc+2 );
nkeynes@380	1471	JMP_TARGET(nottaken);
nkeynes@408	1472	return 2;
nkeynes@374	1473	}
nkeynes@374	1474	:}
nkeynes@374	1475	BF/S disp {:
nkeynes@671	1476	COUNT_INST(I_BFS);
nkeynes@374	1477	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1478	SLOTILLEGAL();
nkeynes@374	1479	} else {
nkeynes@590	1480	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601	1481	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1482	load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669	1483	JT_rel8(nottaken);
nkeynes@601	1484	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	1485	JMP_TARGET(nottaken);
nkeynes@601	1486	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601	1487	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	1488	exit_block_emu(pc+2);
nkeynes@601	1489	sh4_x86.branch_taken = TRUE;
nkeynes@601	1490	return 2;
nkeynes@601	1491	} else {
nkeynes@601	1492	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601	1493	CMP_imm8s_sh4r( 1, R_T );
nkeynes@601	1494	sh4_x86.tstate = TSTATE_E;
nkeynes@601	1495	}
nkeynes@601	1496	sh4vma_t target = disp + pc + 4;
nkeynes@601	1497	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t patch = (uint32_t )xlat_output; OP32(0); // JT rel32
nkeynes@879	1498	int save_tstate = sh4_x86.tstate;
nkeynes@601	1499	sh4_translate_instruction(pc+2);
nkeynes@601	1500	exit_block_rel( target, pc+4 );
nkeynes@601	1501
nkeynes@601	1502	// not taken
nkeynes@601	1503	patch = (xlat_output - ((uint8_t )patch)) - 4;
nkeynes@879	1504	sh4_x86.tstate = save_tstate;
nkeynes@601	1505	sh4_translate_instruction(pc+2);
nkeynes@601	1506	return 4;
nkeynes@417	1507	}
nkeynes@374	1508	}
nkeynes@374	1509	:}
nkeynes@374	1510	BRA disp {:
nkeynes@671	1511	COUNT_INST(I_BRA);
nkeynes@374	1512	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1513	SLOTILLEGAL();
nkeynes@374	1514	} else {
nkeynes@590	1515	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1516	sh4_x86.branch_taken = TRUE;
nkeynes@601	1517	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1518	load_spreg( R_EAX, R_PC );
nkeynes@601	1519	ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601	1520	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	1521	exit_block_emu(pc+2);
nkeynes@601	1522	return 2;
nkeynes@601	1523	} else {
nkeynes@601	1524	sh4_translate_instruction( pc + 2 );
nkeynes@601	1525	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	1526	return 4;
nkeynes@601	1527	}
nkeynes@374	1528	}
nkeynes@374	1529	:}
nkeynes@374	1530	BRAF Rn {:
nkeynes@671	1531	COUNT_INST(I_BRAF);
nkeynes@374	1532	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1533	SLOTILLEGAL();
nkeynes@374	1534	} else {
nkeynes@590	1535	load_spreg( R_EAX, R_PC );
nkeynes@590	1536	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590	1537	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590	1538	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590	1539	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417	1540	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	1541	sh4_x86.branch_taken = TRUE;
nkeynes@601	1542	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1543	exit_block_emu(pc+2);
nkeynes@601	1544	return 2;
nkeynes@601	1545	} else {
nkeynes@601	1546	sh4_translate_instruction( pc + 2 );
nkeynes@974	1547	exit_block_newpcset(pc+4);
nkeynes@601	1548	return 4;
nkeynes@601	1549	}
nkeynes@374	1550	}
nkeynes@374	1551	:}
nkeynes@374	1552	BSR disp {:
nkeynes@671	1553	COUNT_INST(I_BSR);
nkeynes@374	1554	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1555	SLOTILLEGAL();
nkeynes@374	1556	} else {
nkeynes@590	1557	load_spreg( R_EAX, R_PC );
nkeynes@590	1558	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374	1559	store_spreg( R_EAX, R_PR );
nkeynes@590	1560	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1561	sh4_x86.branch_taken = TRUE;
nkeynes@601	1562	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601	1563	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1564	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	1565	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	1566	exit_block_emu(pc+2);
nkeynes@601	1567	return 2;
nkeynes@601	1568	} else {
nkeynes@601	1569	sh4_translate_instruction( pc + 2 );
nkeynes@601	1570	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	1571	return 4;
nkeynes@601	1572	}
nkeynes@374	1573	}
nkeynes@374	1574	:}
nkeynes@374	1575	BSRF Rn {:
nkeynes@671	1576	COUNT_INST(I_BSRF);
nkeynes@374	1577	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1578	SLOTILLEGAL();
nkeynes@374	1579	} else {
nkeynes@590	1580	load_spreg( R_EAX, R_PC );
nkeynes@590	1581	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590	1582	store_spreg( R_EAX, R_PR );
nkeynes@590	1583	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590	1584	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590	1585
nkeynes@601	1586	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417	1587	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	1588	sh4_x86.branch_taken = TRUE;
nkeynes@601	1589	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1590	exit_block_emu(pc+2);
nkeynes@601	1591	return 2;
nkeynes@601	1592	} else {
nkeynes@601	1593	sh4_translate_instruction( pc + 2 );
nkeynes@974	1594	exit_block_newpcset(pc+4);
nkeynes@601	1595	return 4;
nkeynes@601	1596	}
nkeynes@374	1597	}
nkeynes@374	1598	:}
nkeynes@374	1599	BT disp {:
nkeynes@671	1600	COUNT_INST(I_BT);
nkeynes@374	1601	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1602	SLOTILLEGAL();
nkeynes@374	1603	} else {
nkeynes@586	1604	sh4vma_t target = disp + pc + 4;
nkeynes@669	1605	JF_rel8( nottaken );
nkeynes@586	1606	exit_block_rel(target, pc+2 );
nkeynes@380	1607	JMP_TARGET(nottaken);
nkeynes@408	1608	return 2;
nkeynes@374	1609	}
nkeynes@374	1610	:}
nkeynes@374	1611	BT/S disp {:
nkeynes@671	1612	COUNT_INST(I_BTS);
nkeynes@374	1613	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1614	SLOTILLEGAL();
nkeynes@374	1615	} else {
nkeynes@590	1616	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601	1617	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1618	load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669	1619	JF_rel8(nottaken);
nkeynes@601	1620	ADD_imm32_r32( disp, R_EAX );
nkeynes@601	1621	JMP_TARGET(nottaken);
nkeynes@601	1622	ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601	1623	store_spreg( R_EAX, R_NEW_PC );
nkeynes@601	1624	exit_block_emu(pc+2);
nkeynes@601	1625	sh4_x86.branch_taken = TRUE;
nkeynes@601	1626	return 2;
nkeynes@601	1627	} else {
nkeynes@601	1628	if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601	1629	CMP_imm8s_sh4r( 1, R_T );
nkeynes@601	1630	sh4_x86.tstate = TSTATE_E;
nkeynes@601	1631	}
nkeynes@601	1632	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t patch = (uint32_t )xlat_output; OP32(0); // JF rel32
nkeynes@879	1633	int save_tstate = sh4_x86.tstate;
nkeynes@601	1634	sh4_translate_instruction(pc+2);
nkeynes@601	1635	exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601	1636	// not taken
nkeynes@601	1637	patch = (xlat_output - ((uint8_t )patch)) - 4;
nkeynes@879	1638	sh4_x86.tstate = save_tstate;
nkeynes@601	1639	sh4_translate_instruction(pc+2);
nkeynes@601	1640	return 4;
nkeynes@417	1641	}
nkeynes@374	1642	}
nkeynes@374	1643	:}
nkeynes@374	1644	JMP @Rn {:
nkeynes@671	1645	COUNT_INST(I_JMP);
nkeynes@374	1646	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1647	SLOTILLEGAL();
nkeynes@374	1648	} else {
nkeynes@408	1649	load_reg( R_ECX, Rn );
nkeynes@590	1650	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590	1651	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1652	sh4_x86.branch_taken = TRUE;
nkeynes@601	1653	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1654	exit_block_emu(pc+2);
nkeynes@601	1655	return 2;
nkeynes@601	1656	} else {
nkeynes@601	1657	sh4_translate_instruction(pc+2);
nkeynes@974	1658	exit_block_newpcset(pc+4);
nkeynes@601	1659	return 4;
nkeynes@601	1660	}
nkeynes@374	1661	}
nkeynes@374	1662	:}
nkeynes@374	1663	JSR @Rn {:
nkeynes@671	1664	COUNT_INST(I_JSR);
nkeynes@374	1665	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1666	SLOTILLEGAL();
nkeynes@374	1667	} else {
nkeynes@590	1668	load_spreg( R_EAX, R_PC );
nkeynes@590	1669	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374	1670	store_spreg( R_EAX, R_PR );
nkeynes@408	1671	load_reg( R_ECX, Rn );
nkeynes@590	1672	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601	1673	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1674	sh4_x86.branch_taken = TRUE;
nkeynes@601	1675	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601	1676	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1677	exit_block_emu(pc+2);
nkeynes@601	1678	return 2;
nkeynes@601	1679	} else {
nkeynes@601	1680	sh4_translate_instruction(pc+2);
nkeynes@974	1681	exit_block_newpcset(pc+4);
nkeynes@601	1682	return 4;
nkeynes@601	1683	}
nkeynes@374	1684	}
nkeynes@374	1685	:}
nkeynes@374	1686	RTE {:
nkeynes@671	1687	COUNT_INST(I_RTE);
nkeynes@374	1688	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1689	SLOTILLEGAL();
nkeynes@374	1690	} else {
nkeynes@408	1691	check_priv();
nkeynes@408	1692	load_spreg( R_ECX, R_SPC );
nkeynes@590	1693	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374	1694	load_spreg( R_EAX, R_SSR );
nkeynes@374	1695	call_func1( sh4_write_sr, R_EAX );
nkeynes@590	1696	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377	1697	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	1698	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409	1699	sh4_x86.branch_taken = TRUE;
nkeynes@601	1700	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1701	exit_block_emu(pc+2);
nkeynes@601	1702	return 2;
nkeynes@601	1703	} else {
nkeynes@601	1704	sh4_translate_instruction(pc+2);
nkeynes@974	1705	exit_block_newpcset(pc+4);
nkeynes@601	1706	return 4;
nkeynes@601	1707	}
nkeynes@374	1708	}
nkeynes@374	1709	:}
nkeynes@374	1710	RTS {:
nkeynes@671	1711	COUNT_INST(I_RTS);
nkeynes@374	1712	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1713	SLOTILLEGAL();
nkeynes@374	1714	} else {
nkeynes@408	1715	load_spreg( R_ECX, R_PR );
nkeynes@590	1716	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590	1717	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409	1718	sh4_x86.branch_taken = TRUE;
nkeynes@601	1719	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601	1720	exit_block_emu(pc+2);
nkeynes@601	1721	return 2;
nkeynes@601	1722	} else {
nkeynes@601	1723	sh4_translate_instruction(pc+2);
nkeynes@974	1724	exit_block_newpcset(pc+4);
nkeynes@601	1725	return 4;
nkeynes@601	1726	}
nkeynes@374	1727	}
nkeynes@374	1728	:}
nkeynes@374	1729	TRAPA #imm {:
nkeynes@671	1730	COUNT_INST(I_TRAPA);
nkeynes@374	1731	if( sh4_x86.in_delay_slot ) {
nkeynes@374	1732	SLOTILLEGAL();
nkeynes@374	1733	} else {
nkeynes@590	1734	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5
nkeynes@590	1735	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527	1736	load_imm32( R_EAX, imm );
nkeynes@527	1737	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417	1738	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974	1739	exit_block_pcset(pc+2);
nkeynes@409	1740	sh4_x86.branch_taken = TRUE;
nkeynes@408	1741	return 2;
nkeynes@374	1742	}
nkeynes@374	1743	:}
nkeynes@374	1744	UNDEF {:
nkeynes@671	1745	COUNT_INST(I_UNDEF);
nkeynes@374	1746	if( sh4_x86.in_delay_slot ) {
nkeynes@956	1747	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);
nkeynes@374	1748	} else {
nkeynes@956	1749	exit_block_exc(EXC_ILLEGAL, pc);
nkeynes@408	1750	return 2;
nkeynes@374	1751	}
nkeynes@368	1752	:}
nkeynes@374	1753
nkeynes@374	1754	CLRMAC {:
nkeynes@671	1755	COUNT_INST(I_CLRMAC);
nkeynes@374	1756	XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374	1757	store_spreg( R_EAX, R_MACL );
nkeynes@374	1758	store_spreg( R_EAX, R_MACH );
nkeynes@417	1759	sh4_x86.tstate = TSTATE_NONE;
nkeynes@368	1760	:}
nkeynes@374	1761	CLRS {:
nkeynes@671	1762	COUNT_INST(I_CLRS);
nkeynes@374	1763	CLC();
nkeynes@374	1764	SETC_sh4r(R_S);
nkeynes@872	1765	sh4_x86.tstate = TSTATE_NONE;
nkeynes@368	1766	:}
nkeynes@374	1767	CLRT {:
nkeynes@671	1768	COUNT_INST(I_CLRT);
nkeynes@374	1769	CLC();
nkeynes@374	1770	SETC_t();
nkeynes@417	1771	sh4_x86.tstate = TSTATE_C;
nkeynes@359	1772	:}
nkeynes@374	1773	SETS {:
nkeynes@671	1774	COUNT_INST(I_SETS);
nkeynes@374	1775	STC();
nkeynes@374	1776	SETC_sh4r(R_S);
nkeynes@872	1777	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	1778	:}
nkeynes@374	1779	SETT {:
nkeynes@671	1780	COUNT_INST(I_SETT);
nkeynes@374	1781	STC();
nkeynes@374	1782	SETC_t();
nkeynes@417	1783	sh4_x86.tstate = TSTATE_C;
nkeynes@374	1784	:}
nkeynes@359	1785
nkeynes@375	1786	/* Floating point moves */
nkeynes@375	1787	FMOV FRm, FRn {:
nkeynes@671	1788	COUNT_INST(I_FMOV1);
nkeynes@377	1789	check_fpuen();
nkeynes@901	1790	if( sh4_x86.double_size ) {
nkeynes@901	1791	load_dr0( R_EAX, FRm );
nkeynes@901	1792	load_dr1( R_ECX, FRm );
nkeynes@901	1793	store_dr0( R_EAX, FRn );
nkeynes@901	1794	store_dr1( R_ECX, FRn );
nkeynes@901	1795	} else {
nkeynes@901	1796	load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901	1797	store_fr( R_EAX, FRn );
nkeynes@901	1798	}
nkeynes@375	1799	:}
nkeynes@416	1800	FMOV FRm, @Rn {:
nkeynes@671	1801	COUNT_INST(I_FMOV2);
nkeynes@586	1802	check_fpuen();
nkeynes@586	1803	load_reg( R_EAX, Rn );
nkeynes@901	1804	if( sh4_x86.double_size ) {
nkeynes@901	1805	check_walign64( R_EAX );
nkeynes@905	1806	load_dr0( R_EDX, FRm );
nkeynes@953	1807	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953	1808	load_reg( R_EAX, Rn );
nkeynes@953	1809	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	1810	load_dr1( R_EDX, FRm );
nkeynes@953	1811	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901	1812	} else {
nkeynes@901	1813	check_walign32( R_EAX );
nkeynes@905	1814	load_fr( R_EDX, FRm );
nkeynes@905	1815	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901	1816	}
nkeynes@417	1817	sh4_x86.tstate = TSTATE_NONE;
nkeynes@375	1818	:}
nkeynes@375	1819	FMOV @Rm, FRn {:
nkeynes@671	1820	COUNT_INST(I_FMOV5);
nkeynes@586	1821	check_fpuen();
nkeynes@586	1822	load_reg( R_EAX, Rm );
nkeynes@901	1823	if( sh4_x86.double_size ) {
nkeynes@901	1824	check_ralign64( R_EAX );
nkeynes@953	1825	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1826	store_dr0( R_EAX, FRn );
nkeynes@953	1827	load_reg( R_EAX, Rm );
nkeynes@953	1828	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	1829	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1830	store_dr1( R_EAX, FRn );
nkeynes@901	1831	} else {
nkeynes@901	1832	check_ralign32( R_EAX );
nkeynes@901	1833	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901	1834	store_fr( R_EAX, FRn );
nkeynes@901	1835	}
nkeynes@417	1836	sh4_x86.tstate = TSTATE_NONE;
nkeynes@375	1837	:}
nkeynes@377	1838	FMOV FRm, @-Rn {:
nkeynes@671	1839	COUNT_INST(I_FMOV3);
nkeynes@586	1840	check_fpuen();
nkeynes@586	1841	load_reg( R_EAX, Rn );
nkeynes@901	1842	if( sh4_x86.double_size ) {
nkeynes@901	1843	check_walign64( R_EAX );
nkeynes@953	1844	LEA_r32disp8_r32( R_EAX, -8, R_EAX );
nkeynes@905	1845	load_dr0( R_EDX, FRm );
nkeynes@953	1846	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953	1847	load_reg( R_EAX, Rn );
nkeynes@953	1848	LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@953	1849	load_dr1( R_EDX, FRm );
nkeynes@953	1850	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901	1851	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@901	1852	} else {
nkeynes@901	1853	check_walign32( R_EAX );
nkeynes@953	1854	LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@905	1855	load_fr( R_EDX, FRm );
nkeynes@953	1856	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901	1857	ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@901	1858	}
nkeynes@417	1859	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1860	:}
nkeynes@416	1861	FMOV @Rm+, FRn {:
nkeynes@671	1862	COUNT_INST(I_FMOV6);
nkeynes@586	1863	check_fpuen();
nkeynes@586	1864	load_reg( R_EAX, Rm );
nkeynes@901	1865	if( sh4_x86.double_size ) {
nkeynes@901	1866	check_ralign64( R_EAX );
nkeynes@953	1867	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1868	store_dr0( R_EAX, FRn );
nkeynes@953	1869	load_reg( R_EAX, Rm );
nkeynes@953	1870	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	1871	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1872	store_dr1( R_EAX, FRn );
nkeynes@901	1873	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@901	1874	} else {
nkeynes@901	1875	check_ralign32( R_EAX );
nkeynes@901	1876	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901	1877	store_fr( R_EAX, FRn );
nkeynes@953	1878	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901	1879	}
nkeynes@417	1880	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1881	:}
nkeynes@377	1882	FMOV FRm, @(R0, Rn) {:
nkeynes@671	1883	COUNT_INST(I_FMOV4);
nkeynes@586	1884	check_fpuen();
nkeynes@586	1885	load_reg( R_EAX, Rn );
nkeynes@586	1886	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901	1887	if( sh4_x86.double_size ) {
nkeynes@901	1888	check_walign64( R_EAX );
nkeynes@905	1889	load_dr0( R_EDX, FRm );
nkeynes@953	1890	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@953	1891	load_reg( R_EAX, Rn );
nkeynes@953	1892	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@953	1893	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	1894	load_dr1( R_EDX, FRm );
nkeynes@953	1895	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901	1896	} else {
nkeynes@901	1897	check_walign32( R_EAX );
nkeynes@905	1898	load_fr( R_EDX, FRm );
nkeynes@905	1899	MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901	1900	}
nkeynes@417	1901	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1902	:}
nkeynes@377	1903	FMOV @(R0, Rm), FRn {:
nkeynes@671	1904	COUNT_INST(I_FMOV7);
nkeynes@586	1905	check_fpuen();
nkeynes@586	1906	load_reg( R_EAX, Rm );
nkeynes@586	1907	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901	1908	if( sh4_x86.double_size ) {
nkeynes@901	1909	check_ralign64( R_EAX );
nkeynes@953	1910	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@953	1911	store_dr0( R_EAX, FRn );
nkeynes@953	1912	load_reg( R_EAX, Rm );
nkeynes@953	1913	ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@953	1914	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
nkeynes@953	1915	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901	1916	store_dr1( R_EAX, FRn );
nkeynes@901	1917	} else {
nkeynes@901	1918	check_ralign32( R_EAX );
nkeynes@901	1919	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901	1920	store_fr( R_EAX, FRn );
nkeynes@901	1921	}
nkeynes@417	1922	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1923	:}
nkeynes@377	1924	FLDI0 FRn {: /* IFF PR=0 */
nkeynes@671	1925	COUNT_INST(I_FLDI0);
nkeynes@377	1926	check_fpuen();
nkeynes@901	1927	if( sh4_x86.double_prec == 0 ) {
nkeynes@901	1928	XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901	1929	store_fr( R_EAX, FRn );
nkeynes@901	1930	}
nkeynes@417	1931	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1932	:}
nkeynes@377	1933	FLDI1 FRn {: /* IFF PR=0 */
nkeynes@671	1934	COUNT_INST(I_FLDI1);
nkeynes@377	1935	check_fpuen();
nkeynes@901	1936	if( sh4_x86.double_prec == 0 ) {
nkeynes@901	1937	load_imm32(R_EAX, 0x3F800000);
nkeynes@901	1938	store_fr( R_EAX, FRn );
nkeynes@901	1939	}
nkeynes@377	1940	:}
nkeynes@377	1941
nkeynes@377	1942	FLOAT FPUL, FRn {:
nkeynes@671	1943	COUNT_INST(I_FLOAT);
nkeynes@377	1944	check_fpuen();
nkeynes@377	1945	FILD_sh4r(R_FPUL);
nkeynes@901	1946	if( sh4_x86.double_prec ) {
nkeynes@901	1947	pop_dr( FRn );
nkeynes@901	1948	} else {
nkeynes@901	1949	pop_fr( FRn );
nkeynes@901	1950	}
nkeynes@377	1951	:}
nkeynes@377	1952	FTRC FRm, FPUL {:
nkeynes@671	1953	COUNT_INST(I_FTRC);
nkeynes@377	1954	check_fpuen();
nkeynes@901	1955	if( sh4_x86.double_prec ) {
nkeynes@901	1956	push_dr( FRm );
nkeynes@901	1957	} else {
nkeynes@901	1958	push_fr( FRm );
nkeynes@901	1959	}
nkeynes@789	1960	load_ptr( R_ECX, &max_int );
nkeynes@388	1961	FILD_r32ind( R_ECX );
nkeynes@388	1962	FCOMIP_st(1);
nkeynes@669	1963	JNA_rel8( sat );
nkeynes@789	1964	load_ptr( R_ECX, &min_int ); // 5
nkeynes@388	1965	FILD_r32ind( R_ECX ); // 2
nkeynes@388	1966	FCOMIP_st(1); // 2
nkeynes@669	1967	JAE_rel8( sat2 ); // 2
nkeynes@789	1968	load_ptr( R_EAX, &save_fcw );
nkeynes@394	1969	FNSTCW_r32ind( R_EAX );
nkeynes@789	1970	load_ptr( R_EDX, &trunc_fcw );
nkeynes@394	1971	FLDCW_r32ind( R_EDX );
nkeynes@388	1972	FISTP_sh4r(R_FPUL); // 3
nkeynes@394	1973	FLDCW_r32ind( R_EAX );
nkeynes@669	1974	JMP_rel8(end); // 2
nkeynes@388	1975
nkeynes@388	1976	JMP_TARGET(sat);
nkeynes@388	1977	JMP_TARGET(sat2);
nkeynes@388	1978	MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388	1979	store_spreg( R_ECX, R_FPUL );
nkeynes@388	1980	FPOP_st();
nkeynes@388	1981	JMP_TARGET(end);
nkeynes@417	1982	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	1983	:}
nkeynes@377	1984	FLDS FRm, FPUL {:
nkeynes@671	1985	COUNT_INST(I_FLDS);
nkeynes@377	1986	check_fpuen();
nkeynes@669	1987	load_fr( R_EAX, FRm );
nkeynes@377	1988	store_spreg( R_EAX, R_FPUL );
nkeynes@377	1989	:}
nkeynes@377	1990	FSTS FPUL, FRn {:
nkeynes@671	1991	COUNT_INST(I_FSTS);
nkeynes@377	1992	check_fpuen();
nkeynes@377	1993	load_spreg( R_EAX, R_FPUL );
nkeynes@669	1994	store_fr( R_EAX, FRn );
nkeynes@377	1995	:}
nkeynes@377	1996	FCNVDS FRm, FPUL {:
nkeynes@671	1997	COUNT_INST(I_FCNVDS);
nkeynes@377	1998	check_fpuen();
nkeynes@901	1999	if( sh4_x86.double_prec ) {
nkeynes@901	2000	push_dr( FRm );
nkeynes@901	2001	pop_fpul();
nkeynes@901	2002	}
nkeynes@377	2003	:}
nkeynes@377	2004	FCNVSD FPUL, FRn {:
nkeynes@671	2005	COUNT_INST(I_FCNVSD);
nkeynes@377	2006	check_fpuen();
nkeynes@901	2007	if( sh4_x86.double_prec ) {
nkeynes@901	2008	push_fpul();
nkeynes@901	2009	pop_dr( FRn );
nkeynes@901	2010	}
nkeynes@377	2011	:}
nkeynes@375	2012
nkeynes@359	2013	/* Floating point instructions */
nkeynes@374	2014	FABS FRn {:
nkeynes@671	2015	COUNT_INST(I_FABS);
nkeynes@377	2016	check_fpuen();
nkeynes@901	2017	if( sh4_x86.double_prec ) {
nkeynes@901	2018	push_dr(FRn);
nkeynes@901	2019	FABS_st0();
nkeynes@901	2020	pop_dr(FRn);
nkeynes@901	2021	} else {
nkeynes@901	2022	push_fr(FRn);
nkeynes@901	2023	FABS_st0();
nkeynes@901	2024	pop_fr(FRn);
nkeynes@901	2025	}
nkeynes@374	2026	:}
nkeynes@377	2027	FADD FRm, FRn {:
nkeynes@671	2028	COUNT_INST(I_FADD);
nkeynes@377	2029	check_fpuen();
nkeynes@901	2030	if( sh4_x86.double_prec ) {
nkeynes@901	2031	push_dr(FRm);
nkeynes@901	2032	push_dr(FRn);
nkeynes@901	2033	FADDP_st(1);
nkeynes@901	2034	pop_dr(FRn);
nkeynes@901	2035	} else {
nkeynes@901	2036	push_fr(FRm);
nkeynes@901	2037	push_fr(FRn);
nkeynes@901	2038	FADDP_st(1);
nkeynes@901	2039	pop_fr(FRn);
nkeynes@901	2040	}
nkeynes@375	2041	:}
nkeynes@377	2042	FDIV FRm, FRn {:
nkeynes@671	2043	COUNT_INST(I_FDIV);
nkeynes@377	2044	check_fpuen();
nkeynes@901	2045	if( sh4_x86.double_prec ) {
nkeynes@901	2046	push_dr(FRn);
nkeynes@901	2047	push_dr(FRm);
nkeynes@901	2048	FDIVP_st(1);
nkeynes@901	2049	pop_dr(FRn);
nkeynes@901	2050	} else {
nkeynes@901	2051	push_fr(FRn);
nkeynes@901	2052	push_fr(FRm);
nkeynes@901	2053	FDIVP_st(1);
nkeynes@901	2054	pop_fr(FRn);
nkeynes@901	2055	}
nkeynes@375	2056	:}
nkeynes@375	2057	FMAC FR0, FRm, FRn {:
nkeynes@671	2058	COUNT_INST(I_FMAC);
nkeynes@377	2059	check_fpuen();
nkeynes@901	2060	if( sh4_x86.double_prec ) {
nkeynes@901	2061	push_dr( 0 );
nkeynes@901	2062	push_dr( FRm );
nkeynes@901	2063	FMULP_st(1);
nkeynes@901	2064	push_dr( FRn );
nkeynes@901	2065	FADDP_st(1);
nkeynes@901	2066	pop_dr( FRn );
nkeynes@901	2067	} else {
nkeynes@901	2068	push_fr( 0 );
nkeynes@901	2069	push_fr( FRm );
nkeynes@901	2070	FMULP_st(1);
nkeynes@901	2071	push_fr( FRn );
nkeynes@901	2072	FADDP_st(1);
nkeynes@901	2073	pop_fr( FRn );
nkeynes@901	2074	}
nkeynes@375	2075	:}
nkeynes@375	2076
nkeynes@377	2077	FMUL FRm, FRn {:
nkeynes@671	2078	COUNT_INST(I_FMUL);
nkeynes@377	2079	check_fpuen();
nkeynes@901	2080	if( sh4_x86.double_prec ) {
nkeynes@901	2081	push_dr(FRm);
nkeynes@901	2082	push_dr(FRn);
nkeynes@901	2083	FMULP_st(1);
nkeynes@901	2084	pop_dr(FRn);
nkeynes@901	2085	} else {
nkeynes@901	2086	push_fr(FRm);
nkeynes@901	2087	push_fr(FRn);
nkeynes@901	2088	FMULP_st(1);
nkeynes@901	2089	pop_fr(FRn);
nkeynes@901	2090	}
nkeynes@377	2091	:}
nkeynes@377	2092	FNEG FRn {:
nkeynes@671	2093	COUNT_INST(I_FNEG);
nkeynes@377	2094	check_fpuen();
nkeynes@901	2095	if( sh4_x86.double_prec ) {
nkeynes@901	2096	push_dr(FRn);
nkeynes@901	2097	FCHS_st0();
nkeynes@901	2098	pop_dr(FRn);
nkeynes@901	2099	} else {
nkeynes@901	2100	push_fr(FRn);
nkeynes@901	2101	FCHS_st0();
nkeynes@901	2102	pop_fr(FRn);
nkeynes@901	2103	}
nkeynes@377	2104	:}
nkeynes@377	2105	FSRRA FRn {:
nkeynes@671	2106	COUNT_INST(I_FSRRA);
nkeynes@377	2107	check_fpuen();
nkeynes@901	2108	if( sh4_x86.double_prec == 0 ) {
nkeynes@901	2109	FLD1_st0();
nkeynes@901	2110	push_fr(FRn);
nkeynes@901	2111	FSQRT_st0();
nkeynes@901	2112	FDIVP_st(1);
nkeynes@901	2113	pop_fr(FRn);
nkeynes@901	2114	}
nkeynes@377	2115	:}
nkeynes@377	2116	FSQRT FRn {:
nkeynes@671	2117	COUNT_INST(I_FSQRT);
nkeynes@377	2118	check_fpuen();
nkeynes@901	2119	if( sh4_x86.double_prec ) {
nkeynes@901	2120	push_dr(FRn);
nkeynes@901	2121	FSQRT_st0();
nkeynes@901	2122	pop_dr(FRn);
nkeynes@901	2123	} else {
nkeynes@901	2124	push_fr(FRn);
nkeynes@901	2125	FSQRT_st0();
nkeynes@901	2126	pop_fr(FRn);
nkeynes@901	2127	}
nkeynes@377	2128	:}
nkeynes@377	2129	FSUB FRm, FRn {:
nkeynes@671	2130	COUNT_INST(I_FSUB);
nkeynes@377	2131	check_fpuen();
nkeynes@901	2132	if( sh4_x86.double_prec ) {
nkeynes@901	2133	push_dr(FRn);
nkeynes@901	2134	push_dr(FRm);
nkeynes@901	2135	FSUBP_st(1);
nkeynes@901	2136	pop_dr(FRn);
nkeynes@901	2137	} else {
nkeynes@901	2138	push_fr(FRn);
nkeynes@901	2139	push_fr(FRm);
nkeynes@901	2140	FSUBP_st(1);
nkeynes@901	2141	pop_fr(FRn);
nkeynes@901	2142	}
nkeynes@377	2143	:}
nkeynes@377	2144
nkeynes@377	2145	FCMP/EQ FRm, FRn {:
nkeynes@671	2146	COUNT_INST(I_FCMPEQ);
nkeynes@377	2147	check_fpuen();
nkeynes@901	2148	if( sh4_x86.double_prec ) {
nkeynes@901	2149	push_dr(FRm);
nkeynes@901	2150	push_dr(FRn);
nkeynes@901	2151	} else {
nkeynes@901	2152	push_fr(FRm);
nkeynes@901	2153	push_fr(FRn);
nkeynes@901	2154	}
nkeynes@377	2155	FCOMIP_st(1);
nkeynes@377	2156	SETE_t();
nkeynes@377	2157	FPOP_st();
nkeynes@901	2158	sh4_x86.tstate = TSTATE_E;
nkeynes@377	2159	:}
nkeynes@377	2160	FCMP/GT FRm, FRn {:
nkeynes@671	2161	COUNT_INST(I_FCMPGT);
nkeynes@377	2162	check_fpuen();
nkeynes@901	2163	if( sh4_x86.double_prec ) {
nkeynes@901	2164	push_dr(FRm);
nkeynes@901	2165	push_dr(FRn);
nkeynes@901	2166	} else {
nkeynes@901	2167	push_fr(FRm);
nkeynes@901	2168	push_fr(FRn);
nkeynes@901	2169	}
nkeynes@377	2170	FCOMIP_st(1);
nkeynes@377	2171	SETA_t();
nkeynes@377	2172	FPOP_st();
nkeynes@901	2173	sh4_x86.tstate = TSTATE_A;
nkeynes@377	2174	:}
nkeynes@377	2175
nkeynes@377	2176	FSCA FPUL, FRn {:
nkeynes@671	2177	COUNT_INST(I_FSCA);
nkeynes@377	2178	check_fpuen();
nkeynes@901	2179	if( sh4_x86.double_prec == 0 ) {
nkeynes@905	2180	LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905	2181	load_spreg( R_EAX, R_FPUL );
nkeynes@905	2182	call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901	2183	}
nkeynes@417	2184	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	2185	:}
nkeynes@377	2186	FIPR FVm, FVn {:
nkeynes@671	2187	COUNT_INST(I_FIPR);
nkeynes@377	2188	check_fpuen();
nkeynes@901	2189	if( sh4_x86.double_prec == 0 ) {
nkeynes@904	2190	if( sh4_x86.sse3_enabled ) {
nkeynes@903	2191	MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903	2192	MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903	2193	HADDPS_xmm_xmm( 4, 4 );
nkeynes@903	2194	HADDPS_xmm_xmm( 4, 4 );
nkeynes@903	2195	MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903	2196	} else {
nkeynes@904	2197	push_fr( FVm<<2 );
nkeynes@903	2198	push_fr( FVn<<2 );
nkeynes@903	2199	FMULP_st(1);
nkeynes@903	2200	push_fr( (FVm<<2)+1);
nkeynes@903	2201	push_fr( (FVn<<2)+1);
nkeynes@903	2202	FMULP_st(1);
nkeynes@903	2203	FADDP_st(1);
nkeynes@903	2204	push_fr( (FVm<<2)+2);
nkeynes@903	2205	push_fr( (FVn<<2)+2);
nkeynes@903	2206	FMULP_st(1);
nkeynes@903	2207	FADDP_st(1);
nkeynes@903	2208	push_fr( (FVm<<2)+3);
nkeynes@903	2209	push_fr( (FVn<<2)+3);
nkeynes@903	2210	FMULP_st(1);
nkeynes@903	2211	FADDP_st(1);
nkeynes@903	2212	pop_fr( (FVn<<2)+3);
nkeynes@904	2213	}
nkeynes@901	2214	}
nkeynes@377	2215	:}
nkeynes@377	2216	FTRV XMTRX, FVn {:
nkeynes@671	2217	COUNT_INST(I_FTRV);
nkeynes@377	2218	check_fpuen();
nkeynes@901	2219	if( sh4_x86.double_prec == 0 ) {
nkeynes@903	2220	if( sh4_x86.sse3_enabled ) {
nkeynes@903	2221	MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2
nkeynes@903	2222	MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6
nkeynes@903	2223	MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10
nkeynes@903	2224	MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903	2225
nkeynes@903	2226	MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903	2227	MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903	2228	MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903	2229	MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903	2230	MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V1
nkeynes@903	2231	MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V3
nkeynes@903	2232	MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V0
nkeynes@903	2233	MOVHLPS_xmm_xmm( 7, 7 ); // V2 V2 V2 V2
nkeynes@903	2234	MULPS_xmm_xmm( 0, 4 );
nkeynes@903	2235	MULPS_xmm_xmm( 1, 5 );
nkeynes@903	2236	MULPS_xmm_xmm( 2, 6 );
nkeynes@903	2237	MULPS_xmm_xmm( 3, 7 );
nkeynes@903	2238	ADDPS_xmm_xmm( 5, 4 );
nkeynes@903	2239	ADDPS_xmm_xmm( 7, 6 );
nkeynes@903	2240	ADDPS_xmm_xmm( 6, 4 );
nkeynes@903	2241	MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903	2242	} else {
nkeynes@903	2243	LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903	2244	call_func1( sh4_ftrv, R_EAX );
nkeynes@903	2245	}
nkeynes@901	2246	}
nkeynes@417	2247	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	2248	:}
nkeynes@377	2249
nkeynes@377	2250	FRCHG {:
nkeynes@671	2251	COUNT_INST(I_FRCHG);
nkeynes@377	2252	check_fpuen();
nkeynes@953	2253	XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );
nkeynes@669	2254	call_func0( sh4_switch_fr_banks );
nkeynes@417	2255	sh4_x86.tstate = TSTATE_NONE;
nkeynes@377	2256	:}
nkeynes@377	2257	FSCHG {:
nkeynes@671	2258	COUNT_INST(I_FSCHG);
nkeynes@377	2259	check_fpuen();
nkeynes@953	2260	XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);
nkeynes@953	2261	XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417	2262	sh4_x86.tstate = TSTATE_NONE;
nkeynes@901	2263	sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377	2264	:}
nkeynes@359	2265
nkeynes@359	2266	/* Processor control instructions */
nkeynes@368	2267	LDC Rm, SR {:
nkeynes@671	2268	COUNT_INST(I_LDCSR);
nkeynes@386	2269	if( sh4_x86.in_delay_slot ) {
nkeynes@386	2270	SLOTILLEGAL();
nkeynes@386	2271	} else {
nkeynes@386	2272	check_priv();
nkeynes@386	2273	load_reg( R_EAX, Rm );
nkeynes@386	2274	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	2275	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	2276	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953	2277	return 2;
nkeynes@386	2278	}
nkeynes@368	2279	:}
nkeynes@359	2280	LDC Rm, GBR {:
nkeynes@671	2281	COUNT_INST(I_LDC);
nkeynes@359	2282	load_reg( R_EAX, Rm );
nkeynes@359	2283	store_spreg( R_EAX, R_GBR );
nkeynes@359	2284	:}
nkeynes@359	2285	LDC Rm, VBR {:
nkeynes@671	2286	COUNT_INST(I_LDC);
nkeynes@386	2287	check_priv();
nkeynes@359	2288	load_reg( R_EAX, Rm );
nkeynes@359	2289	store_spreg( R_EAX, R_VBR );
nkeynes@417	2290	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2291	:}
nkeynes@359	2292	LDC Rm, SSR {:
nkeynes@671	2293	COUNT_INST(I_LDC);
nkeynes@386	2294	check_priv();
nkeynes@359	2295	load_reg( R_EAX, Rm );
nkeynes@359	2296	store_spreg( R_EAX, R_SSR );
nkeynes@417	2297	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2298	:}
nkeynes@359	2299	LDC Rm, SGR {:
nkeynes@671	2300	COUNT_INST(I_LDC);
nkeynes@386	2301	check_priv();
nkeynes@359	2302	load_reg( R_EAX, Rm );
nkeynes@359	2303	store_spreg( R_EAX, R_SGR );
nkeynes@417	2304	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2305	:}
nkeynes@359	2306	LDC Rm, SPC {:
nkeynes@671	2307	COUNT_INST(I_LDC);
nkeynes@386	2308	check_priv();
nkeynes@359	2309	load_reg( R_EAX, Rm );
nkeynes@359	2310	store_spreg( R_EAX, R_SPC );
nkeynes@417	2311	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2312	:}
nkeynes@359	2313	LDC Rm, DBR {:
nkeynes@671	2314	COUNT_INST(I_LDC);
nkeynes@386	2315	check_priv();
nkeynes@359	2316	load_reg( R_EAX, Rm );
nkeynes@359	2317	store_spreg( R_EAX, R_DBR );
nkeynes@417	2318	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2319	:}
nkeynes@374	2320	LDC Rm, Rn_BANK {:
nkeynes@671	2321	COUNT_INST(I_LDC);
nkeynes@386	2322	check_priv();
nkeynes@374	2323	load_reg( R_EAX, Rm );
nkeynes@374	2324	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417	2325	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	2326	:}
nkeynes@359	2327	LDC.L @Rm+, GBR {:
nkeynes@671	2328	COUNT_INST(I_LDCM);
nkeynes@359	2329	load_reg( R_EAX, Rm );
nkeynes@395	2330	check_ralign32( R_EAX );
nkeynes@953	2331	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2332	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2333	store_spreg( R_EAX, R_GBR );
nkeynes@417	2334	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2335	:}
nkeynes@368	2336	LDC.L @Rm+, SR {:
nkeynes@671	2337	COUNT_INST(I_LDCSRM);
nkeynes@386	2338	if( sh4_x86.in_delay_slot ) {
nkeynes@386	2339	SLOTILLEGAL();
nkeynes@386	2340	} else {
nkeynes@586	2341	check_priv();
nkeynes@386	2342	load_reg( R_EAX, Rm );
nkeynes@395	2343	check_ralign32( R_EAX );
nkeynes@953	2344	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2345	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@386	2346	call_func1( sh4_write_sr, R_EAX );
nkeynes@386	2347	sh4_x86.fpuen_checked = FALSE;
nkeynes@417	2348	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953	2349	return 2;
nkeynes@386	2350	}
nkeynes@359	2351	:}
nkeynes@359	2352	LDC.L @Rm+, VBR {:
nkeynes@671	2353	COUNT_INST(I_LDCM);
nkeynes@586	2354	check_priv();
nkeynes@359	2355	load_reg( R_EAX, Rm );
nkeynes@395	2356	check_ralign32( R_EAX );
nkeynes@953	2357	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2358	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2359	store_spreg( R_EAX, R_VBR );
nkeynes@417	2360	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2361	:}
nkeynes@359	2362	LDC.L @Rm+, SSR {:
nkeynes@671	2363	COUNT_INST(I_LDCM);
nkeynes@586	2364	check_priv();
nkeynes@359	2365	load_reg( R_EAX, Rm );
nkeynes@416	2366	check_ralign32( R_EAX );
nkeynes@953	2367	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2368	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2369	store_spreg( R_EAX, R_SSR );
nkeynes@417	2370	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2371	:}
nkeynes@359	2372	LDC.L @Rm+, SGR {:
nkeynes@671	2373	COUNT_INST(I_LDCM);
nkeynes@586	2374	check_priv();
nkeynes@359	2375	load_reg( R_EAX, Rm );
nkeynes@395	2376	check_ralign32( R_EAX );
nkeynes@953	2377	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2378	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2379	store_spreg( R_EAX, R_SGR );
nkeynes@417	2380	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2381	:}
nkeynes@359	2382	LDC.L @Rm+, SPC {:
nkeynes@671	2383	COUNT_INST(I_LDCM);
nkeynes@586	2384	check_priv();
nkeynes@359	2385	load_reg( R_EAX, Rm );
nkeynes@395	2386	check_ralign32( R_EAX );
nkeynes@953	2387	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2388	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2389	store_spreg( R_EAX, R_SPC );
nkeynes@417	2390	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2391	:}
nkeynes@359	2392	LDC.L @Rm+, DBR {:
nkeynes@671	2393	COUNT_INST(I_LDCM);
nkeynes@586	2394	check_priv();
nkeynes@359	2395	load_reg( R_EAX, Rm );
nkeynes@395	2396	check_ralign32( R_EAX );
nkeynes@953	2397	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2398	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2399	store_spreg( R_EAX, R_DBR );
nkeynes@417	2400	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2401	:}
nkeynes@359	2402	LDC.L @Rm+, Rn_BANK {:
nkeynes@671	2403	COUNT_INST(I_LDCM);
nkeynes@586	2404	check_priv();
nkeynes@374	2405	load_reg( R_EAX, Rm );
nkeynes@395	2406	check_ralign32( R_EAX );
nkeynes@953	2407	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2408	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@374	2409	store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417	2410	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2411	:}
nkeynes@626	2412	LDS Rm, FPSCR {:
nkeynes@673	2413	COUNT_INST(I_LDSFPSCR);
nkeynes@626	2414	check_fpuen();
nkeynes@359	2415	load_reg( R_EAX, Rm );
nkeynes@669	2416	call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417	2417	sh4_x86.tstate = TSTATE_NONE;
nkeynes@901	2418	return 2;
nkeynes@359	2419	:}
nkeynes@359	2420	LDS.L @Rm+, FPSCR {:
nkeynes@673	2421	COUNT_INST(I_LDSFPSCRM);
nkeynes@626	2422	check_fpuen();
nkeynes@359	2423	load_reg( R_EAX, Rm );
nkeynes@395	2424	check_ralign32( R_EAX );
nkeynes@953	2425	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2426	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@669	2427	call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417	2428	sh4_x86.tstate = TSTATE_NONE;
nkeynes@901	2429	return 2;
nkeynes@359	2430	:}
nkeynes@359	2431	LDS Rm, FPUL {:
nkeynes@671	2432	COUNT_INST(I_LDS);
nkeynes@626	2433	check_fpuen();
nkeynes@359	2434	load_reg( R_EAX, Rm );
nkeynes@359	2435	store_spreg( R_EAX, R_FPUL );
nkeynes@359	2436	:}
nkeynes@359	2437	LDS.L @Rm+, FPUL {:
nkeynes@671	2438	COUNT_INST(I_LDSM);
nkeynes@626	2439	check_fpuen();
nkeynes@359	2440	load_reg( R_EAX, Rm );
nkeynes@395	2441	check_ralign32( R_EAX );
nkeynes@953	2442	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2443	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2444	store_spreg( R_EAX, R_FPUL );
nkeynes@417	2445	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2446	:}
nkeynes@359	2447	LDS Rm, MACH {:
nkeynes@671	2448	COUNT_INST(I_LDS);
nkeynes@359	2449	load_reg( R_EAX, Rm );
nkeynes@359	2450	store_spreg( R_EAX, R_MACH );
nkeynes@359	2451	:}
nkeynes@359	2452	LDS.L @Rm+, MACH {:
nkeynes@671	2453	COUNT_INST(I_LDSM);
nkeynes@359	2454	load_reg( R_EAX, Rm );
nkeynes@395	2455	check_ralign32( R_EAX );
nkeynes@953	2456	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2457	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2458	store_spreg( R_EAX, R_MACH );
nkeynes@417	2459	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2460	:}
nkeynes@359	2461	LDS Rm, MACL {:
nkeynes@671	2462	COUNT_INST(I_LDS);
nkeynes@359	2463	load_reg( R_EAX, Rm );
nkeynes@359	2464	store_spreg( R_EAX, R_MACL );
nkeynes@359	2465	:}
nkeynes@359	2466	LDS.L @Rm+, MACL {:
nkeynes@671	2467	COUNT_INST(I_LDSM);
nkeynes@359	2468	load_reg( R_EAX, Rm );
nkeynes@395	2469	check_ralign32( R_EAX );
nkeynes@953	2470	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2471	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2472	store_spreg( R_EAX, R_MACL );
nkeynes@417	2473	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2474	:}
nkeynes@359	2475	LDS Rm, PR {:
nkeynes@671	2476	COUNT_INST(I_LDS);
nkeynes@359	2477	load_reg( R_EAX, Rm );
nkeynes@359	2478	store_spreg( R_EAX, R_PR );
nkeynes@359	2479	:}
nkeynes@359	2480	LDS.L @Rm+, PR {:
nkeynes@671	2481	COUNT_INST(I_LDSM);
nkeynes@359	2482	load_reg( R_EAX, Rm );
nkeynes@395	2483	check_ralign32( R_EAX );
nkeynes@953	2484	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586	2485	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@359	2486	store_spreg( R_EAX, R_PR );
nkeynes@417	2487	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2488	:}
nkeynes@550	2489	LDTLB {:
nkeynes@671	2490	COUNT_INST(I_LDTLB);
nkeynes@553	2491	call_func0( MMU_ldtlb );
nkeynes@875	2492	sh4_x86.tstate = TSTATE_NONE;
nkeynes@550	2493	:}
nkeynes@671	2494	OCBI @Rn {:
nkeynes@671	2495	COUNT_INST(I_OCBI);
nkeynes@671	2496	:}
nkeynes@671	2497	OCBP @Rn {:
nkeynes@671	2498	COUNT_INST(I_OCBP);
nkeynes@671	2499	:}
nkeynes@671	2500	OCBWB @Rn {:
nkeynes@671	2501	COUNT_INST(I_OCBWB);
nkeynes@671	2502	:}
nkeynes@374	2503	PREF @Rn {:
nkeynes@671	2504	COUNT_INST(I_PREF);
nkeynes@374	2505	load_reg( R_EAX, Rn );
nkeynes@953	2506	MEM_PREFETCH( R_EAX );
nkeynes@417	2507	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	2508	:}
nkeynes@388	2509	SLEEP {:
nkeynes@671	2510	COUNT_INST(I_SLEEP);
nkeynes@388	2511	check_priv();
nkeynes@388	2512	call_func0( sh4_sleep );
nkeynes@417	2513	sh4_x86.tstate = TSTATE_NONE;
nkeynes@590	2514	sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408	2515	return 2;
nkeynes@388	2516	:}
nkeynes@386	2517	STC SR, Rn {:
nkeynes@671	2518	COUNT_INST(I_STCSR);
nkeynes@386	2519	check_priv();
nkeynes@386	2520	call_func0(sh4_read_sr);
nkeynes@386	2521	store_reg( R_EAX, Rn );
nkeynes@417	2522	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2523	:}
nkeynes@359	2524	STC GBR, Rn {:
nkeynes@671	2525	COUNT_INST(I_STC);
nkeynes@359	2526	load_spreg( R_EAX, R_GBR );
nkeynes@359	2527	store_reg( R_EAX, Rn );
nkeynes@359	2528	:}
nkeynes@359	2529	STC VBR, Rn {:
nkeynes@671	2530	COUNT_INST(I_STC);
nkeynes@386	2531	check_priv();
nkeynes@359	2532	load_spreg( R_EAX, R_VBR );
nkeynes@359	2533	store_reg( R_EAX, Rn );
nkeynes@417	2534	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2535	:}
nkeynes@359	2536	STC SSR, Rn {:
nkeynes@671	2537	COUNT_INST(I_STC);
nkeynes@386	2538	check_priv();
nkeynes@359	2539	load_spreg( R_EAX, R_SSR );
nkeynes@359	2540	store_reg( R_EAX, Rn );
nkeynes@417	2541	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2542	:}
nkeynes@359	2543	STC SPC, Rn {:
nkeynes@671	2544	COUNT_INST(I_STC);
nkeynes@386	2545	check_priv();
nkeynes@359	2546	load_spreg( R_EAX, R_SPC );
nkeynes@359	2547	store_reg( R_EAX, Rn );
nkeynes@417	2548	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2549	:}
nkeynes@359	2550	STC SGR, Rn {:
nkeynes@671	2551	COUNT_INST(I_STC);
nkeynes@386	2552	check_priv();
nkeynes@359	2553	load_spreg( R_EAX, R_SGR );
nkeynes@359	2554	store_reg( R_EAX, Rn );
nkeynes@417	2555	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2556	:}
nkeynes@359	2557	STC DBR, Rn {:
nkeynes@671	2558	COUNT_INST(I_STC);
nkeynes@386	2559	check_priv();
nkeynes@359	2560	load_spreg( R_EAX, R_DBR );
nkeynes@359	2561	store_reg( R_EAX, Rn );
nkeynes@417	2562	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2563	:}
nkeynes@374	2564	STC Rm_BANK, Rn {:
nkeynes@671	2565	COUNT_INST(I_STC);
nkeynes@386	2566	check_priv();
nkeynes@374	2567	load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374	2568	store_reg( R_EAX, Rn );
nkeynes@417	2569	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2570	:}
nkeynes@374	2571	STC.L SR, @-Rn {:
nkeynes@671	2572	COUNT_INST(I_STCSRM);
nkeynes@586	2573	check_priv();
nkeynes@953	2574	call_func0( sh4_read_sr );
nkeynes@953	2575	MOV_r32_r32( R_EAX, R_EDX );
nkeynes@586	2576	load_reg( R_EAX, Rn );
nkeynes@586	2577	check_walign32( R_EAX );
nkeynes@953	2578	LEA_r32disp8_r32( R_EAX, -4, R_EAX );
nkeynes@953	2579	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2580	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2581	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2582	:}
nkeynes@359	2583	STC.L VBR, @-Rn {:
nkeynes@671	2584	COUNT_INST(I_STCM);
nkeynes@586	2585	check_priv();
nkeynes@586	2586	load_reg( R_EAX, Rn );
nkeynes@586	2587	check_walign32( R_EAX );
nkeynes@586	2588	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2589	load_spreg( R_EDX, R_VBR );
nkeynes@953	2590	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2591	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2592	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2593	:}
nkeynes@359	2594	STC.L SSR, @-Rn {:
nkeynes@671	2595	COUNT_INST(I_STCM);
nkeynes@586	2596	check_priv();
nkeynes@586	2597	load_reg( R_EAX, Rn );
nkeynes@586	2598	check_walign32( R_EAX );
nkeynes@586	2599	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2600	load_spreg( R_EDX, R_SSR );
nkeynes@953	2601	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2602	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2603	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2604	:}
nkeynes@416	2605	STC.L SPC, @-Rn {:
nkeynes@671	2606	COUNT_INST(I_STCM);
nkeynes@586	2607	check_priv();
nkeynes@586	2608	load_reg( R_EAX, Rn );
nkeynes@586	2609	check_walign32( R_EAX );
nkeynes@586	2610	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2611	load_spreg( R_EDX, R_SPC );
nkeynes@953	2612	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2613	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2614	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2615	:}
nkeynes@359	2616	STC.L SGR, @-Rn {:
nkeynes@671	2617	COUNT_INST(I_STCM);
nkeynes@586	2618	check_priv();
nkeynes@586	2619	load_reg( R_EAX, Rn );
nkeynes@586	2620	check_walign32( R_EAX );
nkeynes@586	2621	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2622	load_spreg( R_EDX, R_SGR );
nkeynes@953	2623	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2624	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2625	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2626	:}
nkeynes@359	2627	STC.L DBR, @-Rn {:
nkeynes@671	2628	COUNT_INST(I_STCM);
nkeynes@586	2629	check_priv();
nkeynes@586	2630	load_reg( R_EAX, Rn );
nkeynes@586	2631	check_walign32( R_EAX );
nkeynes@586	2632	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2633	load_spreg( R_EDX, R_DBR );
nkeynes@953	2634	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2635	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2636	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2637	:}
nkeynes@374	2638	STC.L Rm_BANK, @-Rn {:
nkeynes@671	2639	COUNT_INST(I_STCM);
nkeynes@586	2640	check_priv();
nkeynes@586	2641	load_reg( R_EAX, Rn );
nkeynes@586	2642	check_walign32( R_EAX );
nkeynes@586	2643	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2644	load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@953	2645	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2646	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2647	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374	2648	:}
nkeynes@359	2649	STC.L GBR, @-Rn {:
nkeynes@671	2650	COUNT_INST(I_STCM);
nkeynes@586	2651	load_reg( R_EAX, Rn );
nkeynes@586	2652	check_walign32( R_EAX );
nkeynes@586	2653	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2654	load_spreg( R_EDX, R_GBR );
nkeynes@953	2655	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2656	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2657	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2658	:}
nkeynes@359	2659	STS FPSCR, Rn {:
nkeynes@673	2660	COUNT_INST(I_STSFPSCR);
nkeynes@626	2661	check_fpuen();
nkeynes@359	2662	load_spreg( R_EAX, R_FPSCR );
nkeynes@359	2663	store_reg( R_EAX, Rn );
nkeynes@359	2664	:}
nkeynes@359	2665	STS.L FPSCR, @-Rn {:
nkeynes@673	2666	COUNT_INST(I_STSFPSCRM);
nkeynes@626	2667	check_fpuen();
nkeynes@586	2668	load_reg( R_EAX, Rn );
nkeynes@586	2669	check_walign32( R_EAX );
nkeynes@586	2670	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2671	load_spreg( R_EDX, R_FPSCR );
nkeynes@953	2672	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2673	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2674	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2675	:}
nkeynes@359	2676	STS FPUL, Rn {:
nkeynes@671	2677	COUNT_INST(I_STS);
nkeynes@626	2678	check_fpuen();
nkeynes@359	2679	load_spreg( R_EAX, R_FPUL );
nkeynes@359	2680	store_reg( R_EAX, Rn );
nkeynes@359	2681	:}
nkeynes@359	2682	STS.L FPUL, @-Rn {:
nkeynes@671	2683	COUNT_INST(I_STSM);
nkeynes@626	2684	check_fpuen();
nkeynes@586	2685	load_reg( R_EAX, Rn );
nkeynes@586	2686	check_walign32( R_EAX );
nkeynes@586	2687	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2688	load_spreg( R_EDX, R_FPUL );
nkeynes@953	2689	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2690	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2691	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2692	:}
nkeynes@359	2693	STS MACH, Rn {:
nkeynes@671	2694	COUNT_INST(I_STS);
nkeynes@359	2695	load_spreg( R_EAX, R_MACH );
nkeynes@359	2696	store_reg( R_EAX, Rn );
nkeynes@359	2697	:}
nkeynes@359	2698	STS.L MACH, @-Rn {:
nkeynes@671	2699	COUNT_INST(I_STSM);
nkeynes@586	2700	load_reg( R_EAX, Rn );
nkeynes@586	2701	check_walign32( R_EAX );
nkeynes@586	2702	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2703	load_spreg( R_EDX, R_MACH );
nkeynes@953	2704	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2705	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2706	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2707	:}
nkeynes@359	2708	STS MACL, Rn {:
nkeynes@671	2709	COUNT_INST(I_STS);
nkeynes@359	2710	load_spreg( R_EAX, R_MACL );
nkeynes@359	2711	store_reg( R_EAX, Rn );
nkeynes@359	2712	:}
nkeynes@359	2713	STS.L MACL, @-Rn {:
nkeynes@671	2714	COUNT_INST(I_STSM);
nkeynes@586	2715	load_reg( R_EAX, Rn );
nkeynes@586	2716	check_walign32( R_EAX );
nkeynes@586	2717	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2718	load_spreg( R_EDX, R_MACL );
nkeynes@953	2719	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2720	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2721	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2722	:}
nkeynes@359	2723	STS PR, Rn {:
nkeynes@671	2724	COUNT_INST(I_STS);
nkeynes@359	2725	load_spreg( R_EAX, R_PR );
nkeynes@359	2726	store_reg( R_EAX, Rn );
nkeynes@359	2727	:}
nkeynes@359	2728	STS.L PR, @-Rn {:
nkeynes@671	2729	COUNT_INST(I_STSM);
nkeynes@586	2730	load_reg( R_EAX, Rn );
nkeynes@586	2731	check_walign32( R_EAX );
nkeynes@586	2732	ADD_imm8s_r32( -4, R_EAX );
nkeynes@586	2733	load_spreg( R_EDX, R_PR );
nkeynes@953	2734	MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@586	2735	ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@417	2736	sh4_x86.tstate = TSTATE_NONE;
nkeynes@359	2737	:}
nkeynes@359	2738
nkeynes@671	2739	NOP {:
nkeynes@671	2740	COUNT_INST(I_NOP);
nkeynes@671	2741	/* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
nkeynes@671	2742	:}
nkeynes@359	2743	%%
nkeynes@590	2744	sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359	2745	return 0;
nkeynes@359	2746	}