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lxdream.org :: lxdream/src/sh4/sh4x86.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.in
changeset 927:17b6b9e245d8
prev926:68f3e0fe02f1
next929:fd8cb0c82f5f
next953:f4a156508ad1
author nkeynes
date Mon Dec 15 10:44:56 2008 +0000 (11 years ago)
permissions -rw-r--r--
last change Add return-address-modifying exception return code to mmu TLB lookups (a little bit faster)
file annotate diff log raw
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/**
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 * $Id$
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 * 
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 * SH4 => x86 translation. This version does no real optimization, it just
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 * outputs straight-line x86 code - it mainly exists to provide a baseline
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 * to test the optimizing versions against.
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 *
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 * Copyright (c) 2007 Nathan Keynes.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 */
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#include <assert.h>
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#include <math.h>
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#ifndef NDEBUG
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#define DEBUG_JUMPS 1
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#endif
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#include "lxdream.h"
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#include "sh4/xltcache.h"
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#include "sh4/sh4core.h"
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#include "sh4/sh4trans.h"
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#include "sh4/sh4stat.h"
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#include "sh4/sh4mmio.h"
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#include "sh4/x86op.h"
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#include "clock.h"
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#define DEFAULT_BACKPATCH_SIZE 4096
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struct backpatch_record {
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    uint32_t fixup_offset;
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    uint32_t fixup_icount;
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    int32_t exc_code;
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};
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#define DELAY_NONE 0
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#define DELAY_PC 1
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#define DELAY_PC_PR 2
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/** 
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 * Struct to manage internal translation state. This state is not saved -
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 * it is only valid between calls to sh4_translate_begin_block() and
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 * sh4_translate_end_block()
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 */
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struct sh4_x86_state {
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    int in_delay_slot;
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    gboolean priv_checked; /* true if we've already checked the cpu mode. */
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    gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
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    gboolean branch_taken; /* true if we branched unconditionally */
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    gboolean double_prec; /* true if FPU is in double-precision mode */
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    gboolean double_size; /* true if FPU is in double-size mode */
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    gboolean sse3_enabled; /* true if host supports SSE3 instructions */
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    uint32_t block_start_pc;
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    uint32_t stack_posn;   /* Trace stack height for alignment purposes */
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    int tstate;
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    /* mode flags */
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    gboolean tlb_on; /* True if tlb translation is active */
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    /* Allocated memory for the (block-wide) back-patch list */
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    struct backpatch_record *backpatch_list;
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    uint32_t backpatch_posn;
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    uint32_t backpatch_size;
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};
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#define TSTATE_NONE -1
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#define TSTATE_O    0
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#define TSTATE_C    2
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#define TSTATE_E    4
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#define TSTATE_NE   5
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#define TSTATE_G    0xF
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#define TSTATE_GE   0xD
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#define TSTATE_A    7
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#define TSTATE_AE   3
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#ifdef ENABLE_SH4STATS
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#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
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#else
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#define COUNT_INST(id)
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#endif
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/** Branch if T is set (either in the current cflags, or in sh4r.t) */
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#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
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/** Branch if T is clear (either in the current cflags or in sh4r.t) */
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#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
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	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
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    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
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static struct sh4_x86_state sh4_x86;
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static uint32_t max_int = 0x7FFFFFFF;
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static uint32_t min_int = 0x80000000;
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static uint32_t save_fcw; /* save value for fpu control word */
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static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
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gboolean is_sse3_supported()
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{
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    uint32_t features;
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    __asm__ __volatile__(
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        "mov $0x01, %%eax\n\t"
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        "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
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    return (features & 1) ? TRUE : FALSE;
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}
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void sh4_translate_init(void)
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{
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    sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
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    sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
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    sh4_x86.sse3_enabled = is_sse3_supported();
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}
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static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
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{
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    if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
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	sh4_x86.backpatch_size <<= 1;
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	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
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					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
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	assert( sh4_x86.backpatch_list != NULL );
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    }
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    if( sh4_x86.in_delay_slot ) {
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	fixup_pc -= 2;
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    }
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
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	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
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    sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
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    sh4_x86.backpatch_posn++;
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}
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/**
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 * Emit an instruction to load an SH4 reg into a real register
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 */
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static inline void load_reg( int x86reg, int sh4reg ) 
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{
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    /* mov [bp+n], reg */
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    OP(0x8B);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16s( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xBF);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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static inline void load_reg16u( int x86reg, int sh4reg )
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{
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    OP(0x0F);
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    OP(0xB7);
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    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
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}
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#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
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#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
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/**
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 * Emit an instruction to load an immediate value into a register
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 */
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static inline void load_imm32( int x86reg, uint32_t value ) {
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    /* mov #value, reg */
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    OP(0xB8 + x86reg);
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    OP32(value);
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}
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/**
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 * Load an immediate 64-bit quantity (note: x86-64 only)
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 */
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static inline void load_imm64( int x86reg, uint64_t value ) {
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    /* mov #value, reg */
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    REXW();
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    OP(0xB8 + x86reg);
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    OP64(value);
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}
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/**
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 * Emit an instruction to store an SH4 reg (RN)
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 */
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void static inline store_reg( int x86reg, int sh4reg ) {
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    /* mov reg, [bp+n] */
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    OP(0x89);
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    OP(0x45 + (x86reg<<3));
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    OP(REG_OFFSET(r[sh4reg]));
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}
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/**
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 * Load an FR register (single-precision floating point) into an integer x86
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 * register (eg for register-to-register moves)
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 */
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#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
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/**
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 * Load the low half of a DR register (DR or XD) into an integer x86 register 
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 */
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#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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/**
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 * Store an FR register (single-precision floating point) from an integer x86+
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 * register (eg for register-to-register moves)
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 */
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#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
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#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
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#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
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#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
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#define push_fpul()  FLDF_sh4r(R_FPUL)
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#define pop_fpul()   FSTPF_sh4r(R_FPUL)
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#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
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#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
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#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
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#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
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/* Exception checks - Note that all exception checks will clobber EAX */
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#define check_priv( ) \
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    if( !sh4_x86.priv_checked ) { \
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	sh4_x86.priv_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_MD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JE_exc( EXC_SLOT_ILLEGAL );\
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	} else {\
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	    JE_exc( EXC_ILLEGAL );\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }\
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#define check_fpuen( ) \
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    if( !sh4_x86.fpuen_checked ) {\
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	sh4_x86.fpuen_checked = TRUE;\
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	load_spreg( R_EAX, R_SR );\
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	AND_imm32_r32( SR_FD, R_EAX );\
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	if( sh4_x86.in_delay_slot ) {\
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	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
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	} else {\
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	    JNE_exc(EXC_FPU_DISABLED);\
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	}\
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	sh4_x86.tstate = TSTATE_NONE; \
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    }
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#define check_ralign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign16( x86reg ) \
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    TEST_imm32_r32( 0x00000001, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign32( x86reg ) \
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    TEST_imm32_r32( 0x00000003, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define check_ralign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_READ)
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#define check_walign64( x86reg ) \
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    TEST_imm32_r32( 0x00000007, x86reg ); \
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    JNE_exc(EXC_DATA_ADDR_WRITE);
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#define UNDEF(ir)
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#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
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#define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
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#define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
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#define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
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#define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
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#ifdef HAVE_FRAME_ADDRESS
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/**
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 * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) {  call_func1_exc(mmu_vma_to_phys_read, addr_reg, pc); MEM_RESULT(addr_reg); }
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/**
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 * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
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 * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
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 */
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#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1_exc(mmu_vma_to_phys_write, addr_reg, pc); MEM_RESULT(addr_reg); }
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#else
nkeynes@927
   312
#define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@586
   313
#define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
nkeynes@927
   314
#endif
nkeynes@368
   315
nkeynes@590
   316
#define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
nkeynes@388
   317
nkeynes@539
   318
/****** Import appropriate calling conventions ******/
nkeynes@675
   319
#if SIZEOF_VOID_P == 8
nkeynes@539
   320
#include "sh4/ia64abi.h"
nkeynes@675
   321
#else /* 32-bit system */
nkeynes@539
   322
#include "sh4/ia32abi.h"
nkeynes@539
   323
#endif
nkeynes@539
   324
nkeynes@901
   325
void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901
   326
{
nkeynes@927
   327
    enter_block();
nkeynes@901
   328
    sh4_x86.in_delay_slot = FALSE;
nkeynes@901
   329
    sh4_x86.priv_checked = FALSE;
nkeynes@901
   330
    sh4_x86.fpuen_checked = FALSE;
nkeynes@901
   331
    sh4_x86.branch_taken = FALSE;
nkeynes@901
   332
    sh4_x86.backpatch_posn = 0;
nkeynes@901
   333
    sh4_x86.block_start_pc = pc;
nkeynes@901
   334
    sh4_x86.tlb_on = IS_MMU_ENABLED();
nkeynes@901
   335
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
   336
    sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903
   337
    sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901
   338
}
nkeynes@901
   339
nkeynes@901
   340
nkeynes@593
   341
uint32_t sh4_translate_end_block_size()
nkeynes@593
   342
{
nkeynes@596
   343
    if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@901
   344
        return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
nkeynes@596
   345
    } else {
nkeynes@901
   346
        return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
nkeynes@596
   347
    }
nkeynes@593
   348
}
nkeynes@593
   349
nkeynes@593
   350
nkeynes@590
   351
/**
nkeynes@590
   352
 * Embed a breakpoint into the generated code
nkeynes@590
   353
 */
nkeynes@586
   354
void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@586
   355
{
nkeynes@591
   356
    load_imm32( R_EAX, pc );
nkeynes@591
   357
    call_func1( sh4_translate_breakpoint_hit, R_EAX );
nkeynes@875
   358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
   359
}
nkeynes@590
   360
nkeynes@601
   361
nkeynes@601
   362
#define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601
   363
nkeynes@590
   364
/**
nkeynes@590
   365
 * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601
   366
 * can't translate (just page-crossing delay slots at the moment).
nkeynes@601
   367
 * Caller is responsible for setting new_pc before calling this function.
nkeynes@601
   368
 *
nkeynes@601
   369
 * Performs:
nkeynes@601
   370
 *   Set PC = endpc
nkeynes@601
   371
 *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601
   372
 *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601
   373
 *   Call sh4_execute_instruction
nkeynes@601
   374
 *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590
   375
 */
nkeynes@601
   376
void exit_block_emu( sh4vma_t endpc )
nkeynes@590
   377
{
nkeynes@590
   378
    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
nkeynes@590
   379
    ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@586
   380
    
nkeynes@601
   381
    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
nkeynes@590
   382
    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@590
   383
    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
nkeynes@590
   384
    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590
   385
nkeynes@590
   386
    call_func0( sh4_execute_instruction );    
nkeynes@601
   387
    load_spreg( R_EAX, R_PC );
nkeynes@590
   388
    if( sh4_x86.tlb_on ) {
nkeynes@590
   389
	call_func1(xlat_get_code_by_vma,R_EAX);
nkeynes@590
   390
    } else {
nkeynes@590
   391
	call_func1(xlat_get_code,R_EAX);
nkeynes@590
   392
    }
nkeynes@926
   393
    exit_block();
nkeynes@590
   394
} 
nkeynes@539
   395
nkeynes@359
   396
/**
nkeynes@359
   397
 * Translate a single instruction. Delayed branches are handled specially
nkeynes@359
   398
 * by translating both branch and delayed instruction as a single unit (as
nkeynes@359
   399
 * 
nkeynes@586
   400
 * The instruction MUST be in the icache (assert check)
nkeynes@359
   401
 *
nkeynes@359
   402
 * @return true if the instruction marks the end of a basic block
nkeynes@359
   403
 * (eg a branch or 
nkeynes@359
   404
 */
nkeynes@590
   405
uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359
   406
{
nkeynes@388
   407
    uint32_t ir;
nkeynes@586
   408
    /* Read instruction from icache */
nkeynes@586
   409
    assert( IS_IN_ICACHE(pc) );
nkeynes@586
   410
    ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@586
   411
    
nkeynes@586
   412
    if( !sh4_x86.in_delay_slot ) {
nkeynes@596
   413
	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388
   414
    }
nkeynes@359
   415
%%
nkeynes@359
   416
/* ALU operations */
nkeynes@359
   417
ADD Rm, Rn {:
nkeynes@671
   418
    COUNT_INST(I_ADD);
nkeynes@359
   419
    load_reg( R_EAX, Rm );
nkeynes@359
   420
    load_reg( R_ECX, Rn );
nkeynes@359
   421
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   422
    store_reg( R_ECX, Rn );
nkeynes@417
   423
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   424
:}
nkeynes@359
   425
ADD #imm, Rn {:  
nkeynes@671
   426
    COUNT_INST(I_ADDI);
nkeynes@359
   427
    load_reg( R_EAX, Rn );
nkeynes@359
   428
    ADD_imm8s_r32( imm, R_EAX );
nkeynes@359
   429
    store_reg( R_EAX, Rn );
nkeynes@417
   430
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   431
:}
nkeynes@359
   432
ADDC Rm, Rn {:
nkeynes@671
   433
    COUNT_INST(I_ADDC);
nkeynes@417
   434
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911
   435
        LDC_t();
nkeynes@417
   436
    }
nkeynes@359
   437
    load_reg( R_EAX, Rm );
nkeynes@359
   438
    load_reg( R_ECX, Rn );
nkeynes@359
   439
    ADC_r32_r32( R_EAX, R_ECX );
nkeynes@359
   440
    store_reg( R_ECX, Rn );
nkeynes@359
   441
    SETC_t();
nkeynes@417
   442
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   443
:}
nkeynes@359
   444
ADDV Rm, Rn {:
nkeynes@671
   445
    COUNT_INST(I_ADDV);
nkeynes@359
   446
    load_reg( R_EAX, Rm );
nkeynes@359
   447
    load_reg( R_ECX, Rn );
nkeynes@359
   448
    ADD_r32_r32( R_EAX, R_ECX );
nkeynes@359
   449
    store_reg( R_ECX, Rn );
nkeynes@359
   450
    SETO_t();
nkeynes@417
   451
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
   452
:}
nkeynes@359
   453
AND Rm, Rn {:
nkeynes@671
   454
    COUNT_INST(I_AND);
nkeynes@359
   455
    load_reg( R_EAX, Rm );
nkeynes@359
   456
    load_reg( R_ECX, Rn );
nkeynes@359
   457
    AND_r32_r32( R_EAX, R_ECX );
nkeynes@359
   458
    store_reg( R_ECX, Rn );
nkeynes@417
   459
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   460
:}
nkeynes@359
   461
AND #imm, R0 {:  
nkeynes@671
   462
    COUNT_INST(I_ANDI);
nkeynes@359
   463
    load_reg( R_EAX, 0 );
nkeynes@359
   464
    AND_imm32_r32(imm, R_EAX); 
nkeynes@359
   465
    store_reg( R_EAX, 0 );
nkeynes@417
   466
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   467
:}
nkeynes@359
   468
AND.B #imm, @(R0, GBR) {: 
nkeynes@671
   469
    COUNT_INST(I_ANDB);
nkeynes@359
   470
    load_reg( R_EAX, 0 );
nkeynes@359
   471
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   472
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   473
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
   474
    MOV_r32_esp8(R_EAX, 0);
nkeynes@905
   475
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   476
    MOV_esp8_r32(0, R_EAX);
nkeynes@905
   477
    AND_imm32_r32(imm, R_EDX );
nkeynes@905
   478
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   479
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   480
:}
nkeynes@359
   481
CMP/EQ Rm, Rn {:  
nkeynes@671
   482
    COUNT_INST(I_CMPEQ);
nkeynes@359
   483
    load_reg( R_EAX, Rm );
nkeynes@359
   484
    load_reg( R_ECX, Rn );
nkeynes@359
   485
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   486
    SETE_t();
nkeynes@417
   487
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   488
:}
nkeynes@359
   489
CMP/EQ #imm, R0 {:  
nkeynes@671
   490
    COUNT_INST(I_CMPEQI);
nkeynes@359
   491
    load_reg( R_EAX, 0 );
nkeynes@359
   492
    CMP_imm8s_r32(imm, R_EAX);
nkeynes@359
   493
    SETE_t();
nkeynes@417
   494
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   495
:}
nkeynes@359
   496
CMP/GE Rm, Rn {:  
nkeynes@671
   497
    COUNT_INST(I_CMPGE);
nkeynes@359
   498
    load_reg( R_EAX, Rm );
nkeynes@359
   499
    load_reg( R_ECX, Rn );
nkeynes@359
   500
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   501
    SETGE_t();
nkeynes@417
   502
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   503
:}
nkeynes@359
   504
CMP/GT Rm, Rn {: 
nkeynes@671
   505
    COUNT_INST(I_CMPGT);
nkeynes@359
   506
    load_reg( R_EAX, Rm );
nkeynes@359
   507
    load_reg( R_ECX, Rn );
nkeynes@359
   508
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   509
    SETG_t();
nkeynes@417
   510
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   511
:}
nkeynes@359
   512
CMP/HI Rm, Rn {:  
nkeynes@671
   513
    COUNT_INST(I_CMPHI);
nkeynes@359
   514
    load_reg( R_EAX, Rm );
nkeynes@359
   515
    load_reg( R_ECX, Rn );
nkeynes@359
   516
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   517
    SETA_t();
nkeynes@417
   518
    sh4_x86.tstate = TSTATE_A;
nkeynes@359
   519
:}
nkeynes@359
   520
CMP/HS Rm, Rn {: 
nkeynes@671
   521
    COUNT_INST(I_CMPHS);
nkeynes@359
   522
    load_reg( R_EAX, Rm );
nkeynes@359
   523
    load_reg( R_ECX, Rn );
nkeynes@359
   524
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@359
   525
    SETAE_t();
nkeynes@417
   526
    sh4_x86.tstate = TSTATE_AE;
nkeynes@359
   527
 :}
nkeynes@359
   528
CMP/PL Rn {: 
nkeynes@671
   529
    COUNT_INST(I_CMPPL);
nkeynes@359
   530
    load_reg( R_EAX, Rn );
nkeynes@359
   531
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   532
    SETG_t();
nkeynes@417
   533
    sh4_x86.tstate = TSTATE_G;
nkeynes@359
   534
:}
nkeynes@359
   535
CMP/PZ Rn {:  
nkeynes@671
   536
    COUNT_INST(I_CMPPZ);
nkeynes@359
   537
    load_reg( R_EAX, Rn );
nkeynes@359
   538
    CMP_imm8s_r32( 0, R_EAX );
nkeynes@359
   539
    SETGE_t();
nkeynes@417
   540
    sh4_x86.tstate = TSTATE_GE;
nkeynes@359
   541
:}
nkeynes@361
   542
CMP/STR Rm, Rn {:  
nkeynes@671
   543
    COUNT_INST(I_CMPSTR);
nkeynes@368
   544
    load_reg( R_EAX, Rm );
nkeynes@368
   545
    load_reg( R_ECX, Rn );
nkeynes@368
   546
    XOR_r32_r32( R_ECX, R_EAX );
nkeynes@368
   547
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   548
    JE_rel8(target1);
nkeynes@669
   549
    TEST_r8_r8( R_AH, R_AH );
nkeynes@669
   550
    JE_rel8(target2);
nkeynes@669
   551
    SHR_imm8_r32( 16, R_EAX );
nkeynes@669
   552
    TEST_r8_r8( R_AL, R_AL );
nkeynes@669
   553
    JE_rel8(target3);
nkeynes@669
   554
    TEST_r8_r8( R_AH, R_AH );
nkeynes@380
   555
    JMP_TARGET(target1);
nkeynes@380
   556
    JMP_TARGET(target2);
nkeynes@380
   557
    JMP_TARGET(target3);
nkeynes@368
   558
    SETE_t();
nkeynes@417
   559
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
   560
:}
nkeynes@361
   561
DIV0S Rm, Rn {:
nkeynes@671
   562
    COUNT_INST(I_DIV0S);
nkeynes@361
   563
    load_reg( R_EAX, Rm );
nkeynes@386
   564
    load_reg( R_ECX, Rn );
nkeynes@361
   565
    SHR_imm8_r32( 31, R_EAX );
nkeynes@361
   566
    SHR_imm8_r32( 31, R_ECX );
nkeynes@361
   567
    store_spreg( R_EAX, R_M );
nkeynes@361
   568
    store_spreg( R_ECX, R_Q );
nkeynes@361
   569
    CMP_r32_r32( R_EAX, R_ECX );
nkeynes@386
   570
    SETNE_t();
nkeynes@417
   571
    sh4_x86.tstate = TSTATE_NE;
nkeynes@361
   572
:}
nkeynes@361
   573
DIV0U {:  
nkeynes@671
   574
    COUNT_INST(I_DIV0U);
nkeynes@361
   575
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@361
   576
    store_spreg( R_EAX, R_Q );
nkeynes@361
   577
    store_spreg( R_EAX, R_M );
nkeynes@361
   578
    store_spreg( R_EAX, R_T );
nkeynes@417
   579
    sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361
   580
:}
nkeynes@386
   581
DIV1 Rm, Rn {:
nkeynes@671
   582
    COUNT_INST(I_DIV1);
nkeynes@386
   583
    load_spreg( R_ECX, R_M );
nkeynes@386
   584
    load_reg( R_EAX, Rn );
nkeynes@417
   585
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   586
	LDC_t();
nkeynes@417
   587
    }
nkeynes@386
   588
    RCL1_r32( R_EAX );
nkeynes@386
   589
    SETC_r8( R_DL ); // Q'
nkeynes@386
   590
    CMP_sh4r_r32( R_Q, R_ECX );
nkeynes@669
   591
    JE_rel8(mqequal);
nkeynes@386
   592
    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@669
   593
    JMP_rel8(end);
nkeynes@380
   594
    JMP_TARGET(mqequal);
nkeynes@386
   595
    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
nkeynes@386
   596
    JMP_TARGET(end);
nkeynes@386
   597
    store_reg( R_EAX, Rn ); // Done with Rn now
nkeynes@386
   598
    SETC_r8(R_AL); // tmp1
nkeynes@386
   599
    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
nkeynes@386
   600
    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
nkeynes@386
   601
    store_spreg( R_ECX, R_Q );
nkeynes@386
   602
    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
nkeynes@386
   603
    MOVZX_r8_r32( R_AL, R_EAX );
nkeynes@386
   604
    store_spreg( R_EAX, R_T );
nkeynes@417
   605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   606
:}
nkeynes@361
   607
DMULS.L Rm, Rn {:  
nkeynes@671
   608
    COUNT_INST(I_DMULS);
nkeynes@361
   609
    load_reg( R_EAX, Rm );
nkeynes@361
   610
    load_reg( R_ECX, Rn );
nkeynes@361
   611
    IMUL_r32(R_ECX);
nkeynes@361
   612
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   613
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   614
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   615
:}
nkeynes@361
   616
DMULU.L Rm, Rn {:  
nkeynes@671
   617
    COUNT_INST(I_DMULU);
nkeynes@361
   618
    load_reg( R_EAX, Rm );
nkeynes@361
   619
    load_reg( R_ECX, Rn );
nkeynes@361
   620
    MUL_r32(R_ECX);
nkeynes@361
   621
    store_spreg( R_EDX, R_MACH );
nkeynes@361
   622
    store_spreg( R_EAX, R_MACL );    
nkeynes@417
   623
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   624
:}
nkeynes@359
   625
DT Rn {:  
nkeynes@671
   626
    COUNT_INST(I_DT);
nkeynes@359
   627
    load_reg( R_EAX, Rn );
nkeynes@382
   628
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@359
   629
    store_reg( R_EAX, Rn );
nkeynes@359
   630
    SETE_t();
nkeynes@417
   631
    sh4_x86.tstate = TSTATE_E;
nkeynes@359
   632
:}
nkeynes@359
   633
EXTS.B Rm, Rn {:  
nkeynes@671
   634
    COUNT_INST(I_EXTSB);
nkeynes@359
   635
    load_reg( R_EAX, Rm );
nkeynes@359
   636
    MOVSX_r8_r32( R_EAX, R_EAX );
nkeynes@359
   637
    store_reg( R_EAX, Rn );
nkeynes@359
   638
:}
nkeynes@361
   639
EXTS.W Rm, Rn {:  
nkeynes@671
   640
    COUNT_INST(I_EXTSW);
nkeynes@361
   641
    load_reg( R_EAX, Rm );
nkeynes@361
   642
    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   643
    store_reg( R_EAX, Rn );
nkeynes@361
   644
:}
nkeynes@361
   645
EXTU.B Rm, Rn {:  
nkeynes@671
   646
    COUNT_INST(I_EXTUB);
nkeynes@361
   647
    load_reg( R_EAX, Rm );
nkeynes@361
   648
    MOVZX_r8_r32( R_EAX, R_EAX );
nkeynes@361
   649
    store_reg( R_EAX, Rn );
nkeynes@361
   650
:}
nkeynes@361
   651
EXTU.W Rm, Rn {:  
nkeynes@671
   652
    COUNT_INST(I_EXTUW);
nkeynes@361
   653
    load_reg( R_EAX, Rm );
nkeynes@361
   654
    MOVZX_r16_r32( R_EAX, R_EAX );
nkeynes@361
   655
    store_reg( R_EAX, Rn );
nkeynes@361
   656
:}
nkeynes@586
   657
MAC.L @Rm+, @Rn+ {:
nkeynes@671
   658
    COUNT_INST(I_MACL);
nkeynes@586
   659
    if( Rm == Rn ) {
nkeynes@586
   660
	load_reg( R_EAX, Rm );
nkeynes@586
   661
	check_ralign32( R_EAX );
nkeynes@586
   662
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   663
	MOV_r32_esp8(R_EAX, 0);
nkeynes@586
   664
	load_reg( R_EAX, Rn );
nkeynes@586
   665
	ADD_imm8s_r32( 4, R_EAX );
nkeynes@926
   666
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   667
	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
nkeynes@586
   668
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   669
	// adding a page-boundary check to skip the second translation
nkeynes@586
   670
    } else {
nkeynes@586
   671
	load_reg( R_EAX, Rm );
nkeynes@586
   672
	check_ralign32( R_EAX );
nkeynes@586
   673
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   674
	MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   675
	load_reg( R_EAX, Rn );
nkeynes@926
   676
	check_ralign32( R_EAX );
nkeynes@926
   677
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   678
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   679
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
   680
    }
nkeynes@586
   681
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   682
    MOV_r32_esp8( R_EAX, 4 );
nkeynes@926
   683
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   684
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@926
   685
    MOV_esp8_r32( 4, R_ECX );
nkeynes@586
   686
nkeynes@386
   687
    IMUL_r32( R_ECX );
nkeynes@386
   688
    ADD_r32_sh4r( R_EAX, R_MACL );
nkeynes@386
   689
    ADC_r32_sh4r( R_EDX, R_MACH );
nkeynes@386
   690
nkeynes@386
   691
    load_spreg( R_ECX, R_S );
nkeynes@386
   692
    TEST_r32_r32(R_ECX, R_ECX);
nkeynes@669
   693
    JE_rel8( nosat );
nkeynes@386
   694
    call_func0( signsat48 );
nkeynes@386
   695
    JMP_TARGET( nosat );
nkeynes@417
   696
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   697
:}
nkeynes@386
   698
MAC.W @Rm+, @Rn+ {:  
nkeynes@671
   699
    COUNT_INST(I_MACW);
nkeynes@586
   700
    if( Rm == Rn ) {
nkeynes@586
   701
	load_reg( R_EAX, Rm );
nkeynes@586
   702
	check_ralign16( R_EAX );
nkeynes@586
   703
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   704
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@586
   705
	load_reg( R_EAX, Rn );
nkeynes@586
   706
	ADD_imm8s_r32( 2, R_EAX );
nkeynes@926
   707
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   708
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
nkeynes@586
   709
	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@586
   710
	// adding a page-boundary check to skip the second translation
nkeynes@586
   711
    } else {
nkeynes@586
   712
	load_reg( R_EAX, Rm );
nkeynes@586
   713
	check_ralign16( R_EAX );
nkeynes@586
   714
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@926
   715
        MOV_r32_esp8( R_EAX, 0 );
nkeynes@926
   716
	load_reg( R_EAX, Rn );
nkeynes@926
   717
	check_ralign16( R_EAX );
nkeynes@926
   718
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
   719
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
nkeynes@586
   720
	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
   721
    }
nkeynes@586
   722
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   723
    MOV_r32_esp8( R_EAX, 4 );
nkeynes@926
   724
    MOV_esp8_r32( 0, R_EAX );
nkeynes@926
   725
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@926
   726
    MOV_esp8_r32( 4, R_ECX );
nkeynes@926
   727
nkeynes@386
   728
    IMUL_r32( R_ECX );
nkeynes@386
   729
    load_spreg( R_ECX, R_S );
nkeynes@386
   730
    TEST_r32_r32( R_ECX, R_ECX );
nkeynes@669
   731
    JE_rel8( nosat );
nkeynes@386
   732
nkeynes@386
   733
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@669
   734
    JNO_rel8( end );            // 2
nkeynes@386
   735
    load_imm32( R_EDX, 1 );         // 5
nkeynes@386
   736
    store_spreg( R_EDX, R_MACH );   // 6
nkeynes@669
   737
    JS_rel8( positive );        // 2
nkeynes@386
   738
    load_imm32( R_EAX, 0x80000000 );// 5
nkeynes@386
   739
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   740
    JMP_rel8(end2);           // 2
nkeynes@386
   741
nkeynes@386
   742
    JMP_TARGET(positive);
nkeynes@386
   743
    load_imm32( R_EAX, 0x7FFFFFFF );// 5
nkeynes@386
   744
    store_spreg( R_EAX, R_MACL );   // 6
nkeynes@669
   745
    JMP_rel8(end3);            // 2
nkeynes@386
   746
nkeynes@386
   747
    JMP_TARGET(nosat);
nkeynes@386
   748
    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
nkeynes@386
   749
    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
nkeynes@386
   750
    JMP_TARGET(end);
nkeynes@386
   751
    JMP_TARGET(end2);
nkeynes@386
   752
    JMP_TARGET(end3);
nkeynes@417
   753
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
   754
:}
nkeynes@359
   755
MOVT Rn {:  
nkeynes@671
   756
    COUNT_INST(I_MOVT);
nkeynes@359
   757
    load_spreg( R_EAX, R_T );
nkeynes@359
   758
    store_reg( R_EAX, Rn );
nkeynes@359
   759
:}
nkeynes@361
   760
MUL.L Rm, Rn {:  
nkeynes@671
   761
    COUNT_INST(I_MULL);
nkeynes@361
   762
    load_reg( R_EAX, Rm );
nkeynes@361
   763
    load_reg( R_ECX, Rn );
nkeynes@361
   764
    MUL_r32( R_ECX );
nkeynes@361
   765
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   766
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   767
:}
nkeynes@374
   768
MULS.W Rm, Rn {:
nkeynes@671
   769
    COUNT_INST(I_MULSW);
nkeynes@374
   770
    load_reg16s( R_EAX, Rm );
nkeynes@374
   771
    load_reg16s( R_ECX, Rn );
nkeynes@374
   772
    MUL_r32( R_ECX );
nkeynes@374
   773
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   774
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
   775
:}
nkeynes@374
   776
MULU.W Rm, Rn {:  
nkeynes@671
   777
    COUNT_INST(I_MULUW);
nkeynes@374
   778
    load_reg16u( R_EAX, Rm );
nkeynes@374
   779
    load_reg16u( R_ECX, Rn );
nkeynes@374
   780
    MUL_r32( R_ECX );
nkeynes@374
   781
    store_spreg( R_EAX, R_MACL );
nkeynes@417
   782
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   783
:}
nkeynes@359
   784
NEG Rm, Rn {:
nkeynes@671
   785
    COUNT_INST(I_NEG);
nkeynes@359
   786
    load_reg( R_EAX, Rm );
nkeynes@359
   787
    NEG_r32( R_EAX );
nkeynes@359
   788
    store_reg( R_EAX, Rn );
nkeynes@417
   789
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   790
:}
nkeynes@359
   791
NEGC Rm, Rn {:  
nkeynes@671
   792
    COUNT_INST(I_NEGC);
nkeynes@359
   793
    load_reg( R_EAX, Rm );
nkeynes@359
   794
    XOR_r32_r32( R_ECX, R_ECX );
nkeynes@359
   795
    LDC_t();
nkeynes@359
   796
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
   797
    store_reg( R_ECX, Rn );
nkeynes@359
   798
    SETC_t();
nkeynes@417
   799
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   800
:}
nkeynes@359
   801
NOT Rm, Rn {:  
nkeynes@671
   802
    COUNT_INST(I_NOT);
nkeynes@359
   803
    load_reg( R_EAX, Rm );
nkeynes@359
   804
    NOT_r32( R_EAX );
nkeynes@359
   805
    store_reg( R_EAX, Rn );
nkeynes@417
   806
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   807
:}
nkeynes@359
   808
OR Rm, Rn {:  
nkeynes@671
   809
    COUNT_INST(I_OR);
nkeynes@359
   810
    load_reg( R_EAX, Rm );
nkeynes@359
   811
    load_reg( R_ECX, Rn );
nkeynes@359
   812
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
   813
    store_reg( R_ECX, Rn );
nkeynes@417
   814
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   815
:}
nkeynes@359
   816
OR #imm, R0 {:
nkeynes@671
   817
    COUNT_INST(I_ORI);
nkeynes@359
   818
    load_reg( R_EAX, 0 );
nkeynes@359
   819
    OR_imm32_r32(imm, R_EAX);
nkeynes@359
   820
    store_reg( R_EAX, 0 );
nkeynes@417
   821
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   822
:}
nkeynes@374
   823
OR.B #imm, @(R0, GBR) {:  
nkeynes@671
   824
    COUNT_INST(I_ORB);
nkeynes@374
   825
    load_reg( R_EAX, 0 );
nkeynes@374
   826
    load_spreg( R_ECX, R_GBR );
nkeynes@586
   827
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
   828
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
   829
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
   830
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@926
   831
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
   832
    OR_imm32_r32(imm, R_EDX );
nkeynes@905
   833
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
   834
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
   835
:}
nkeynes@359
   836
ROTCL Rn {:
nkeynes@671
   837
    COUNT_INST(I_ROTCL);
nkeynes@359
   838
    load_reg( R_EAX, Rn );
nkeynes@417
   839
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   840
	LDC_t();
nkeynes@417
   841
    }
nkeynes@359
   842
    RCL1_r32( R_EAX );
nkeynes@359
   843
    store_reg( R_EAX, Rn );
nkeynes@359
   844
    SETC_t();
nkeynes@417
   845
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   846
:}
nkeynes@359
   847
ROTCR Rn {:  
nkeynes@671
   848
    COUNT_INST(I_ROTCR);
nkeynes@359
   849
    load_reg( R_EAX, Rn );
nkeynes@417
   850
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
   851
	LDC_t();
nkeynes@417
   852
    }
nkeynes@359
   853
    RCR1_r32( R_EAX );
nkeynes@359
   854
    store_reg( R_EAX, Rn );
nkeynes@359
   855
    SETC_t();
nkeynes@417
   856
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   857
:}
nkeynes@359
   858
ROTL Rn {:  
nkeynes@671
   859
    COUNT_INST(I_ROTL);
nkeynes@359
   860
    load_reg( R_EAX, Rn );
nkeynes@359
   861
    ROL1_r32( R_EAX );
nkeynes@359
   862
    store_reg( R_EAX, Rn );
nkeynes@359
   863
    SETC_t();
nkeynes@417
   864
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   865
:}
nkeynes@359
   866
ROTR Rn {:  
nkeynes@671
   867
    COUNT_INST(I_ROTR);
nkeynes@359
   868
    load_reg( R_EAX, Rn );
nkeynes@359
   869
    ROR1_r32( R_EAX );
nkeynes@359
   870
    store_reg( R_EAX, Rn );
nkeynes@359
   871
    SETC_t();
nkeynes@417
   872
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   873
:}
nkeynes@359
   874
SHAD Rm, Rn {:
nkeynes@671
   875
    COUNT_INST(I_SHAD);
nkeynes@359
   876
    /* Annoyingly enough, not directly convertible */
nkeynes@361
   877
    load_reg( R_EAX, Rn );
nkeynes@361
   878
    load_reg( R_ECX, Rm );
nkeynes@361
   879
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   880
    JGE_rel8(doshl);
nkeynes@361
   881
                    
nkeynes@361
   882
    NEG_r32( R_ECX );      // 2
nkeynes@361
   883
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   884
    JE_rel8(emptysar);     // 2
nkeynes@361
   885
    SAR_r32_CL( R_EAX );       // 2
nkeynes@669
   886
    JMP_rel8(end);          // 2
nkeynes@386
   887
nkeynes@386
   888
    JMP_TARGET(emptysar);
nkeynes@386
   889
    SAR_imm8_r32(31, R_EAX );  // 3
nkeynes@669
   890
    JMP_rel8(end2);
nkeynes@382
   891
nkeynes@380
   892
    JMP_TARGET(doshl);
nkeynes@361
   893
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@361
   894
    SHL_r32_CL( R_EAX );       // 2
nkeynes@380
   895
    JMP_TARGET(end);
nkeynes@386
   896
    JMP_TARGET(end2);
nkeynes@361
   897
    store_reg( R_EAX, Rn );
nkeynes@417
   898
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   899
:}
nkeynes@359
   900
SHLD Rm, Rn {:  
nkeynes@671
   901
    COUNT_INST(I_SHLD);
nkeynes@368
   902
    load_reg( R_EAX, Rn );
nkeynes@368
   903
    load_reg( R_ECX, Rm );
nkeynes@382
   904
    CMP_imm32_r32( 0, R_ECX );
nkeynes@669
   905
    JGE_rel8(doshl);
nkeynes@368
   906
nkeynes@382
   907
    NEG_r32( R_ECX );      // 2
nkeynes@382
   908
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@669
   909
    JE_rel8(emptyshr );
nkeynes@382
   910
    SHR_r32_CL( R_EAX );       // 2
nkeynes@669
   911
    JMP_rel8(end);          // 2
nkeynes@386
   912
nkeynes@386
   913
    JMP_TARGET(emptyshr);
nkeynes@386
   914
    XOR_r32_r32( R_EAX, R_EAX );
nkeynes@669
   915
    JMP_rel8(end2);
nkeynes@382
   916
nkeynes@382
   917
    JMP_TARGET(doshl);
nkeynes@382
   918
    AND_imm8_r8( 0x1F, R_CL ); // 3
nkeynes@382
   919
    SHL_r32_CL( R_EAX );       // 2
nkeynes@382
   920
    JMP_TARGET(end);
nkeynes@386
   921
    JMP_TARGET(end2);
nkeynes@368
   922
    store_reg( R_EAX, Rn );
nkeynes@417
   923
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   924
:}
nkeynes@359
   925
SHAL Rn {: 
nkeynes@671
   926
    COUNT_INST(I_SHAL);
nkeynes@359
   927
    load_reg( R_EAX, Rn );
nkeynes@359
   928
    SHL1_r32( R_EAX );
nkeynes@397
   929
    SETC_t();
nkeynes@359
   930
    store_reg( R_EAX, Rn );
nkeynes@417
   931
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   932
:}
nkeynes@359
   933
SHAR Rn {:  
nkeynes@671
   934
    COUNT_INST(I_SHAR);
nkeynes@359
   935
    load_reg( R_EAX, Rn );
nkeynes@359
   936
    SAR1_r32( R_EAX );
nkeynes@397
   937
    SETC_t();
nkeynes@359
   938
    store_reg( R_EAX, Rn );
nkeynes@417
   939
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   940
:}
nkeynes@359
   941
SHLL Rn {:  
nkeynes@671
   942
    COUNT_INST(I_SHLL);
nkeynes@359
   943
    load_reg( R_EAX, Rn );
nkeynes@359
   944
    SHL1_r32( R_EAX );
nkeynes@397
   945
    SETC_t();
nkeynes@359
   946
    store_reg( R_EAX, Rn );
nkeynes@417
   947
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   948
:}
nkeynes@359
   949
SHLL2 Rn {:
nkeynes@671
   950
    COUNT_INST(I_SHLL);
nkeynes@359
   951
    load_reg( R_EAX, Rn );
nkeynes@359
   952
    SHL_imm8_r32( 2, R_EAX );
nkeynes@359
   953
    store_reg( R_EAX, Rn );
nkeynes@417
   954
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   955
:}
nkeynes@359
   956
SHLL8 Rn {:  
nkeynes@671
   957
    COUNT_INST(I_SHLL);
nkeynes@359
   958
    load_reg( R_EAX, Rn );
nkeynes@359
   959
    SHL_imm8_r32( 8, R_EAX );
nkeynes@359
   960
    store_reg( R_EAX, Rn );
nkeynes@417
   961
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   962
:}
nkeynes@359
   963
SHLL16 Rn {:  
nkeynes@671
   964
    COUNT_INST(I_SHLL);
nkeynes@359
   965
    load_reg( R_EAX, Rn );
nkeynes@359
   966
    SHL_imm8_r32( 16, R_EAX );
nkeynes@359
   967
    store_reg( R_EAX, Rn );
nkeynes@417
   968
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   969
:}
nkeynes@359
   970
SHLR Rn {:  
nkeynes@671
   971
    COUNT_INST(I_SHLR);
nkeynes@359
   972
    load_reg( R_EAX, Rn );
nkeynes@359
   973
    SHR1_r32( R_EAX );
nkeynes@397
   974
    SETC_t();
nkeynes@359
   975
    store_reg( R_EAX, Rn );
nkeynes@417
   976
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
   977
:}
nkeynes@359
   978
SHLR2 Rn {:  
nkeynes@671
   979
    COUNT_INST(I_SHLR);
nkeynes@359
   980
    load_reg( R_EAX, Rn );
nkeynes@359
   981
    SHR_imm8_r32( 2, R_EAX );
nkeynes@359
   982
    store_reg( R_EAX, Rn );
nkeynes@417
   983
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   984
:}
nkeynes@359
   985
SHLR8 Rn {:  
nkeynes@671
   986
    COUNT_INST(I_SHLR);
nkeynes@359
   987
    load_reg( R_EAX, Rn );
nkeynes@359
   988
    SHR_imm8_r32( 8, R_EAX );
nkeynes@359
   989
    store_reg( R_EAX, Rn );
nkeynes@417
   990
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   991
:}
nkeynes@359
   992
SHLR16 Rn {:  
nkeynes@671
   993
    COUNT_INST(I_SHLR);
nkeynes@359
   994
    load_reg( R_EAX, Rn );
nkeynes@359
   995
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
   996
    store_reg( R_EAX, Rn );
nkeynes@417
   997
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
   998
:}
nkeynes@359
   999
SUB Rm, Rn {:  
nkeynes@671
  1000
    COUNT_INST(I_SUB);
nkeynes@359
  1001
    load_reg( R_EAX, Rm );
nkeynes@359
  1002
    load_reg( R_ECX, Rn );
nkeynes@359
  1003
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1004
    store_reg( R_ECX, Rn );
nkeynes@417
  1005
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1006
:}
nkeynes@359
  1007
SUBC Rm, Rn {:  
nkeynes@671
  1008
    COUNT_INST(I_SUBC);
nkeynes@359
  1009
    load_reg( R_EAX, Rm );
nkeynes@359
  1010
    load_reg( R_ECX, Rn );
nkeynes@417
  1011
    if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417
  1012
	LDC_t();
nkeynes@417
  1013
    }
nkeynes@359
  1014
    SBB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1015
    store_reg( R_ECX, Rn );
nkeynes@394
  1016
    SETC_t();
nkeynes@417
  1017
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1018
:}
nkeynes@359
  1019
SUBV Rm, Rn {:  
nkeynes@671
  1020
    COUNT_INST(I_SUBV);
nkeynes@359
  1021
    load_reg( R_EAX, Rm );
nkeynes@359
  1022
    load_reg( R_ECX, Rn );
nkeynes@359
  1023
    SUB_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1024
    store_reg( R_ECX, Rn );
nkeynes@359
  1025
    SETO_t();
nkeynes@417
  1026
    sh4_x86.tstate = TSTATE_O;
nkeynes@359
  1027
:}
nkeynes@359
  1028
SWAP.B Rm, Rn {:  
nkeynes@671
  1029
    COUNT_INST(I_SWAPB);
nkeynes@359
  1030
    load_reg( R_EAX, Rm );
nkeynes@601
  1031
    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
nkeynes@359
  1032
    store_reg( R_EAX, Rn );
nkeynes@359
  1033
:}
nkeynes@359
  1034
SWAP.W Rm, Rn {:  
nkeynes@671
  1035
    COUNT_INST(I_SWAPB);
nkeynes@359
  1036
    load_reg( R_EAX, Rm );
nkeynes@359
  1037
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1038
    SHL_imm8_r32( 16, R_ECX );
nkeynes@359
  1039
    SHR_imm8_r32( 16, R_EAX );
nkeynes@359
  1040
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1041
    store_reg( R_ECX, Rn );
nkeynes@417
  1042
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1043
:}
nkeynes@361
  1044
TAS.B @Rn {:  
nkeynes@671
  1045
    COUNT_INST(I_TASB);
nkeynes@586
  1046
    load_reg( R_EAX, Rn );
nkeynes@586
  1047
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  1048
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1049
    MEM_READ_BYTE( R_EAX, R_EDX );
nkeynes@905
  1050
    TEST_r8_r8( R_DL, R_DL );
nkeynes@361
  1051
    SETE_t();
nkeynes@905
  1052
    OR_imm8_r8( 0x80, R_DL );
nkeynes@926
  1053
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1054
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1055
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1056
:}
nkeynes@361
  1057
TST Rm, Rn {:  
nkeynes@671
  1058
    COUNT_INST(I_TST);
nkeynes@361
  1059
    load_reg( R_EAX, Rm );
nkeynes@361
  1060
    load_reg( R_ECX, Rn );
nkeynes@361
  1061
    TEST_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1062
    SETE_t();
nkeynes@417
  1063
    sh4_x86.tstate = TSTATE_E;
nkeynes@361
  1064
:}
nkeynes@368
  1065
TST #imm, R0 {:  
nkeynes@671
  1066
    COUNT_INST(I_TSTI);
nkeynes@368
  1067
    load_reg( R_EAX, 0 );
nkeynes@368
  1068
    TEST_imm32_r32( imm, R_EAX );
nkeynes@368
  1069
    SETE_t();
nkeynes@417
  1070
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1071
:}
nkeynes@368
  1072
TST.B #imm, @(R0, GBR) {:  
nkeynes@671
  1073
    COUNT_INST(I_TSTB);
nkeynes@368
  1074
    load_reg( R_EAX, 0);
nkeynes@368
  1075
    load_reg( R_ECX, R_GBR);
nkeynes@586
  1076
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1077
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1078
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@394
  1079
    TEST_imm8_r8( imm, R_AL );
nkeynes@368
  1080
    SETE_t();
nkeynes@417
  1081
    sh4_x86.tstate = TSTATE_E;
nkeynes@368
  1082
:}
nkeynes@359
  1083
XOR Rm, Rn {:  
nkeynes@671
  1084
    COUNT_INST(I_XOR);
nkeynes@359
  1085
    load_reg( R_EAX, Rm );
nkeynes@359
  1086
    load_reg( R_ECX, Rn );
nkeynes@359
  1087
    XOR_r32_r32( R_EAX, R_ECX );
nkeynes@359
  1088
    store_reg( R_ECX, Rn );
nkeynes@417
  1089
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1090
:}
nkeynes@359
  1091
XOR #imm, R0 {:  
nkeynes@671
  1092
    COUNT_INST(I_XORI);
nkeynes@359
  1093
    load_reg( R_EAX, 0 );
nkeynes@359
  1094
    XOR_imm32_r32( imm, R_EAX );
nkeynes@359
  1095
    store_reg( R_EAX, 0 );
nkeynes@417
  1096
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1097
:}
nkeynes@359
  1098
XOR.B #imm, @(R0, GBR) {:  
nkeynes@671
  1099
    COUNT_INST(I_XORB);
nkeynes@359
  1100
    load_reg( R_EAX, 0 );
nkeynes@359
  1101
    load_spreg( R_ECX, R_GBR );
nkeynes@586
  1102
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1103
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  1104
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@905
  1105
    MEM_READ_BYTE(R_EAX, R_EDX);
nkeynes@926
  1106
    MOV_esp8_r32( 0, R_EAX );
nkeynes@905
  1107
    XOR_imm32_r32( imm, R_EDX );
nkeynes@905
  1108
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1109
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1110
:}
nkeynes@361
  1111
XTRCT Rm, Rn {:
nkeynes@671
  1112
    COUNT_INST(I_XTRCT);
nkeynes@361
  1113
    load_reg( R_EAX, Rm );
nkeynes@394
  1114
    load_reg( R_ECX, Rn );
nkeynes@394
  1115
    SHL_imm8_r32( 16, R_EAX );
nkeynes@394
  1116
    SHR_imm8_r32( 16, R_ECX );
nkeynes@361
  1117
    OR_r32_r32( R_EAX, R_ECX );
nkeynes@361
  1118
    store_reg( R_ECX, Rn );
nkeynes@417
  1119
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1120
:}
nkeynes@359
  1121
nkeynes@359
  1122
/* Data move instructions */
nkeynes@359
  1123
MOV Rm, Rn {:  
nkeynes@671
  1124
    COUNT_INST(I_MOV);
nkeynes@359
  1125
    load_reg( R_EAX, Rm );
nkeynes@359
  1126
    store_reg( R_EAX, Rn );
nkeynes@359
  1127
:}
nkeynes@359
  1128
MOV #imm, Rn {:  
nkeynes@671
  1129
    COUNT_INST(I_MOVI);
nkeynes@359
  1130
    load_imm32( R_EAX, imm );
nkeynes@359
  1131
    store_reg( R_EAX, Rn );
nkeynes@359
  1132
:}
nkeynes@359
  1133
MOV.B Rm, @Rn {:  
nkeynes@671
  1134
    COUNT_INST(I_MOVB);
nkeynes@586
  1135
    load_reg( R_EAX, Rn );
nkeynes@586
  1136
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1137
    load_reg( R_EDX, Rm );
nkeynes@586
  1138
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1139
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1140
:}
nkeynes@359
  1141
MOV.B Rm, @-Rn {:  
nkeynes@671
  1142
    COUNT_INST(I_MOVB);
nkeynes@586
  1143
    load_reg( R_EAX, Rn );
nkeynes@586
  1144
    ADD_imm8s_r32( -1, R_EAX );
nkeynes@586
  1145
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1146
    load_reg( R_EDX, Rm );
nkeynes@586
  1147
    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
nkeynes@586
  1148
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1149
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1150
:}
nkeynes@359
  1151
MOV.B Rm, @(R0, Rn) {:  
nkeynes@671
  1152
    COUNT_INST(I_MOVB);
nkeynes@359
  1153
    load_reg( R_EAX, 0 );
nkeynes@359
  1154
    load_reg( R_ECX, Rn );
nkeynes@586
  1155
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1156
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1157
    load_reg( R_EDX, Rm );
nkeynes@586
  1158
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1159
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1160
:}
nkeynes@359
  1161
MOV.B R0, @(disp, GBR) {:  
nkeynes@671
  1162
    COUNT_INST(I_MOVB);
nkeynes@586
  1163
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1164
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1165
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1166
    load_reg( R_EDX, 0 );
nkeynes@586
  1167
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1168
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1169
:}
nkeynes@359
  1170
MOV.B R0, @(disp, Rn) {:  
nkeynes@671
  1171
    COUNT_INST(I_MOVB);
nkeynes@586
  1172
    load_reg( R_EAX, Rn );
nkeynes@586
  1173
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1174
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1175
    load_reg( R_EDX, 0 );
nkeynes@586
  1176
    MEM_WRITE_BYTE( R_EAX, R_EDX );
nkeynes@417
  1177
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1178
:}
nkeynes@359
  1179
MOV.B @Rm, Rn {:  
nkeynes@671
  1180
    COUNT_INST(I_MOVB);
nkeynes@586
  1181
    load_reg( R_EAX, Rm );
nkeynes@586
  1182
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1183
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@386
  1184
    store_reg( R_EAX, Rn );
nkeynes@417
  1185
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1186
:}
nkeynes@359
  1187
MOV.B @Rm+, Rn {:  
nkeynes@671
  1188
    COUNT_INST(I_MOVB);
nkeynes@586
  1189
    load_reg( R_EAX, Rm );
nkeynes@586
  1190
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1191
    ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
nkeynes@586
  1192
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1193
    store_reg( R_EAX, Rn );
nkeynes@417
  1194
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1195
:}
nkeynes@359
  1196
MOV.B @(R0, Rm), Rn {:  
nkeynes@671
  1197
    COUNT_INST(I_MOVB);
nkeynes@359
  1198
    load_reg( R_EAX, 0 );
nkeynes@359
  1199
    load_reg( R_ECX, Rm );
nkeynes@586
  1200
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1201
    MMU_TRANSLATE_READ( R_EAX )
nkeynes@586
  1202
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1203
    store_reg( R_EAX, Rn );
nkeynes@417
  1204
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1205
:}
nkeynes@359
  1206
MOV.B @(disp, GBR), R0 {:  
nkeynes@671
  1207
    COUNT_INST(I_MOVB);
nkeynes@586
  1208
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1209
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1210
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1211
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1212
    store_reg( R_EAX, 0 );
nkeynes@417
  1213
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1214
:}
nkeynes@359
  1215
MOV.B @(disp, Rm), R0 {:  
nkeynes@671
  1216
    COUNT_INST(I_MOVB);
nkeynes@586
  1217
    load_reg( R_EAX, Rm );
nkeynes@586
  1218
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1219
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1220
    MEM_READ_BYTE( R_EAX, R_EAX );
nkeynes@359
  1221
    store_reg( R_EAX, 0 );
nkeynes@417
  1222
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1223
:}
nkeynes@374
  1224
MOV.L Rm, @Rn {:
nkeynes@671
  1225
    COUNT_INST(I_MOVL);
nkeynes@586
  1226
    load_reg( R_EAX, Rn );
nkeynes@586
  1227
    check_walign32(R_EAX);
nkeynes@586
  1228
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1229
    load_reg( R_EDX, Rm );
nkeynes@586
  1230
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1231
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1232
:}
nkeynes@361
  1233
MOV.L Rm, @-Rn {:  
nkeynes@671
  1234
    COUNT_INST(I_MOVL);
nkeynes@586
  1235
    load_reg( R_EAX, Rn );
nkeynes@586
  1236
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  1237
    check_walign32( R_EAX );
nkeynes@586
  1238
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1239
    load_reg( R_EDX, Rm );
nkeynes@586
  1240
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  1241
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1242
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1243
:}
nkeynes@361
  1244
MOV.L Rm, @(R0, Rn) {:  
nkeynes@671
  1245
    COUNT_INST(I_MOVL);
nkeynes@361
  1246
    load_reg( R_EAX, 0 );
nkeynes@361
  1247
    load_reg( R_ECX, Rn );
nkeynes@586
  1248
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1249
    check_walign32( R_EAX );
nkeynes@586
  1250
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1251
    load_reg( R_EDX, Rm );
nkeynes@586
  1252
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1253
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1254
:}
nkeynes@361
  1255
MOV.L R0, @(disp, GBR) {:  
nkeynes@671
  1256
    COUNT_INST(I_MOVL);
nkeynes@586
  1257
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1258
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1259
    check_walign32( R_EAX );
nkeynes@586
  1260
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1261
    load_reg( R_EDX, 0 );
nkeynes@586
  1262
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1263
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1264
:}
nkeynes@361
  1265
MOV.L Rm, @(disp, Rn) {:  
nkeynes@671
  1266
    COUNT_INST(I_MOVL);
nkeynes@586
  1267
    load_reg( R_EAX, Rn );
nkeynes@586
  1268
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1269
    check_walign32( R_EAX );
nkeynes@586
  1270
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1271
    load_reg( R_EDX, Rm );
nkeynes@586
  1272
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1273
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1274
:}
nkeynes@361
  1275
MOV.L @Rm, Rn {:  
nkeynes@671
  1276
    COUNT_INST(I_MOVL);
nkeynes@586
  1277
    load_reg( R_EAX, Rm );
nkeynes@586
  1278
    check_ralign32( R_EAX );
nkeynes@586
  1279
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1280
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1281
    store_reg( R_EAX, Rn );
nkeynes@417
  1282
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1283
:}
nkeynes@361
  1284
MOV.L @Rm+, Rn {:  
nkeynes@671
  1285
    COUNT_INST(I_MOVL);
nkeynes@361
  1286
    load_reg( R_EAX, Rm );
nkeynes@382
  1287
    check_ralign32( R_EAX );
nkeynes@586
  1288
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1289
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  1290
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1291
    store_reg( R_EAX, Rn );
nkeynes@417
  1292
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1293
:}
nkeynes@361
  1294
MOV.L @(R0, Rm), Rn {:  
nkeynes@671
  1295
    COUNT_INST(I_MOVL);
nkeynes@361
  1296
    load_reg( R_EAX, 0 );
nkeynes@361
  1297
    load_reg( R_ECX, Rm );
nkeynes@586
  1298
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1299
    check_ralign32( R_EAX );
nkeynes@586
  1300
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1301
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1302
    store_reg( R_EAX, Rn );
nkeynes@417
  1303
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1304
:}
nkeynes@361
  1305
MOV.L @(disp, GBR), R0 {:
nkeynes@671
  1306
    COUNT_INST(I_MOVL);
nkeynes@586
  1307
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1308
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1309
    check_ralign32( R_EAX );
nkeynes@586
  1310
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1311
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1312
    store_reg( R_EAX, 0 );
nkeynes@417
  1313
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1314
:}
nkeynes@361
  1315
MOV.L @(disp, PC), Rn {:  
nkeynes@671
  1316
    COUNT_INST(I_MOVLPC);
nkeynes@374
  1317
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1318
	SLOTILLEGAL();
nkeynes@374
  1319
    } else {
nkeynes@388
  1320
	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@586
  1321
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1322
	    // If the target address is in the same page as the code, it's
nkeynes@586
  1323
	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@586
  1324
	    // memory subsystem. (this is a big performance win)
nkeynes@586
  1325
nkeynes@586
  1326
	    // FIXME: There's a corner-case that's not handled here when
nkeynes@586
  1327
	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@586
  1328
	    // (should generate a TLB miss although need to test SH4 
nkeynes@586
  1329
	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@586
  1330
	    // behaviour though.
nkeynes@586
  1331
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@527
  1332
	    MOV_moff32_EAX( ptr );
nkeynes@388
  1333
	} else {
nkeynes@586
  1334
	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@586
  1335
	    // different virtual address than the translation was done with,
nkeynes@586
  1336
	    // but we can safely assume that the low bits are the same.
nkeynes@586
  1337
	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1338
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1339
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1340
	    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@586
  1341
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388
  1342
	}
nkeynes@382
  1343
	store_reg( R_EAX, Rn );
nkeynes@374
  1344
    }
nkeynes@361
  1345
:}
nkeynes@361
  1346
MOV.L @(disp, Rm), Rn {:  
nkeynes@671
  1347
    COUNT_INST(I_MOVL);
nkeynes@586
  1348
    load_reg( R_EAX, Rm );
nkeynes@586
  1349
    ADD_imm8s_r32( disp, R_EAX );
nkeynes@586
  1350
    check_ralign32( R_EAX );
nkeynes@586
  1351
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1352
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@361
  1353
    store_reg( R_EAX, Rn );
nkeynes@417
  1354
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1355
:}
nkeynes@361
  1356
MOV.W Rm, @Rn {:  
nkeynes@671
  1357
    COUNT_INST(I_MOVW);
nkeynes@586
  1358
    load_reg( R_EAX, Rn );
nkeynes@586
  1359
    check_walign16( R_EAX );
nkeynes@586
  1360
    MMU_TRANSLATE_WRITE( R_EAX )
nkeynes@586
  1361
    load_reg( R_EDX, Rm );
nkeynes@586
  1362
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1363
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1364
:}
nkeynes@361
  1365
MOV.W Rm, @-Rn {:  
nkeynes@671
  1366
    COUNT_INST(I_MOVW);
nkeynes@586
  1367
    load_reg( R_EAX, Rn );
nkeynes@586
  1368
    ADD_imm8s_r32( -2, R_EAX );
nkeynes@586
  1369
    check_walign16( R_EAX );
nkeynes@586
  1370
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1371
    load_reg( R_EDX, Rm );
nkeynes@586
  1372
    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
nkeynes@586
  1373
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1374
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1375
:}
nkeynes@361
  1376
MOV.W Rm, @(R0, Rn) {:  
nkeynes@671
  1377
    COUNT_INST(I_MOVW);
nkeynes@361
  1378
    load_reg( R_EAX, 0 );
nkeynes@361
  1379
    load_reg( R_ECX, Rn );
nkeynes@586
  1380
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1381
    check_walign16( R_EAX );
nkeynes@586
  1382
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1383
    load_reg( R_EDX, Rm );
nkeynes@586
  1384
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1385
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1386
:}
nkeynes@361
  1387
MOV.W R0, @(disp, GBR) {:  
nkeynes@671
  1388
    COUNT_INST(I_MOVW);
nkeynes@586
  1389
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1390
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1391
    check_walign16( R_EAX );
nkeynes@586
  1392
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1393
    load_reg( R_EDX, 0 );
nkeynes@586
  1394
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1395
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1396
:}
nkeynes@361
  1397
MOV.W R0, @(disp, Rn) {:  
nkeynes@671
  1398
    COUNT_INST(I_MOVW);
nkeynes@586
  1399
    load_reg( R_EAX, Rn );
nkeynes@586
  1400
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1401
    check_walign16( R_EAX );
nkeynes@586
  1402
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1403
    load_reg( R_EDX, 0 );
nkeynes@586
  1404
    MEM_WRITE_WORD( R_EAX, R_EDX );
nkeynes@417
  1405
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1406
:}
nkeynes@361
  1407
MOV.W @Rm, Rn {:  
nkeynes@671
  1408
    COUNT_INST(I_MOVW);
nkeynes@586
  1409
    load_reg( R_EAX, Rm );
nkeynes@586
  1410
    check_ralign16( R_EAX );
nkeynes@586
  1411
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1412
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1413
    store_reg( R_EAX, Rn );
nkeynes@417
  1414
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1415
:}
nkeynes@361
  1416
MOV.W @Rm+, Rn {:  
nkeynes@671
  1417
    COUNT_INST(I_MOVW);
nkeynes@361
  1418
    load_reg( R_EAX, Rm );
nkeynes@374
  1419
    check_ralign16( R_EAX );
nkeynes@586
  1420
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1421
    ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
nkeynes@586
  1422
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1423
    store_reg( R_EAX, Rn );
nkeynes@417
  1424
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1425
:}
nkeynes@361
  1426
MOV.W @(R0, Rm), Rn {:  
nkeynes@671
  1427
    COUNT_INST(I_MOVW);
nkeynes@361
  1428
    load_reg( R_EAX, 0 );
nkeynes@361
  1429
    load_reg( R_ECX, Rm );
nkeynes@586
  1430
    ADD_r32_r32( R_ECX, R_EAX );
nkeynes@586
  1431
    check_ralign16( R_EAX );
nkeynes@586
  1432
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1433
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1434
    store_reg( R_EAX, Rn );
nkeynes@417
  1435
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1436
:}
nkeynes@361
  1437
MOV.W @(disp, GBR), R0 {:  
nkeynes@671
  1438
    COUNT_INST(I_MOVW);
nkeynes@586
  1439
    load_spreg( R_EAX, R_GBR );
nkeynes@586
  1440
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1441
    check_ralign16( R_EAX );
nkeynes@586
  1442
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1443
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1444
    store_reg( R_EAX, 0 );
nkeynes@417
  1445
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1446
:}
nkeynes@361
  1447
MOV.W @(disp, PC), Rn {:  
nkeynes@671
  1448
    COUNT_INST(I_MOVW);
nkeynes@374
  1449
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1450
	SLOTILLEGAL();
nkeynes@374
  1451
    } else {
nkeynes@586
  1452
	// See comments for MOV.L @(disp, PC), Rn
nkeynes@586
  1453
	uint32_t target = pc + disp + 4;
nkeynes@586
  1454
	if( IS_IN_ICACHE(target) ) {
nkeynes@586
  1455
	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@586
  1456
	    MOV_moff32_EAX( ptr );
nkeynes@586
  1457
	    MOVSX_r16_r32( R_EAX, R_EAX );
nkeynes@586
  1458
	} else {
nkeynes@586
  1459
	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
nkeynes@586
  1460
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@586
  1461
	    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1462
	    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@586
  1463
	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@586
  1464
	}
nkeynes@374
  1465
	store_reg( R_EAX, Rn );
nkeynes@374
  1466
    }
nkeynes@361
  1467
:}
nkeynes@361
  1468
MOV.W @(disp, Rm), R0 {:  
nkeynes@671
  1469
    COUNT_INST(I_MOVW);
nkeynes@586
  1470
    load_reg( R_EAX, Rm );
nkeynes@586
  1471
    ADD_imm32_r32( disp, R_EAX );
nkeynes@586
  1472
    check_ralign16( R_EAX );
nkeynes@586
  1473
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  1474
    MEM_READ_WORD( R_EAX, R_EAX );
nkeynes@361
  1475
    store_reg( R_EAX, 0 );
nkeynes@417
  1476
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1477
:}
nkeynes@361
  1478
MOVA @(disp, PC), R0 {:  
nkeynes@671
  1479
    COUNT_INST(I_MOVA);
nkeynes@374
  1480
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1481
	SLOTILLEGAL();
nkeynes@374
  1482
    } else {
nkeynes@586
  1483
	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
nkeynes@586
  1484
	ADD_sh4r_r32( R_PC, R_ECX );
nkeynes@374
  1485
	store_reg( R_ECX, 0 );
nkeynes@586
  1486
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  1487
    }
nkeynes@361
  1488
:}
nkeynes@361
  1489
MOVCA.L R0, @Rn {:  
nkeynes@671
  1490
    COUNT_INST(I_MOVCA);
nkeynes@586
  1491
    load_reg( R_EAX, Rn );
nkeynes@586
  1492
    check_walign32( R_EAX );
nkeynes@586
  1493
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  1494
    load_reg( R_EDX, 0 );
nkeynes@586
  1495
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  1496
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@361
  1497
:}
nkeynes@359
  1498
nkeynes@359
  1499
/* Control transfer instructions */
nkeynes@374
  1500
BF disp {:
nkeynes@671
  1501
    COUNT_INST(I_BF);
nkeynes@374
  1502
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1503
	SLOTILLEGAL();
nkeynes@374
  1504
    } else {
nkeynes@586
  1505
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1506
	JT_rel8( nottaken );
nkeynes@586
  1507
	exit_block_rel(target, pc+2 );
nkeynes@380
  1508
	JMP_TARGET(nottaken);
nkeynes@408
  1509
	return 2;
nkeynes@374
  1510
    }
nkeynes@374
  1511
:}
nkeynes@374
  1512
BF/S disp {:
nkeynes@671
  1513
    COUNT_INST(I_BFS);
nkeynes@374
  1514
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1515
	SLOTILLEGAL();
nkeynes@374
  1516
    } else {
nkeynes@590
  1517
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1518
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1519
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1520
	    JT_rel8(nottaken);
nkeynes@601
  1521
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1522
	    JMP_TARGET(nottaken);
nkeynes@601
  1523
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1524
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1525
	    exit_block_emu(pc+2);
nkeynes@601
  1526
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1527
	    return 2;
nkeynes@601
  1528
	} else {
nkeynes@601
  1529
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1530
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1531
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1532
	    }
nkeynes@601
  1533
	    sh4vma_t target = disp + pc + 4;
nkeynes@601
  1534
	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
nkeynes@879
  1535
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1536
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1537
	    exit_block_rel( target, pc+4 );
nkeynes@601
  1538
	    
nkeynes@601
  1539
	    // not taken
nkeynes@601
  1540
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1541
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1542
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1543
	    return 4;
nkeynes@417
  1544
	}
nkeynes@374
  1545
    }
nkeynes@374
  1546
:}
nkeynes@374
  1547
BRA disp {:  
nkeynes@671
  1548
    COUNT_INST(I_BRA);
nkeynes@374
  1549
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1550
	SLOTILLEGAL();
nkeynes@374
  1551
    } else {
nkeynes@590
  1552
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1553
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1554
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1555
	    load_spreg( R_EAX, R_PC );
nkeynes@601
  1556
	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@601
  1557
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1558
	    exit_block_emu(pc+2);
nkeynes@601
  1559
	    return 2;
nkeynes@601
  1560
	} else {
nkeynes@601
  1561
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1562
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1563
	    return 4;
nkeynes@601
  1564
	}
nkeynes@374
  1565
    }
nkeynes@374
  1566
:}
nkeynes@374
  1567
BRAF Rn {:  
nkeynes@671
  1568
    COUNT_INST(I_BRAF);
nkeynes@374
  1569
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1570
	SLOTILLEGAL();
nkeynes@374
  1571
    } else {
nkeynes@590
  1572
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1573
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1574
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1575
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1576
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1577
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1578
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1579
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1580
	    exit_block_emu(pc+2);
nkeynes@601
  1581
	    return 2;
nkeynes@601
  1582
	} else {
nkeynes@601
  1583
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1584
	    exit_block_newpcset(pc+2);
nkeynes@601
  1585
	    return 4;
nkeynes@601
  1586
	}
nkeynes@374
  1587
    }
nkeynes@374
  1588
:}
nkeynes@374
  1589
BSR disp {:  
nkeynes@671
  1590
    COUNT_INST(I_BSR);
nkeynes@374
  1591
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1592
	SLOTILLEGAL();
nkeynes@374
  1593
    } else {
nkeynes@590
  1594
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1595
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1596
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1597
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1598
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1599
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1600
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1601
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1602
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1603
	    exit_block_emu(pc+2);
nkeynes@601
  1604
	    return 2;
nkeynes@601
  1605
	} else {
nkeynes@601
  1606
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1607
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1608
	    return 4;
nkeynes@601
  1609
	}
nkeynes@374
  1610
    }
nkeynes@374
  1611
:}
nkeynes@374
  1612
BSRF Rn {:  
nkeynes@671
  1613
    COUNT_INST(I_BSRF);
nkeynes@374
  1614
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1615
	SLOTILLEGAL();
nkeynes@374
  1616
    } else {
nkeynes@590
  1617
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1618
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@590
  1619
	store_spreg( R_EAX, R_PR );
nkeynes@590
  1620
	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
nkeynes@590
  1621
	store_spreg( R_EAX, R_NEW_PC );
nkeynes@590
  1622
nkeynes@601
  1623
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417
  1624
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1625
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1626
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1627
	    exit_block_emu(pc+2);
nkeynes@601
  1628
	    return 2;
nkeynes@601
  1629
	} else {
nkeynes@601
  1630
	    sh4_translate_instruction( pc + 2 );
nkeynes@601
  1631
	    exit_block_newpcset(pc+2);
nkeynes@601
  1632
	    return 4;
nkeynes@601
  1633
	}
nkeynes@374
  1634
    }
nkeynes@374
  1635
:}
nkeynes@374
  1636
BT disp {:
nkeynes@671
  1637
    COUNT_INST(I_BT);
nkeynes@374
  1638
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1639
	SLOTILLEGAL();
nkeynes@374
  1640
    } else {
nkeynes@586
  1641
	sh4vma_t target = disp + pc + 4;
nkeynes@669
  1642
	JF_rel8( nottaken );
nkeynes@586
  1643
	exit_block_rel(target, pc+2 );
nkeynes@380
  1644
	JMP_TARGET(nottaken);
nkeynes@408
  1645
	return 2;
nkeynes@374
  1646
    }
nkeynes@374
  1647
:}
nkeynes@374
  1648
BT/S disp {:
nkeynes@671
  1649
    COUNT_INST(I_BTS);
nkeynes@374
  1650
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1651
	SLOTILLEGAL();
nkeynes@374
  1652
    } else {
nkeynes@590
  1653
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601
  1654
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1655
	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
nkeynes@669
  1656
	    JF_rel8(nottaken);
nkeynes@601
  1657
	    ADD_imm32_r32( disp, R_EAX );
nkeynes@601
  1658
	    JMP_TARGET(nottaken);
nkeynes@601
  1659
	    ADD_sh4r_r32( R_PC, R_EAX );
nkeynes@601
  1660
	    store_spreg( R_EAX, R_NEW_PC );
nkeynes@601
  1661
	    exit_block_emu(pc+2);
nkeynes@601
  1662
	    sh4_x86.branch_taken = TRUE;
nkeynes@601
  1663
	    return 2;
nkeynes@601
  1664
	} else {
nkeynes@601
  1665
	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@601
  1666
		CMP_imm8s_sh4r( 1, R_T );
nkeynes@601
  1667
		sh4_x86.tstate = TSTATE_E;
nkeynes@601
  1668
	    }
nkeynes@601
  1669
	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
nkeynes@879
  1670
	    int save_tstate = sh4_x86.tstate;
nkeynes@601
  1671
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1672
	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601
  1673
	    // not taken
nkeynes@601
  1674
	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879
  1675
	    sh4_x86.tstate = save_tstate;
nkeynes@601
  1676
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1677
	    return 4;
nkeynes@417
  1678
	}
nkeynes@374
  1679
    }
nkeynes@374
  1680
:}
nkeynes@374
  1681
JMP @Rn {:  
nkeynes@671
  1682
    COUNT_INST(I_JMP);
nkeynes@374
  1683
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1684
	SLOTILLEGAL();
nkeynes@374
  1685
    } else {
nkeynes@408
  1686
	load_reg( R_ECX, Rn );
nkeynes@590
  1687
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1688
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1689
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1690
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1691
	    exit_block_emu(pc+2);
nkeynes@601
  1692
	    return 2;
nkeynes@601
  1693
	} else {
nkeynes@601
  1694
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1695
	    exit_block_newpcset(pc+2);
nkeynes@601
  1696
	    return 4;
nkeynes@601
  1697
	}
nkeynes@374
  1698
    }
nkeynes@374
  1699
:}
nkeynes@374
  1700
JSR @Rn {:  
nkeynes@671
  1701
    COUNT_INST(I_JSR);
nkeynes@374
  1702
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1703
	SLOTILLEGAL();
nkeynes@374
  1704
    } else {
nkeynes@590
  1705
	load_spreg( R_EAX, R_PC );
nkeynes@590
  1706
	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
nkeynes@374
  1707
	store_spreg( R_EAX, R_PR );
nkeynes@408
  1708
	load_reg( R_ECX, Rn );
nkeynes@590
  1709
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@601
  1710
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1711
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1712
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601
  1713
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1714
	    exit_block_emu(pc+2);
nkeynes@601
  1715
	    return 2;
nkeynes@601
  1716
	} else {
nkeynes@601
  1717
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1718
	    exit_block_newpcset(pc+2);
nkeynes@601
  1719
	    return 4;
nkeynes@601
  1720
	}
nkeynes@374
  1721
    }
nkeynes@374
  1722
:}
nkeynes@374
  1723
RTE {:  
nkeynes@671
  1724
    COUNT_INST(I_RTE);
nkeynes@374
  1725
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1726
	SLOTILLEGAL();
nkeynes@374
  1727
    } else {
nkeynes@408
  1728
	check_priv();
nkeynes@408
  1729
	load_spreg( R_ECX, R_SPC );
nkeynes@590
  1730
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@374
  1731
	load_spreg( R_EAX, R_SSR );
nkeynes@374
  1732
	call_func1( sh4_write_sr, R_EAX );
nkeynes@590
  1733
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377
  1734
	sh4_x86.priv_checked = FALSE;
nkeynes@377
  1735
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  1736
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409
  1737
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1738
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1739
	    exit_block_emu(pc+2);
nkeynes@601
  1740
	    return 2;
nkeynes@601
  1741
	} else {
nkeynes@601
  1742
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1743
	    exit_block_newpcset(pc+2);
nkeynes@601
  1744
	    return 4;
nkeynes@601
  1745
	}
nkeynes@374
  1746
    }
nkeynes@374
  1747
:}
nkeynes@374
  1748
RTS {:  
nkeynes@671
  1749
    COUNT_INST(I_RTS);
nkeynes@374
  1750
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1751
	SLOTILLEGAL();
nkeynes@374
  1752
    } else {
nkeynes@408
  1753
	load_spreg( R_ECX, R_PR );
nkeynes@590
  1754
	store_spreg( R_ECX, R_NEW_PC );
nkeynes@590
  1755
	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409
  1756
	sh4_x86.branch_taken = TRUE;
nkeynes@601
  1757
	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601
  1758
	    exit_block_emu(pc+2);
nkeynes@601
  1759
	    return 2;
nkeynes@601
  1760
	} else {
nkeynes@601
  1761
	    sh4_translate_instruction(pc+2);
nkeynes@601
  1762
	    exit_block_newpcset(pc+2);
nkeynes@601
  1763
	    return 4;
nkeynes@601
  1764
	}
nkeynes@374
  1765
    }
nkeynes@374
  1766
:}
nkeynes@374
  1767
TRAPA #imm {:  
nkeynes@671
  1768
    COUNT_INST(I_TRAPA);
nkeynes@374
  1769
    if( sh4_x86.in_delay_slot ) {
nkeynes@374
  1770
	SLOTILLEGAL();
nkeynes@374
  1771
    } else {
nkeynes@590
  1772
	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
nkeynes@590
  1773
	ADD_r32_sh4r( R_ECX, R_PC );
nkeynes@527
  1774
	load_imm32( R_EAX, imm );
nkeynes@527
  1775
	call_func1( sh4_raise_trap, R_EAX );
nkeynes@417
  1776
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@408
  1777
	exit_block_pcset(pc);
nkeynes@409
  1778
	sh4_x86.branch_taken = TRUE;
nkeynes@408
  1779
	return 2;
nkeynes@374
  1780
    }
nkeynes@374
  1781
:}
nkeynes@374
  1782
UNDEF {:  
nkeynes@671
  1783
    COUNT_INST(I_UNDEF);
nkeynes@374
  1784
    if( sh4_x86.in_delay_slot ) {
nkeynes@382
  1785
	SLOTILLEGAL();
nkeynes@374
  1786
    } else {
nkeynes@586
  1787
	JMP_exc(EXC_ILLEGAL);
nkeynes@408
  1788
	return 2;
nkeynes@374
  1789
    }
nkeynes@368
  1790
:}
nkeynes@374
  1791
nkeynes@374
  1792
CLRMAC {:  
nkeynes@671
  1793
    COUNT_INST(I_CLRMAC);
nkeynes@374
  1794
    XOR_r32_r32(R_EAX, R_EAX);
nkeynes@374
  1795
    store_spreg( R_EAX, R_MACL );
nkeynes@374
  1796
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  1797
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1798
:}
nkeynes@374
  1799
CLRS {:
nkeynes@671
  1800
    COUNT_INST(I_CLRS);
nkeynes@374
  1801
    CLC();
nkeynes@374
  1802
    SETC_sh4r(R_S);
nkeynes@872
  1803
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@368
  1804
:}
nkeynes@374
  1805
CLRT {:  
nkeynes@671
  1806
    COUNT_INST(I_CLRT);
nkeynes@374
  1807
    CLC();
nkeynes@374
  1808
    SETC_t();
nkeynes@417
  1809
    sh4_x86.tstate = TSTATE_C;
nkeynes@359
  1810
:}
nkeynes@374
  1811
SETS {:  
nkeynes@671
  1812
    COUNT_INST(I_SETS);
nkeynes@374
  1813
    STC();
nkeynes@374
  1814
    SETC_sh4r(R_S);
nkeynes@872
  1815
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  1816
:}
nkeynes@374
  1817
SETT {:  
nkeynes@671
  1818
    COUNT_INST(I_SETT);
nkeynes@374
  1819
    STC();
nkeynes@374
  1820
    SETC_t();
nkeynes@417
  1821
    sh4_x86.tstate = TSTATE_C;
nkeynes@374
  1822
:}
nkeynes@359
  1823
nkeynes@375
  1824
/* Floating point moves */
nkeynes@375
  1825
FMOV FRm, FRn {:  
nkeynes@671
  1826
    COUNT_INST(I_FMOV1);
nkeynes@377
  1827
    check_fpuen();
nkeynes@901
  1828
    if( sh4_x86.double_size ) {
nkeynes@901
  1829
        load_dr0( R_EAX, FRm );
nkeynes@901
  1830
        load_dr1( R_ECX, FRm );
nkeynes@901
  1831
        store_dr0( R_EAX, FRn );
nkeynes@901
  1832
        store_dr1( R_ECX, FRn );
nkeynes@901
  1833
    } else {
nkeynes@901
  1834
        load_fr( R_EAX, FRm ); // SZ=0 branch
nkeynes@901
  1835
        store_fr( R_EAX, FRn );
nkeynes@901
  1836
    }
nkeynes@375
  1837
:}
nkeynes@416
  1838
FMOV FRm, @Rn {: 
nkeynes@671
  1839
    COUNT_INST(I_FMOV2);
nkeynes@586
  1840
    check_fpuen();
nkeynes@586
  1841
    load_reg( R_EAX, Rn );
nkeynes@901
  1842
    if( sh4_x86.double_size ) {
nkeynes@901
  1843
        check_walign64( R_EAX );
nkeynes@901
  1844
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1845
        load_dr0( R_EDX, FRm );
nkeynes@905
  1846
        load_dr1( R_ECX, FRm );
nkeynes@905
  1847
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1848
    } else {
nkeynes@901
  1849
        check_walign32( R_EAX );
nkeynes@901
  1850
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1851
        load_fr( R_EDX, FRm );
nkeynes@905
  1852
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1853
    }
nkeynes@417
  1854
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1855
:}
nkeynes@375
  1856
FMOV @Rm, FRn {:  
nkeynes@671
  1857
    COUNT_INST(I_FMOV5);
nkeynes@586
  1858
    check_fpuen();
nkeynes@586
  1859
    load_reg( R_EAX, Rm );
nkeynes@901
  1860
    if( sh4_x86.double_size ) {
nkeynes@901
  1861
        check_ralign64( R_EAX );
nkeynes@901
  1862
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@905
  1863
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1864
        store_dr0( R_EDX, FRn );
nkeynes@901
  1865
        store_dr1( R_EAX, FRn );    
nkeynes@901
  1866
    } else {
nkeynes@901
  1867
        check_ralign32( R_EAX );
nkeynes@901
  1868
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1869
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1870
        store_fr( R_EAX, FRn );
nkeynes@901
  1871
    }
nkeynes@417
  1872
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@375
  1873
:}
nkeynes@377
  1874
FMOV FRm, @-Rn {:  
nkeynes@671
  1875
    COUNT_INST(I_FMOV3);
nkeynes@586
  1876
    check_fpuen();
nkeynes@586
  1877
    load_reg( R_EAX, Rn );
nkeynes@901
  1878
    if( sh4_x86.double_size ) {
nkeynes@901
  1879
        check_walign64( R_EAX );
nkeynes@901
  1880
        ADD_imm8s_r32(-8,R_EAX);
nkeynes@901
  1881
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1882
        load_dr0( R_EDX, FRm );
nkeynes@905
  1883
        load_dr1( R_ECX, FRm );
nkeynes@901
  1884
        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
nkeynes@905
  1885
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1886
    } else {
nkeynes@901
  1887
        check_walign32( R_EAX );
nkeynes@901
  1888
        ADD_imm8s_r32( -4, R_EAX );
nkeynes@901
  1889
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1890
        load_fr( R_EDX, FRm );
nkeynes@901
  1891
        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
nkeynes@905
  1892
        MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@901
  1893
    }
nkeynes@417
  1894
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1895
:}
nkeynes@416
  1896
FMOV @Rm+, FRn {:
nkeynes@671
  1897
    COUNT_INST(I_FMOV6);
nkeynes@586
  1898
    check_fpuen();
nkeynes@586
  1899
    load_reg( R_EAX, Rm );
nkeynes@901
  1900
    if( sh4_x86.double_size ) {
nkeynes@901
  1901
        check_ralign64( R_EAX );
nkeynes@901
  1902
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1903
        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
nkeynes@905
  1904
        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
nkeynes@905
  1905
        store_dr0( R_EDX, FRn );
nkeynes@901
  1906
        store_dr1( R_EAX, FRn );
nkeynes@901
  1907
    } else {
nkeynes@901
  1908
        check_ralign32( R_EAX );
nkeynes@901
  1909
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1910
        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@901
  1911
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1912
        store_fr( R_EAX, FRn );
nkeynes@901
  1913
    }
nkeynes@417
  1914
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1915
:}
nkeynes@377
  1916
FMOV FRm, @(R0, Rn) {:  
nkeynes@671
  1917
    COUNT_INST(I_FMOV4);
nkeynes@586
  1918
    check_fpuen();
nkeynes@586
  1919
    load_reg( R_EAX, Rn );
nkeynes@586
  1920
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1921
    if( sh4_x86.double_size ) {
nkeynes@901
  1922
        check_walign64( R_EAX );
nkeynes@901
  1923
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1924
        load_dr0( R_EDX, FRm );
nkeynes@905
  1925
        load_dr1( R_ECX, FRm );
nkeynes@905
  1926
        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
nkeynes@901
  1927
    } else {
nkeynes@901
  1928
        check_walign32( R_EAX );
nkeynes@901
  1929
        MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@905
  1930
        load_fr( R_EDX, FRm );
nkeynes@905
  1931
        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
nkeynes@901
  1932
    }
nkeynes@417
  1933
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1934
:}
nkeynes@377
  1935
FMOV @(R0, Rm), FRn {:  
nkeynes@671
  1936
    COUNT_INST(I_FMOV7);
nkeynes@586
  1937
    check_fpuen();
nkeynes@586
  1938
    load_reg( R_EAX, Rm );
nkeynes@586
  1939
    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
nkeynes@901
  1940
    if( sh4_x86.double_size ) {
nkeynes@901
  1941
        check_ralign64( R_EAX );
nkeynes@901
  1942
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1943
        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
nkeynes@901
  1944
        store_dr0( R_ECX, FRn );
nkeynes@901
  1945
        store_dr1( R_EAX, FRn );
nkeynes@901
  1946
    } else {
nkeynes@901
  1947
        check_ralign32( R_EAX );
nkeynes@901
  1948
        MMU_TRANSLATE_READ( R_EAX );
nkeynes@901
  1949
        MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@901
  1950
        store_fr( R_EAX, FRn );
nkeynes@901
  1951
    }
nkeynes@417
  1952
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1953
:}
nkeynes@377
  1954
FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671
  1955
    COUNT_INST(I_FLDI0);
nkeynes@377
  1956
    check_fpuen();
nkeynes@901
  1957
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1958
        XOR_r32_r32( R_EAX, R_EAX );
nkeynes@901
  1959
        store_fr( R_EAX, FRn );
nkeynes@901
  1960
    }
nkeynes@417
  1961
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  1962
:}
nkeynes@377
  1963
FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671
  1964
    COUNT_INST(I_FLDI1);
nkeynes@377
  1965
    check_fpuen();
nkeynes@901
  1966
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  1967
        load_imm32(R_EAX, 0x3F800000);
nkeynes@901
  1968
        store_fr( R_EAX, FRn );
nkeynes@901
  1969
    }
nkeynes@377
  1970
:}
nkeynes@377
  1971
nkeynes@377
  1972
FLOAT FPUL, FRn {:  
nkeynes@671
  1973
    COUNT_INST(I_FLOAT);
nkeynes@377
  1974
    check_fpuen();
nkeynes@377
  1975
    FILD_sh4r(R_FPUL);
nkeynes@901
  1976
    if( sh4_x86.double_prec ) {
nkeynes@901
  1977
        pop_dr( FRn );
nkeynes@901
  1978
    } else {
nkeynes@901
  1979
        pop_fr( FRn );
nkeynes@901
  1980
    }
nkeynes@377
  1981
:}
nkeynes@377
  1982
FTRC FRm, FPUL {:  
nkeynes@671
  1983
    COUNT_INST(I_FTRC);
nkeynes@377
  1984
    check_fpuen();
nkeynes@901
  1985
    if( sh4_x86.double_prec ) {
nkeynes@901
  1986
        push_dr( FRm );
nkeynes@901
  1987
    } else {
nkeynes@901
  1988
        push_fr( FRm );
nkeynes@901
  1989
    }
nkeynes@789
  1990
    load_ptr( R_ECX, &max_int );
nkeynes@388
  1991
    FILD_r32ind( R_ECX );
nkeynes@388
  1992
    FCOMIP_st(1);
nkeynes@669
  1993
    JNA_rel8( sat );
nkeynes@789
  1994
    load_ptr( R_ECX, &min_int );  // 5
nkeynes@388
  1995
    FILD_r32ind( R_ECX );           // 2
nkeynes@388
  1996
    FCOMIP_st(1);                   // 2
nkeynes@669
  1997
    JAE_rel8( sat2 );            // 2
nkeynes@789
  1998
    load_ptr( R_EAX, &save_fcw );
nkeynes@394
  1999
    FNSTCW_r32ind( R_EAX );
nkeynes@789
  2000
    load_ptr( R_EDX, &trunc_fcw );
nkeynes@394
  2001
    FLDCW_r32ind( R_EDX );
nkeynes@388
  2002
    FISTP_sh4r(R_FPUL);             // 3
nkeynes@394
  2003
    FLDCW_r32ind( R_EAX );
nkeynes@669
  2004
    JMP_rel8(end);             // 2
nkeynes@388
  2005
nkeynes@388
  2006
    JMP_TARGET(sat);
nkeynes@388
  2007
    JMP_TARGET(sat2);
nkeynes@388
  2008
    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
nkeynes@388
  2009
    store_spreg( R_ECX, R_FPUL );
nkeynes@388
  2010
    FPOP_st();
nkeynes@388
  2011
    JMP_TARGET(end);
nkeynes@417
  2012
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2013
:}
nkeynes@377
  2014
FLDS FRm, FPUL {:  
nkeynes@671
  2015
    COUNT_INST(I_FLDS);
nkeynes@377
  2016
    check_fpuen();
nkeynes@669
  2017
    load_fr( R_EAX, FRm );
nkeynes@377
  2018
    store_spreg( R_EAX, R_FPUL );
nkeynes@377
  2019
:}
nkeynes@377
  2020
FSTS FPUL, FRn {:  
nkeynes@671
  2021
    COUNT_INST(I_FSTS);
nkeynes@377
  2022
    check_fpuen();
nkeynes@377
  2023
    load_spreg( R_EAX, R_FPUL );
nkeynes@669
  2024
    store_fr( R_EAX, FRn );
nkeynes@377
  2025
:}
nkeynes@377
  2026
FCNVDS FRm, FPUL {:  
nkeynes@671
  2027
    COUNT_INST(I_FCNVDS);
nkeynes@377
  2028
    check_fpuen();
nkeynes@901
  2029
    if( sh4_x86.double_prec ) {
nkeynes@901
  2030
        push_dr( FRm );
nkeynes@901
  2031
        pop_fpul();
nkeynes@901
  2032
    }
nkeynes@377
  2033
:}
nkeynes@377
  2034
FCNVSD FPUL, FRn {:  
nkeynes@671
  2035
    COUNT_INST(I_FCNVSD);
nkeynes@377
  2036
    check_fpuen();
nkeynes@901
  2037
    if( sh4_x86.double_prec ) {
nkeynes@901
  2038
        push_fpul();
nkeynes@901
  2039
        pop_dr( FRn );
nkeynes@901
  2040
    }
nkeynes@377
  2041
:}
nkeynes@375
  2042
nkeynes@359
  2043
/* Floating point instructions */
nkeynes@374
  2044
FABS FRn {:  
nkeynes@671
  2045
    COUNT_INST(I_FABS);
nkeynes@377
  2046
    check_fpuen();
nkeynes@901
  2047
    if( sh4_x86.double_prec ) {
nkeynes@901
  2048
        push_dr(FRn);
nkeynes@901
  2049
        FABS_st0();
nkeynes@901
  2050
        pop_dr(FRn);
nkeynes@901
  2051
    } else {
nkeynes@901
  2052
        push_fr(FRn);
nkeynes@901
  2053
        FABS_st0();
nkeynes@901
  2054
        pop_fr(FRn);
nkeynes@901
  2055
    }
nkeynes@374
  2056
:}
nkeynes@377
  2057
FADD FRm, FRn {:  
nkeynes@671
  2058
    COUNT_INST(I_FADD);
nkeynes@377
  2059
    check_fpuen();
nkeynes@901
  2060
    if( sh4_x86.double_prec ) {
nkeynes@901
  2061
        push_dr(FRm);
nkeynes@901
  2062
        push_dr(FRn);
nkeynes@901
  2063
        FADDP_st(1);
nkeynes@901
  2064
        pop_dr(FRn);
nkeynes@901
  2065
    } else {
nkeynes@901
  2066
        push_fr(FRm);
nkeynes@901
  2067
        push_fr(FRn);
nkeynes@901
  2068
        FADDP_st(1);
nkeynes@901
  2069
        pop_fr(FRn);
nkeynes@901
  2070
    }
nkeynes@375
  2071
:}
nkeynes@377
  2072
FDIV FRm, FRn {:  
nkeynes@671
  2073
    COUNT_INST(I_FDIV);
nkeynes@377
  2074
    check_fpuen();
nkeynes@901
  2075
    if( sh4_x86.double_prec ) {
nkeynes@901
  2076
        push_dr(FRn);
nkeynes@901
  2077
        push_dr(FRm);
nkeynes@901
  2078
        FDIVP_st(1);
nkeynes@901
  2079
        pop_dr(FRn);
nkeynes@901
  2080
    } else {
nkeynes@901
  2081
        push_fr(FRn);
nkeynes@901
  2082
        push_fr(FRm);
nkeynes@901
  2083
        FDIVP_st(1);
nkeynes@901
  2084
        pop_fr(FRn);
nkeynes@901
  2085
    }
nkeynes@375
  2086
:}
nkeynes@375
  2087
FMAC FR0, FRm, FRn {:  
nkeynes@671
  2088
    COUNT_INST(I_FMAC);
nkeynes@377
  2089
    check_fpuen();
nkeynes@901
  2090
    if( sh4_x86.double_prec ) {
nkeynes@901
  2091
        push_dr( 0 );
nkeynes@901
  2092
        push_dr( FRm );
nkeynes@901
  2093
        FMULP_st(1);
nkeynes@901
  2094
        push_dr( FRn );
nkeynes@901
  2095
        FADDP_st(1);
nkeynes@901
  2096
        pop_dr( FRn );
nkeynes@901
  2097
    } else {
nkeynes@901
  2098
        push_fr( 0 );
nkeynes@901
  2099
        push_fr( FRm );
nkeynes@901
  2100
        FMULP_st(1);
nkeynes@901
  2101
        push_fr( FRn );
nkeynes@901
  2102
        FADDP_st(1);
nkeynes@901
  2103
        pop_fr( FRn );
nkeynes@901
  2104
    }
nkeynes@375
  2105
:}
nkeynes@375
  2106
nkeynes@377
  2107
FMUL FRm, FRn {:  
nkeynes@671
  2108
    COUNT_INST(I_FMUL);
nkeynes@377
  2109
    check_fpuen();
nkeynes@901
  2110
    if( sh4_x86.double_prec ) {
nkeynes@901
  2111
        push_dr(FRm);
nkeynes@901
  2112
        push_dr(FRn);
nkeynes@901
  2113
        FMULP_st(1);
nkeynes@901
  2114
        pop_dr(FRn);
nkeynes@901
  2115
    } else {
nkeynes@901
  2116
        push_fr(FRm);
nkeynes@901
  2117
        push_fr(FRn);
nkeynes@901
  2118
        FMULP_st(1);
nkeynes@901
  2119
        pop_fr(FRn);
nkeynes@901
  2120
    }
nkeynes@377
  2121
:}
nkeynes@377
  2122
FNEG FRn {:  
nkeynes@671
  2123
    COUNT_INST(I_FNEG);
nkeynes@377
  2124
    check_fpuen();
nkeynes@901
  2125
    if( sh4_x86.double_prec ) {
nkeynes@901
  2126
        push_dr(FRn);
nkeynes@901
  2127
        FCHS_st0();
nkeynes@901
  2128
        pop_dr(FRn);
nkeynes@901
  2129
    } else {
nkeynes@901
  2130
        push_fr(FRn);
nkeynes@901
  2131
        FCHS_st0();
nkeynes@901
  2132
        pop_fr(FRn);
nkeynes@901
  2133
    }
nkeynes@377
  2134
:}
nkeynes@377
  2135
FSRRA FRn {:  
nkeynes@671
  2136
    COUNT_INST(I_FSRRA);
nkeynes@377
  2137
    check_fpuen();
nkeynes@901
  2138
    if( sh4_x86.double_prec == 0 ) {
nkeynes@901
  2139
        FLD1_st0();
nkeynes@901
  2140
        push_fr(FRn);
nkeynes@901
  2141
        FSQRT_st0();
nkeynes@901
  2142
        FDIVP_st(1);
nkeynes@901
  2143
        pop_fr(FRn);
nkeynes@901
  2144
    }
nkeynes@377
  2145
:}
nkeynes@377
  2146
FSQRT FRn {:  
nkeynes@671
  2147
    COUNT_INST(I_FSQRT);
nkeynes@377
  2148
    check_fpuen();
nkeynes@901
  2149
    if( sh4_x86.double_prec ) {
nkeynes@901
  2150
        push_dr(FRn);
nkeynes@901
  2151
        FSQRT_st0();
nkeynes@901
  2152
        pop_dr(FRn);
nkeynes@901
  2153
    } else {
nkeynes@901
  2154
        push_fr(FRn);
nkeynes@901
  2155
        FSQRT_st0();
nkeynes@901
  2156
        pop_fr(FRn);
nkeynes@901
  2157
    }
nkeynes@377
  2158
:}
nkeynes@377
  2159
FSUB FRm, FRn {:  
nkeynes@671
  2160
    COUNT_INST(I_FSUB);
nkeynes@377
  2161
    check_fpuen();
nkeynes@901
  2162
    if( sh4_x86.double_prec ) {
nkeynes@901
  2163
        push_dr(FRn);
nkeynes@901
  2164
        push_dr(FRm);
nkeynes@901
  2165
        FSUBP_st(1);
nkeynes@901
  2166
        pop_dr(FRn);
nkeynes@901
  2167
    } else {
nkeynes@901
  2168
        push_fr(FRn);
nkeynes@901
  2169
        push_fr(FRm);
nkeynes@901
  2170
        FSUBP_st(1);
nkeynes@901
  2171
        pop_fr(FRn);
nkeynes@901
  2172
    }
nkeynes@377
  2173
:}
nkeynes@377
  2174
nkeynes@377
  2175
FCMP/EQ FRm, FRn {:  
nkeynes@671
  2176
    COUNT_INST(I_FCMPEQ);
nkeynes@377
  2177
    check_fpuen();
nkeynes@901
  2178
    if( sh4_x86.double_prec ) {
nkeynes@901
  2179
        push_dr(FRm);
nkeynes@901
  2180
        push_dr(FRn);
nkeynes@901
  2181
    } else {
nkeynes@901
  2182
        push_fr(FRm);
nkeynes@901
  2183
        push_fr(FRn);
nkeynes@901
  2184
    }
nkeynes@377
  2185
    FCOMIP_st(1);
nkeynes@377
  2186
    SETE_t();
nkeynes@377
  2187
    FPOP_st();
nkeynes@901
  2188
    sh4_x86.tstate = TSTATE_E;
nkeynes@377
  2189
:}
nkeynes@377
  2190
FCMP/GT FRm, FRn {:  
nkeynes@671
  2191
    COUNT_INST(I_FCMPGT);
nkeynes@377
  2192
    check_fpuen();
nkeynes@901
  2193
    if( sh4_x86.double_prec ) {
nkeynes@901
  2194
        push_dr(FRm);
nkeynes@901
  2195
        push_dr(FRn);
nkeynes@901
  2196
    } else {
nkeynes@901
  2197
        push_fr(FRm);
nkeynes@901
  2198
        push_fr(FRn);
nkeynes@901
  2199
    }
nkeynes@377
  2200
    FCOMIP_st(1);
nkeynes@377
  2201
    SETA_t();
nkeynes@377
  2202
    FPOP_st();
nkeynes@901
  2203
    sh4_x86.tstate = TSTATE_A;
nkeynes@377
  2204
:}
nkeynes@377
  2205
nkeynes@377
  2206
FSCA FPUL, FRn {:  
nkeynes@671
  2207
    COUNT_INST(I_FSCA);
nkeynes@377
  2208
    check_fpuen();
nkeynes@901
  2209
    if( sh4_x86.double_prec == 0 ) {
nkeynes@905
  2210
        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
nkeynes@905
  2211
        load_spreg( R_EAX, R_FPUL );
nkeynes@905
  2212
        call_func2( sh4_fsca, R_EAX, R_EDX );
nkeynes@901
  2213
    }
nkeynes@417
  2214
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2215
:}
nkeynes@377
  2216
FIPR FVm, FVn {:  
nkeynes@671
  2217
    COUNT_INST(I_FIPR);
nkeynes@377
  2218
    check_fpuen();
nkeynes@901
  2219
    if( sh4_x86.double_prec == 0 ) {
nkeynes@904
  2220
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2221
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@903
  2222
            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903
  2223
            HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903
  2224
            HADDPS_xmm_xmm( 4, 4 );
nkeynes@903
  2225
            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903
  2226
        } else {
nkeynes@904
  2227
            push_fr( FVm<<2 );
nkeynes@903
  2228
            push_fr( FVn<<2 );
nkeynes@903
  2229
            FMULP_st(1);
nkeynes@903
  2230
            push_fr( (FVm<<2)+1);
nkeynes@903
  2231
            push_fr( (FVn<<2)+1);
nkeynes@903
  2232
            FMULP_st(1);
nkeynes@903
  2233
            FADDP_st(1);
nkeynes@903
  2234
            push_fr( (FVm<<2)+2);
nkeynes@903
  2235
            push_fr( (FVn<<2)+2);
nkeynes@903
  2236
            FMULP_st(1);
nkeynes@903
  2237
            FADDP_st(1);
nkeynes@903
  2238
            push_fr( (FVm<<2)+3);
nkeynes@903
  2239
            push_fr( (FVn<<2)+3);
nkeynes@903
  2240
            FMULP_st(1);
nkeynes@903
  2241
            FADDP_st(1);
nkeynes@903
  2242
            pop_fr( (FVn<<2)+3);
nkeynes@904
  2243
        }
nkeynes@901
  2244
    }
nkeynes@377
  2245
:}
nkeynes@377
  2246
FTRV XMTRX, FVn {:  
nkeynes@671
  2247
    COUNT_INST(I_FTRV);
nkeynes@377
  2248
    check_fpuen();
nkeynes@901
  2249
    if( sh4_x86.double_prec == 0 ) {
nkeynes@903
  2250
        if( sh4_x86.sse3_enabled ) {
nkeynes@903
  2251
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@903
  2252
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@903
  2253
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@903
  2254
            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903
  2255
nkeynes@903
  2256
            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@903
  2257
            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@903
  2258
            MOVAPS_xmm_xmm( 4, 6 );
nkeynes@903
  2259
            MOVAPS_xmm_xmm( 5, 7 );
nkeynes@903
  2260
            MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903
  2261
            MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903
  2262
            MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903
  2263
            MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903
  2264
            MULPS_xmm_xmm( 0, 4 );
nkeynes@903
  2265
            MULPS_xmm_xmm( 1, 5 );
nkeynes@903
  2266
            MULPS_xmm_xmm( 2, 6 );
nkeynes@903
  2267
            MULPS_xmm_xmm( 3, 7 );
nkeynes@903
  2268
            ADDPS_xmm_xmm( 5, 4 );
nkeynes@903
  2269
            ADDPS_xmm_xmm( 7, 6 );
nkeynes@903
  2270
            ADDPS_xmm_xmm( 6, 4 );
nkeynes@903
  2271
            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903
  2272
        } else {
nkeynes@903
  2273
            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
nkeynes@903
  2274
            call_func1( sh4_ftrv, R_EAX );
nkeynes@903
  2275
        }
nkeynes@901
  2276
    }
nkeynes@417
  2277
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2278
:}
nkeynes@377
  2279
nkeynes@377
  2280
FRCHG {:  
nkeynes@671
  2281
    COUNT_INST(I_FRCHG);
nkeynes@377
  2282
    check_fpuen();
nkeynes@377
  2283
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2284
    XOR_imm32_r32( FPSCR_FR, R_ECX );
nkeynes@377
  2285
    store_spreg( R_ECX, R_FPSCR );
nkeynes@669
  2286
    call_func0( sh4_switch_fr_banks );
nkeynes@417
  2287
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@377
  2288
:}
nkeynes@377
  2289
FSCHG {:  
nkeynes@671
  2290
    COUNT_INST(I_FSCHG);
nkeynes@377
  2291
    check_fpuen();
nkeynes@377
  2292
    load_spreg( R_ECX, R_FPSCR );
nkeynes@377
  2293
    XOR_imm32_r32( FPSCR_SZ, R_ECX );
nkeynes@377
  2294
    store_spreg( R_ECX, R_FPSCR );
nkeynes@417
  2295
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2296
    sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377
  2297
:}
nkeynes@359
  2298
nkeynes@359
  2299
/* Processor control instructions */
nkeynes@368
  2300
LDC Rm, SR {:
nkeynes@671
  2301
    COUNT_INST(I_LDCSR);
nkeynes@386
  2302
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2303
	SLOTILLEGAL();
nkeynes@386
  2304
    } else {
nkeynes@386
  2305
	check_priv();
nkeynes@386
  2306
	load_reg( R_EAX, Rm );
nkeynes@386
  2307
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2308
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2309
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2310
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2311
    }
nkeynes@368
  2312
:}
nkeynes@359
  2313
LDC Rm, GBR {: 
nkeynes@671
  2314
    COUNT_INST(I_LDC);
nkeynes@359
  2315
    load_reg( R_EAX, Rm );
nkeynes@359
  2316
    store_spreg( R_EAX, R_GBR );
nkeynes@359
  2317
:}
nkeynes@359
  2318
LDC Rm, VBR {:  
nkeynes@671
  2319
    COUNT_INST(I_LDC);
nkeynes@386
  2320
    check_priv();
nkeynes@359
  2321
    load_reg( R_EAX, Rm );
nkeynes@359
  2322
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2323
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2324
:}
nkeynes@359
  2325
LDC Rm, SSR {:  
nkeynes@671
  2326
    COUNT_INST(I_LDC);
nkeynes@386
  2327
    check_priv();
nkeynes@359
  2328
    load_reg( R_EAX, Rm );
nkeynes@359
  2329
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2330
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2331
:}
nkeynes@359
  2332
LDC Rm, SGR {:  
nkeynes@671
  2333
    COUNT_INST(I_LDC);
nkeynes@386
  2334
    check_priv();
nkeynes@359
  2335
    load_reg( R_EAX, Rm );
nkeynes@359
  2336
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2337
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2338
:}
nkeynes@359
  2339
LDC Rm, SPC {:  
nkeynes@671
  2340
    COUNT_INST(I_LDC);
nkeynes@386
  2341
    check_priv();
nkeynes@359
  2342
    load_reg( R_EAX, Rm );
nkeynes@359
  2343
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2344
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2345
:}
nkeynes@359
  2346
LDC Rm, DBR {:  
nkeynes@671
  2347
    COUNT_INST(I_LDC);
nkeynes@386
  2348
    check_priv();
nkeynes@359
  2349
    load_reg( R_EAX, Rm );
nkeynes@359
  2350
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2351
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2352
:}
nkeynes@374
  2353
LDC Rm, Rn_BANK {:  
nkeynes@671
  2354
    COUNT_INST(I_LDC);
nkeynes@386
  2355
    check_priv();
nkeynes@374
  2356
    load_reg( R_EAX, Rm );
nkeynes@374
  2357
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2358
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2359
:}
nkeynes@359
  2360
LDC.L @Rm+, GBR {:  
nkeynes@671
  2361
    COUNT_INST(I_LDCM);
nkeynes@359
  2362
    load_reg( R_EAX, Rm );
nkeynes@395
  2363
    check_ralign32( R_EAX );
nkeynes@586
  2364
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2365
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2366
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2367
    store_spreg( R_EAX, R_GBR );
nkeynes@417
  2368
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2369
:}
nkeynes@368
  2370
LDC.L @Rm+, SR {:
nkeynes@671
  2371
    COUNT_INST(I_LDCSRM);
nkeynes@386
  2372
    if( sh4_x86.in_delay_slot ) {
nkeynes@386
  2373
	SLOTILLEGAL();
nkeynes@386
  2374
    } else {
nkeynes@586
  2375
	check_priv();
nkeynes@386
  2376
	load_reg( R_EAX, Rm );
nkeynes@395
  2377
	check_ralign32( R_EAX );
nkeynes@586
  2378
	MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2379
	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2380
	MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@386
  2381
	call_func1( sh4_write_sr, R_EAX );
nkeynes@386
  2382
	sh4_x86.priv_checked = FALSE;
nkeynes@386
  2383
	sh4_x86.fpuen_checked = FALSE;
nkeynes@417
  2384
	sh4_x86.tstate = TSTATE_NONE;
nkeynes@386
  2385
    }
nkeynes@359
  2386
:}
nkeynes@359
  2387
LDC.L @Rm+, VBR {:  
nkeynes@671
  2388
    COUNT_INST(I_LDCM);
nkeynes@586
  2389
    check_priv();
nkeynes@359
  2390
    load_reg( R_EAX, Rm );
nkeynes@395
  2391
    check_ralign32( R_EAX );
nkeynes@586
  2392
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2393
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2394
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2395
    store_spreg( R_EAX, R_VBR );
nkeynes@417
  2396
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2397
:}
nkeynes@359
  2398
LDC.L @Rm+, SSR {:
nkeynes@671
  2399
    COUNT_INST(I_LDCM);
nkeynes@586
  2400
    check_priv();
nkeynes@359
  2401
    load_reg( R_EAX, Rm );
nkeynes@416
  2402
    check_ralign32( R_EAX );
nkeynes@586
  2403
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2404
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2405
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2406
    store_spreg( R_EAX, R_SSR );
nkeynes@417
  2407
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2408
:}
nkeynes@359
  2409
LDC.L @Rm+, SGR {:  
nkeynes@671
  2410
    COUNT_INST(I_LDCM);
nkeynes@586
  2411
    check_priv();
nkeynes@359
  2412
    load_reg( R_EAX, Rm );
nkeynes@395
  2413
    check_ralign32( R_EAX );
nkeynes@586
  2414
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2415
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2416
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2417
    store_spreg( R_EAX, R_SGR );
nkeynes@417
  2418
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2419
:}
nkeynes@359
  2420
LDC.L @Rm+, SPC {:  
nkeynes@671
  2421
    COUNT_INST(I_LDCM);
nkeynes@586
  2422
    check_priv();
nkeynes@359
  2423
    load_reg( R_EAX, Rm );
nkeynes@395
  2424
    check_ralign32( R_EAX );
nkeynes@586
  2425
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2426
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2427
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2428
    store_spreg( R_EAX, R_SPC );
nkeynes@417
  2429
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2430
:}
nkeynes@359
  2431
LDC.L @Rm+, DBR {:  
nkeynes@671
  2432
    COUNT_INST(I_LDCM);
nkeynes@586
  2433
    check_priv();
nkeynes@359
  2434
    load_reg( R_EAX, Rm );
nkeynes@395
  2435
    check_ralign32( R_EAX );
nkeynes@586
  2436
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2437
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2438
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2439
    store_spreg( R_EAX, R_DBR );
nkeynes@417
  2440
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2441
:}
nkeynes@359
  2442
LDC.L @Rm+, Rn_BANK {:  
nkeynes@671
  2443
    COUNT_INST(I_LDCM);
nkeynes@586
  2444
    check_priv();
nkeynes@374
  2445
    load_reg( R_EAX, Rm );
nkeynes@395
  2446
    check_ralign32( R_EAX );
nkeynes@586
  2447
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2448
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2449
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@374
  2450
    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417
  2451
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2452
:}
nkeynes@626
  2453
LDS Rm, FPSCR {:
nkeynes@673
  2454
    COUNT_INST(I_LDSFPSCR);
nkeynes@626
  2455
    check_fpuen();
nkeynes@359
  2456
    load_reg( R_EAX, Rm );
nkeynes@669
  2457
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2458
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2459
    return 2;
nkeynes@359
  2460
:}
nkeynes@359
  2461
LDS.L @Rm+, FPSCR {:  
nkeynes@673
  2462
    COUNT_INST(I_LDSFPSCRM);
nkeynes@626
  2463
    check_fpuen();
nkeynes@359
  2464
    load_reg( R_EAX, Rm );
nkeynes@395
  2465
    check_ralign32( R_EAX );
nkeynes@586
  2466
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2467
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2468
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@669
  2469
    call_func1( sh4_write_fpscr, R_EAX );
nkeynes@417
  2470
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@901
  2471
    return 2;
nkeynes@359
  2472
:}
nkeynes@359
  2473
LDS Rm, FPUL {:  
nkeynes@671
  2474
    COUNT_INST(I_LDS);
nkeynes@626
  2475
    check_fpuen();
nkeynes@359
  2476
    load_reg( R_EAX, Rm );
nkeynes@359
  2477
    store_spreg( R_EAX, R_FPUL );
nkeynes@359
  2478
:}
nkeynes@359
  2479
LDS.L @Rm+, FPUL {:  
nkeynes@671
  2480
    COUNT_INST(I_LDSM);
nkeynes@626
  2481
    check_fpuen();
nkeynes@359
  2482
    load_reg( R_EAX, Rm );
nkeynes@395
  2483
    check_ralign32( R_EAX );
nkeynes@586
  2484
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2485
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2486
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2487
    store_spreg( R_EAX, R_FPUL );
nkeynes@417
  2488
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2489
:}
nkeynes@359
  2490
LDS Rm, MACH {: 
nkeynes@671
  2491
    COUNT_INST(I_LDS);
nkeynes@359
  2492
    load_reg( R_EAX, Rm );
nkeynes@359
  2493
    store_spreg( R_EAX, R_MACH );
nkeynes@359
  2494
:}
nkeynes@359
  2495
LDS.L @Rm+, MACH {:  
nkeynes@671
  2496
    COUNT_INST(I_LDSM);
nkeynes@359
  2497
    load_reg( R_EAX, Rm );
nkeynes@395
  2498
    check_ralign32( R_EAX );
nkeynes@586
  2499
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2500
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2501
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2502
    store_spreg( R_EAX, R_MACH );
nkeynes@417
  2503
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2504
:}
nkeynes@359
  2505
LDS Rm, MACL {:  
nkeynes@671
  2506
    COUNT_INST(I_LDS);
nkeynes@359
  2507
    load_reg( R_EAX, Rm );
nkeynes@359
  2508
    store_spreg( R_EAX, R_MACL );
nkeynes@359
  2509
:}
nkeynes@359
  2510
LDS.L @Rm+, MACL {:  
nkeynes@671
  2511
    COUNT_INST(I_LDSM);
nkeynes@359
  2512
    load_reg( R_EAX, Rm );
nkeynes@395
  2513
    check_ralign32( R_EAX );
nkeynes@586
  2514
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2515
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2516
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2517
    store_spreg( R_EAX, R_MACL );
nkeynes@417
  2518
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2519
:}
nkeynes@359
  2520
LDS Rm, PR {:  
nkeynes@671
  2521
    COUNT_INST(I_LDS);
nkeynes@359
  2522
    load_reg( R_EAX, Rm );
nkeynes@359
  2523
    store_spreg( R_EAX, R_PR );
nkeynes@359
  2524
:}
nkeynes@359
  2525
LDS.L @Rm+, PR {:  
nkeynes@671
  2526
    COUNT_INST(I_LDSM);
nkeynes@359
  2527
    load_reg( R_EAX, Rm );
nkeynes@395
  2528
    check_ralign32( R_EAX );
nkeynes@586
  2529
    MMU_TRANSLATE_READ( R_EAX );
nkeynes@586
  2530
    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
nkeynes@586
  2531
    MEM_READ_LONG( R_EAX, R_EAX );
nkeynes@359
  2532
    store_spreg( R_EAX, R_PR );
nkeynes@417
  2533
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2534
:}
nkeynes@550
  2535
LDTLB {:  
nkeynes@671
  2536
    COUNT_INST(I_LDTLB);
nkeynes@553
  2537
    call_func0( MMU_ldtlb );
nkeynes@875
  2538
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@550
  2539
:}
nkeynes@671
  2540
OCBI @Rn {:
nkeynes@671
  2541
    COUNT_INST(I_OCBI);
nkeynes@671
  2542
:}
nkeynes@671
  2543
OCBP @Rn {:
nkeynes@671
  2544
    COUNT_INST(I_OCBP);
nkeynes@671
  2545
:}
nkeynes@671
  2546
OCBWB @Rn {:
nkeynes@671
  2547
    COUNT_INST(I_OCBWB);
nkeynes@671
  2548
:}
nkeynes@374
  2549
PREF @Rn {:
nkeynes@671
  2550
    COUNT_INST(I_PREF);
nkeynes@374
  2551
    load_reg( R_EAX, Rn );
nkeynes@532
  2552
    MOV_r32_r32( R_EAX, R_ECX );
nkeynes@905
  2553
    AND_imm32_r32( 0xFC000000, R_ECX );
nkeynes@905
  2554
    CMP_imm32_r32( 0xE0000000, R_ECX );
nkeynes@669
  2555
    JNE_rel8(end);
nkeynes@911
  2556
    if( sh4_x86.tlb_on ) {
nkeynes@911
  2557
    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
nkeynes@911
  2558
        TEST_r32_r32( R_EAX, R_EAX );
nkeynes@911
  2559
        JE_exc(-1);
nkeynes@911
  2560
    } else {
nkeynes@911
  2561
    	call_func1( sh4_flush_store_queue, R_EAX );
nkeynes@911
  2562
   	}
nkeynes@380
  2563
    JMP_TARGET(end);
nkeynes@417
  2564
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2565
:}
nkeynes@388
  2566
SLEEP {: 
nkeynes@671
  2567
    COUNT_INST(I_SLEEP);
nkeynes@388
  2568
    check_priv();
nkeynes@388
  2569
    call_func0( sh4_sleep );
nkeynes@417
  2570
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@590
  2571
    sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408
  2572
    return 2;
nkeynes@388
  2573
:}
nkeynes@386
  2574
STC SR, Rn {:
nkeynes@671
  2575
    COUNT_INST(I_STCSR);
nkeynes@386
  2576
    check_priv();
nkeynes@386
  2577
    call_func0(sh4_read_sr);
nkeynes@386
  2578
    store_reg( R_EAX, Rn );
nkeynes@417
  2579
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2580
:}
nkeynes@359
  2581
STC GBR, Rn {:  
nkeynes@671
  2582
    COUNT_INST(I_STC);
nkeynes@359
  2583
    load_spreg( R_EAX, R_GBR );
nkeynes@359
  2584
    store_reg( R_EAX, Rn );
nkeynes@359
  2585
:}
nkeynes@359
  2586
STC VBR, Rn {:  
nkeynes@671
  2587
    COUNT_INST(I_STC);
nkeynes@386
  2588
    check_priv();
nkeynes@359
  2589
    load_spreg( R_EAX, R_VBR );
nkeynes@359
  2590
    store_reg( R_EAX, Rn );
nkeynes@417
  2591
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2592
:}
nkeynes@359
  2593
STC SSR, Rn {:  
nkeynes@671
  2594
    COUNT_INST(I_STC);
nkeynes@386
  2595
    check_priv();
nkeynes@359
  2596
    load_spreg( R_EAX, R_SSR );
nkeynes@359
  2597
    store_reg( R_EAX, Rn );
nkeynes@417
  2598
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2599
:}
nkeynes@359
  2600
STC SPC, Rn {:  
nkeynes@671
  2601
    COUNT_INST(I_STC);
nkeynes@386
  2602
    check_priv();
nkeynes@359
  2603
    load_spreg( R_EAX, R_SPC );
nkeynes@359
  2604
    store_reg( R_EAX, Rn );
nkeynes@417
  2605
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2606
:}
nkeynes@359
  2607
STC SGR, Rn {:  
nkeynes@671
  2608
    COUNT_INST(I_STC);
nkeynes@386
  2609
    check_priv();
nkeynes@359
  2610
    load_spreg( R_EAX, R_SGR );
nkeynes@359
  2611
    store_reg( R_EAX, Rn );
nkeynes@417
  2612
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2613
:}
nkeynes@359
  2614
STC DBR, Rn {:  
nkeynes@671
  2615
    COUNT_INST(I_STC);
nkeynes@386
  2616
    check_priv();
nkeynes@359
  2617
    load_spreg( R_EAX, R_DBR );
nkeynes@359
  2618
    store_reg( R_EAX, Rn );
nkeynes@417
  2619
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2620
:}
nkeynes@374
  2621
STC Rm_BANK, Rn {:
nkeynes@671
  2622
    COUNT_INST(I_STC);
nkeynes@386
  2623
    check_priv();
nkeynes@374
  2624
    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@374
  2625
    store_reg( R_EAX, Rn );
nkeynes@417
  2626
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2627
:}
nkeynes@374
  2628
STC.L SR, @-Rn {:
nkeynes@671
  2629
    COUNT_INST(I_STCSRM);
nkeynes@586
  2630
    check_priv();
nkeynes@586
  2631
    load_reg( R_EAX, Rn );
nkeynes@586
  2632
    check_walign32( R_EAX );
nkeynes@586
  2633
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2634
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@926
  2635
    MOV_r32_esp8( R_EAX, 0 );
nkeynes@395
  2636
    call_func0( sh4_read_sr );
nkeynes@926
  2637
    MOV_r32_r32( R_EAX, R_EDX );
nkeynes@926
  2638
    MOV_esp8_r32( 0, R_EAX );
nkeynes@586
  2639
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@926
  2640
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2641
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2642
:}
nkeynes@359
  2643
STC.L VBR, @-Rn {:  
nkeynes@671
  2644
    COUNT_INST(I_STCM);
nkeynes@586
  2645
    check_priv();
nkeynes@586
  2646
    load_reg( R_EAX, Rn );
nkeynes@586
  2647
    check_walign32( R_EAX );
nkeynes@586
  2648
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2649
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2650
    load_spreg( R_EDX, R_VBR );
nkeynes@586
  2651
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2652
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2653
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2654
:}
nkeynes@359
  2655
STC.L SSR, @-Rn {:  
nkeynes@671
  2656
    COUNT_INST(I_STCM);
nkeynes@586
  2657
    check_priv();
nkeynes@586
  2658
    load_reg( R_EAX, Rn );
nkeynes@586
  2659
    check_walign32( R_EAX );
nkeynes@586
  2660
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2661
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2662
    load_spreg( R_EDX, R_SSR );
nkeynes@586
  2663
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2664
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2665
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2666
:}
nkeynes@416
  2667
STC.L SPC, @-Rn {:
nkeynes@671
  2668
    COUNT_INST(I_STCM);
nkeynes@586
  2669
    check_priv();
nkeynes@586
  2670
    load_reg( R_EAX, Rn );
nkeynes@586
  2671
    check_walign32( R_EAX );
nkeynes@586
  2672
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2673
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2674
    load_spreg( R_EDX, R_SPC );
nkeynes@586
  2675
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2676
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2677
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2678
:}
nkeynes@359
  2679
STC.L SGR, @-Rn {:  
nkeynes@671
  2680
    COUNT_INST(I_STCM);
nkeynes@586
  2681
    check_priv();
nkeynes@586
  2682
    load_reg( R_EAX, Rn );
nkeynes@586
  2683
    check_walign32( R_EAX );
nkeynes@586
  2684
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2685
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2686
    load_spreg( R_EDX, R_SGR );
nkeynes@586
  2687
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2688
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2689
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2690
:}
nkeynes@359
  2691
STC.L DBR, @-Rn {:  
nkeynes@671
  2692
    COUNT_INST(I_STCM);
nkeynes@586
  2693
    check_priv();
nkeynes@586
  2694
    load_reg( R_EAX, Rn );
nkeynes@586
  2695
    check_walign32( R_EAX );
nkeynes@586
  2696
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2697
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2698
    load_spreg( R_EDX, R_DBR );
nkeynes@586
  2699
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2700
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2701
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2702
:}
nkeynes@374
  2703
STC.L Rm_BANK, @-Rn {:  
nkeynes@671
  2704
    COUNT_INST(I_STCM);
nkeynes@586
  2705
    check_priv();
nkeynes@586
  2706
    load_reg( R_EAX, Rn );
nkeynes@586
  2707
    check_walign32( R_EAX );
nkeynes@586
  2708
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2709
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2710
    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
nkeynes@586
  2711
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2712
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2713
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@374
  2714
:}
nkeynes@359
  2715
STC.L GBR, @-Rn {:  
nkeynes@671
  2716
    COUNT_INST(I_STCM);
nkeynes@586
  2717
    load_reg( R_EAX, Rn );
nkeynes@586
  2718
    check_walign32( R_EAX );
nkeynes@586
  2719
    ADD_imm8s_r32( -4, R_EAX );
nkeynes@586
  2720
    MMU_TRANSLATE_WRITE( R_EAX );
nkeynes@586
  2721
    load_spreg( R_EDX, R_GBR );
nkeynes@586
  2722
    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
nkeynes@586
  2723
    MEM_WRITE_LONG( R_EAX, R_EDX );
nkeynes@417
  2724
    sh4_x86.tstate = TSTATE_NONE;
nkeynes@359
  2725
:}
nkeynes@359
  2726
STS FPSCR, Rn {:  
nkeynes@673
  2727
    COUNT_INST(I_STSFPSCR);
nkeynes@626
  2728
    check_fpuen();
nkeynes@359
  2729
    load_spreg( R_EAX, R_FPSCR );
nkeynes@359
  2730
    store_reg( R_EAX, Rn );
nkeynes@359
  2731
:}
nkeynes@359
  2732
STS.L FPSCR, @-Rn {:  
nkeynes@673
  2733
    COUNT_INST(I_STSFPSCRM);
nkeynes@626
  2734